From 594f3d26ea55219fd1855d388477601d4cbb1a28 Mon Sep 17 00:00:00 2001 From: Tejal Kudav Date: Tue, 14 Nov 2017 14:53:09 +0530 Subject: gpu: nvgpu: Update vfe_var interface as per chips_a_23609936 Changes made: 1. Fuse value can now be signed or unsigned. A new boolean added to check if the value is signed or not. 2. Masks added for dependent variable and equations 3. Restructing some data structures as per r384 JIRA NVGPUGV100-39 Change-Id: I7d9d1a55e26a06686f6253dedeb55925a32fd0ad Signed-off-by: Tejal Kudav Reviewed-on: https://git-master.nvidia.com/r/1597761 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Vaikundanathan S Tested-by: Vaikundanathan S Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/ctrl/ctrlperf.h | 66 +++++++++++++++++++++- drivers/gpu/nvgpu/include/nvgpu/bios.h | 3 + .../gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h | 45 ++++----------- drivers/gpu/nvgpu/perf/vfe_var.c | 55 ++++++++++-------- drivers/gpu/nvgpu/perf/vfe_var.h | 12 ++-- 5 files changed, 119 insertions(+), 62 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/ctrl/ctrlperf.h b/drivers/gpu/nvgpu/ctrl/ctrlperf.h index 52ff60c7..477b33d8 100644 --- a/drivers/gpu/nvgpu/ctrl/ctrlperf.h +++ b/drivers/gpu/nvgpu/ctrl/ctrlperf.h @@ -1,7 +1,7 @@ /* * general p state infrastructure * - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -36,4 +36,68 @@ struct ctrl_perf_volt_rail_list { rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS]; }; +union ctrl_perf_vfe_var_single_sensed_fuse_value_data { + int signed_value; + u32 unsigned_value; +}; + +struct ctrl_perf_vfe_var_single_sensed_fuse_value { + bool b_signed; + union ctrl_perf_vfe_var_single_sensed_fuse_value_data data; +}; + +struct ctrl_bios_vfield_register_segment_super { + u8 low_bit; + u8 high_bit; +}; + +struct ctrl_bios_vfield_register_segment_reg { + struct ctrl_bios_vfield_register_segment_super super; + u32 addr; +}; + +struct ctrl_bios_vfield_register_segment_index_reg { + struct ctrl_bios_vfield_register_segment_super super; + u32 addr; + u32 reg_index; + u32 index; +}; + +union ctrl_bios_vfield_register_segment_data { + struct ctrl_bios_vfield_register_segment_reg reg; + struct ctrl_bios_vfield_register_segment_index_reg index_reg; +}; + +struct ctrl_bios_vfield_register_segment { + u8 type; + union ctrl_bios_vfield_register_segment_data data; +}; + +#define NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX 1 + +struct ctrl_perf_vfe_var_single_sensed_fuse_info { + u8 segment_count; + struct ctrl_bios_vfield_register_segment segments[NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX]; +}; + +struct ctrl_perf_vfe_var_single_sensed_fuse_override_info { + u32 fuse_val_override; + u8 b_fuse_regkey_override; +}; + +struct ctrl_perf_vfe_var_single_sensed_fuse_vfield_info { + struct ctrl_perf_vfe_var_single_sensed_fuse_info fuse; + u32 fuse_val_default; + u32 hw_correction_scale; + int hw_correction_offset; + u8 v_field_id; +}; + +struct ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info { + struct ctrl_perf_vfe_var_single_sensed_fuse_info fuse; + u8 ver_expected; + bool b_ver_check; + bool b_use_default_on_ver_check_fail; + u8 v_field_id_ver; +}; #endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h index 191f0dbd..eec057f2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/bios.h +++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h @@ -321,6 +321,9 @@ struct vbios_vfe_3x_var_entry_struct { #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_MASK 0x1000000 #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_SHIFT 24 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VALUE_SIGNED_INTEGER_MASK 0x2000000 +#define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VALUE_SIGNED_INTEGER_SHIFT 25 + #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_YES 0x00000001 #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_NO 0x00000000 #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_MASK 0xFF diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h index 18568a4d..7764c72a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -24,11 +24,11 @@ #include "gpmuifbios.h" #include "gpmuifboardobj.h" +#include "ctrl/ctrlperf.h" #define CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT 0x03 #define NV_PMU_PERF_RPC_VFE_EQU_EVAL_VAR_COUNT_MAX 2 #define NV_PMU_PERF_RPC_VFE_EQU_MONITOR_COUNT_MAX 16 -#define NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX 1 struct nv_pmu_perf_vfe_var_value { u8 var_type; @@ -66,8 +66,8 @@ struct nv_pmu_perf_vfe_var_get_status_super { struct nv_pmu_perf_vfe_var_single_sensed_fuse_get_status { struct nv_pmu_perf_vfe_var_get_status_super super; - u32 fuse_value_integer; - u32 fuse_value_hw_integer; + struct ctrl_perf_vfe_var_single_sensed_fuse_value fuse_value_integer; + struct ctrl_perf_vfe_var_single_sensed_fuse_value fuse_value_hw_integer; u8 fuse_version; bool b_version_check_failed; }; @@ -84,6 +84,8 @@ struct nv_pmu_vfe_var { struct nv_pmu_boardobj super; u32 out_range_min; u32 out_range_max; + struct ctrl_boardobjgrp_mask_e32 mask_dependent_vars; + struct ctrl_boardobjgrp_mask_e255 mask_dependent_equs; }; struct nv_pmu_vfe_var_derived { @@ -116,38 +118,13 @@ struct nv_pmu_vfe_var_single_sensed { struct nv_pmu_vfe_var_single super; }; -struct nv_pmu_vfe_var_single_sensed_fuse_info { - u8 segment_count; - union nv_pmu_bios_vfield_register_segment segments[ - NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX]; -}; - -struct nv_pmu_vfe_var_single_sensed_fuse_vfield_info { - struct nv_pmu_vfe_var_single_sensed_fuse_info fuse; - u32 fuse_val_default; - int hw_correction_scale; - int hw_correction_offset; - u8 v_field_id; -}; - -struct nv_pmu_vfe_var_single_sensed_fuse_ver_vfield_info { - struct nv_pmu_vfe_var_single_sensed_fuse_info fuse; - u8 ver_expected; - bool b_ver_check; - bool b_use_default_on_ver_check_fail; - u8 v_field_id_ver; -}; - -struct nv_pmu_vfe_var_single_sensed_fuse_override_info { - u32 fuse_val_override; - bool b_fuse_regkey_override; -}; - struct nv_pmu_vfe_var_single_sensed_fuse { struct nv_pmu_vfe_var_single_sensed super; - struct nv_pmu_vfe_var_single_sensed_fuse_override_info override_info; - struct nv_pmu_vfe_var_single_sensed_fuse_vfield_info vfield_info; - struct nv_pmu_vfe_var_single_sensed_fuse_ver_vfield_info vfield_ver_info; + struct ctrl_perf_vfe_var_single_sensed_fuse_override_info override_info; + struct ctrl_perf_vfe_var_single_sensed_fuse_vfield_info vfield_info; + struct ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info vfield_ver_info; + struct ctrl_perf_vfe_var_single_sensed_fuse_value fuse_val_default; + bool b_fuse_value_signed; }; struct nv_pmu_vfe_var_single_sensed_temp { diff --git a/drivers/gpu/nvgpu/perf/vfe_var.c b/drivers/gpu/nvgpu/perf/vfe_var.c index c46747c9..a44c39ad 100644 --- a/drivers/gpu/nvgpu/perf/vfe_var.c +++ b/drivers/gpu/nvgpu/perf/vfe_var.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -29,6 +29,7 @@ #include "boardobj/boardobjgrp_e32.h" #include "ctrl/ctrlclk.h" #include "ctrl/ctrlvolt.h" +#include "ctrl/ctrlperf.h" static u32 devinit_get_vfe_var_table(struct gk20a *g, struct vfe_vars *pvarobjs); @@ -183,7 +184,7 @@ static u32 dev_init_get_vfield_info(struct gk20a *g, struct vfield_reg_entry vregentry; struct vfield_header vheader; struct vfield_entry ventry; - union nv_pmu_bios_vfield_register_segment *psegment = NULL; + struct ctrl_bios_vfield_register_segment *psegment = NULL; u8 *psegmentcount = NULL; u32 status = 0; @@ -254,32 +255,34 @@ static u32 dev_init_get_vfield_info(struct gk20a *g, continue; } - psegment->super.high_bit = (u8)(VFIELD_BIT_STOP(ventry)); - psegment->super.low_bit = (u8)(VFIELD_BIT_START(ventry)); switch (VFIELD_CODE((&vregentry))) { case NV_VFIELD_DESC_CODE_REG: - psegment->reg.super.type = + psegment->type = NV_PMU_BIOS_VFIELD_DESC_CODE_REG; - psegment->reg.addr = vregentry.reg; + psegment->data.reg.addr = vregentry.reg; + psegment->data.reg.super.high_bit = (u8)(VFIELD_BIT_STOP(ventry)); + psegment->data.reg.super.low_bit = (u8)(VFIELD_BIT_START(ventry)); break; case NV_VFIELD_DESC_CODE_INDEX_REG: - psegment->index_reg.super.type = + psegment->type = NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG; - psegment->index_reg.addr = vregentry.reg; - psegment->index_reg.index = vregentry.index; - psegment->index_reg.reg_index = vregentry.reg_index; + psegment->data.index_reg.addr = vregentry.reg; + psegment->data.index_reg.index = vregentry.index; + psegment->data.index_reg.reg_index = vregentry.reg_index; + psegment->data.index_reg.super.high_bit = (u8)(VFIELD_BIT_STOP(ventry)); + psegment->data.index_reg.super.low_bit = (u8)(VFIELD_BIT_START(ventry)); break; default: - psegment->super.type = + psegment->type = NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID; status = -EINVAL; goto done; } if (VFIELD_SIZE((&vregentry)) != NV_VFIELD_DESC_SIZE_DWORD) { - psegment->super.type = + psegment->type = NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID; return -EINVAL; } @@ -287,7 +290,6 @@ static u32 dev_init_get_vfield_info(struct gk20a *g, } done: - return status; } @@ -310,7 +312,12 @@ static u32 _vfe_var_pmudatainit_super(struct gk20a *g, pset->out_range_min = pvfe_var->out_range_min; pset->out_range_max = pvfe_var->out_range_max; - + status = boardobjgrpmask_export(&pvfe_var->mask_dependent_vars.super, + pvfe_var->mask_dependent_vars.super.bitcount, + &pset->mask_dependent_vars.super); + status = boardobjgrpmask_export(&pvfe_var->mask_dependent_equs.super, + pvfe_var->mask_dependent_equs.super.bitcount, + &pset->mask_dependent_equs.super); return status; } @@ -336,7 +343,8 @@ static u32 vfe_var_construct_super(struct gk20a *g, pvfevar->out_range_min = ptmpvar->out_range_min; pvfevar->out_range_max = ptmpvar->out_range_max; pvfevar->b_is_dynamic_valid = false; - + status = boardobjgrpmask_e32_init(&pvfevar->mask_dependent_vars, NULL); + status = boardobjgrpmask_e255_init(&pvfevar->mask_dependent_equs, NULL); gk20a_dbg_info(""); return status; @@ -583,16 +591,17 @@ static u32 _vfe_var_pmudatainit_single_sensed_fuse(struct gk20a *g, ppmudata; memcpy(&pset->vfield_info, &pvfe_var_single_sensed_fuse->vfield_info, - sizeof(struct nv_pmu_vfe_var_single_sensed_fuse_vfield_info)); + sizeof(struct ctrl_perf_vfe_var_single_sensed_fuse_vfield_info)); memcpy(&pset->vfield_ver_info, &pvfe_var_single_sensed_fuse->vfield_ver_info, - sizeof(struct nv_pmu_vfe_var_single_sensed_fuse_ver_vfield_info)); + sizeof(struct ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info)); memcpy(&pset->override_info, &pvfe_var_single_sensed_fuse->override_info, - sizeof(struct nv_pmu_vfe_var_single_sensed_fuse_override_info)); + sizeof(struct ctrl_perf_vfe_var_single_sensed_fuse_override_info)); + pset->b_fuse_value_signed = pvfe_var_single_sensed_fuse->b_fuse_value_signed; return status; } @@ -661,7 +670,8 @@ static u32 vfe_var_construct_single_sensed_fuse(struct gk20a *g, pvfevar->vfield_ver_info.b_use_default_on_ver_check_fail = ptmpvar->vfield_ver_info.b_use_default_on_ver_check_fail; pvfevar->b_version_check_done = false; - + pvfevar->b_fuse_value_signed = + ptmpvar->b_fuse_value_signed; pvfevar->super.super.super.b_is_dynamic = false; pvfevar->super.super.super.b_is_dynamic_valid = true; @@ -899,7 +909,6 @@ static u32 devinit_get_vfe_var_table(struct gk20a *g, /* Read table entries*/ vfevars_tbl_entry_ptr = vfevars_tbl_ptr + vfevars_tbl_header.header_size; - for (index = 0; index < vfevars_tbl_header.vfe_var_entry_count; index++) { @@ -910,9 +919,6 @@ static u32 devinit_get_vfe_var_table(struct gk20a *g, var_data.super.out_range_min = var.out_range_min; var_data.super.out_range_max = var.out_range_max; - var_data.super.out_range_min = var.out_range_min; - var_data.super.out_range_max = var.out_range_max; - switch ((u8)var.type) { case VBIOS_VFE_3X_VAR_ENTRY_TYPE_DISABLED: continue; @@ -955,6 +961,9 @@ static u32 devinit_get_vfe_var_table(struct gk20a *g, (BIOS_GET_FIELD(var.param0, VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL) && VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_YES); + var_data.single_sensed_fuse.b_fuse_value_signed = + (u8)BIOS_GET_FIELD(var.param0, + VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VALUE_SIGNED_INTEGER); var_data.single_sensed_fuse.vfield_info.fuse_val_default = var.param1; if (szfmt >= VBIOS_VFE_3X_VAR_ENTRY_SIZE_19) { diff --git a/drivers/gpu/nvgpu/perf/vfe_var.h b/drivers/gpu/nvgpu/perf/vfe_var.h index c443bc4b..3364f994 100644 --- a/drivers/gpu/nvgpu/perf/vfe_var.h +++ b/drivers/gpu/nvgpu/perf/vfe_var.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -40,6 +40,8 @@ struct vfe_var { struct boardobj super; u32 out_range_min; u32 out_range_max; + struct boardobjgrpmask_e32 mask_dependent_vars; + struct boardobjgrpmask_e255 mask_dependent_equs; bool b_is_dynamic_valid; bool b_is_dynamic; }; @@ -85,9 +87,11 @@ struct vfe_var_single_sensed { struct vfe_var_single_sensed_fuse { struct vfe_var_single_sensed super; - struct nv_pmu_vfe_var_single_sensed_fuse_override_info override_info; - struct nv_pmu_vfe_var_single_sensed_fuse_vfield_info vfield_info; - struct nv_pmu_vfe_var_single_sensed_fuse_ver_vfield_info vfield_ver_info; + struct ctrl_perf_vfe_var_single_sensed_fuse_override_info override_info; + struct ctrl_perf_vfe_var_single_sensed_fuse_vfield_info vfield_info; + struct ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info vfield_ver_info; + struct ctrl_perf_vfe_var_single_sensed_fuse_value fuse_val_default; + bool b_fuse_value_signed; u32 fuse_value_integer; u32 fuse_value_hw_integer; u8 fuse_version; -- cgit v1.2.2