From 3ec909036af46fbe582c50e486beb2bded42b645 Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Tue, 25 Oct 2016 16:27:19 +0530 Subject: gpu: nvgpu: Add PMU thermal RPC for WARN_TEMP Added PMU thermal slct RPC handling for WARN_TEMP threshold configuration. JIRA DNVGPU-130 Change-Id: I5011db5f08476516f72722e639838e968e7e60dd Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1242132 (cherry picked from commit 6e87a23ca04be435107da801c15f7b55a1f45e8b) Reviewed-on: http://git-master/r/1246211 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gk20a.h | 3 ++ drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 3 ++ drivers/gpu/nvgpu/pmuif/gpmuiftherm.h | 71 +++++++++++++++++++++++++++++++++++ 3 files changed, 77 insertions(+) create mode 100644 drivers/gpu/nvgpu/pmuif/gpmuiftherm.h (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 43f673f5..7699cd53 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -969,6 +969,9 @@ struct gk20a { /* PCIe power states. */ bool xve_l0s; bool xve_l1; + + /* Current warning temp in sfxp24.8 */ + s32 curr_warn_temp; }; static inline unsigned long gk20a_get_gr_idle_timeout(struct gk20a *g) diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index c31bd187..6ec0067b 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h @@ -28,6 +28,7 @@ #include "pmuif/gpmuifperf.h" #include "pmuif/gpmuifpmgr.h" #include "pmuif/gpmuifvolt.h" +#include "pmuif/gpmuiftherm.h" /* defined by pmu hw spec */ #define GK20A_PMU_VA_SIZE (512 * 1024 * 1024) @@ -365,6 +366,7 @@ struct pmu_cmd { struct nv_pmu_volt_cmd volt; struct nv_pmu_clk_cmd clk; struct nv_pmu_pmgr_cmd pmgr; + struct nv_pmu_therm_cmd therm; } cmd; }; @@ -382,6 +384,7 @@ struct pmu_msg { struct nv_pmu_volt_msg volt; struct nv_pmu_clk_msg clk; struct nv_pmu_pmgr_msg pmgr; + struct nv_pmu_therm_msg therm; } msg; }; diff --git a/drivers/gpu/nvgpu/pmuif/gpmuiftherm.h b/drivers/gpu/nvgpu/pmuif/gpmuiftherm.h new file mode 100644 index 00000000..9c10e93c --- /dev/null +++ b/drivers/gpu/nvgpu/pmuif/gpmuiftherm.h @@ -0,0 +1,71 @@ +/* +* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms and conditions of the GNU General Public License, +* version 2, as published by the Free Software Foundation. +* +* This program is distributed in the hope it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +*/ + +#ifndef _GPMUIFTHERM_H_ +#define _GPMUIFTHERM_H_ + +#include "gk20a/pmu_common.h" + +#define NV_PMU_THERM_CMD_ID_RPC 0x00000002 +#define NV_PMU_THERM_MSG_ID_RPC 0x00000002 +#define NV_PMU_THERM_RPC_ID_SLCT_EVENT_TEMP_TH_SET 0x00000006 +#define NV_PMU_THERM_EVENT_THERMAL_1 0x00000004 + +struct nv_pmu_therm_rpc_slct_event_temp_th_set { + s32 temp_threshold; + u8 event_id; + flcn_status flcn_stat; +}; + +struct nv_pmu_therm_rpc { + u8 function; + bool b_supported; + union { + struct nv_pmu_therm_rpc_slct_event_temp_th_set slct_event_temp_th_set; + } params; +}; + +struct nv_pmu_therm_cmd_rpc { + u8 cmd_type; + u8 pad[3]; + struct nv_pmu_allocation request; +}; + +#define NV_PMU_THERM_CMD_RPC_ALLOC_OFFSET \ + offsetof(struct nv_pmu_therm_cmd_rpc, request) + +struct nv_pmu_therm_cmd { + union { + u8 cmd_type; + struct nv_pmu_therm_cmd_rpc rpc; + }; +}; + +struct nv_pmu_therm_msg_rpc { + u8 msg_type; + u8 rsvd[3]; + struct nv_pmu_allocation response; +}; + +#define NV_PMU_THERM_MSG_RPC_ALLOC_OFFSET \ + offsetof(struct nv_pmu_therm_msg_rpc, response) + +struct nv_pmu_therm_msg { + union { + u8 msg_type; + struct nv_pmu_therm_msg_rpc rpc; + }; +}; + +#endif + -- cgit v1.2.2