From 39727398230bdb0fb01d9aa54e4cc572f6d39299 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Wed, 24 May 2017 13:27:28 -0700 Subject: gpu: nvgpu: gv11b: No need to set init val for fb & pbdma timeout fb_timeout and pbdma_timeout values are already set by h/w to init values. No need to reinitialize. JIRA GPUT19X-22 Change-Id: If6f1111f58940d51e53f028b046c42fa852221ee Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1493458 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 38a402dc..b6691db5 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" @@ -1122,19 +1123,13 @@ static int gv11b_init_fifo_reset_enable_hw(struct gk20a *g) timeout = gk20a_readl(g, fifo_fb_timeout_r()); - timeout = set_field(timeout, fifo_fb_timeout_period_m(), - fifo_fb_timeout_period_init_f()); - gk20a_dbg_info("fifo_fb_timeout reg val = 0x%08x", timeout); - gk20a_writel(g, fifo_fb_timeout_r(), timeout); - - /* write pbdma timeout value */ + nvgpu_log_info(g, "fifo_fb_timeout reg val = 0x%08x", timeout); for (i = 0; i < host_num_pbdma; i++) { timeout = gk20a_readl(g, pbdma_timeout_r(i)); - timeout = set_field(timeout, pbdma_timeout_period_m(), - pbdma_timeout_period_init_f()); - gk20a_dbg_info("pbdma_timeout reg val = 0x%08x", timeout); - gk20a_writel(g, pbdma_timeout_r(i), timeout); + nvgpu_log_info(g, "pbdma_timeout reg val = 0x%08x", + timeout); } + /* clear and enable pbdma interrupt */ for (i = 0; i < host_num_pbdma; i++) { gk20a_writel(g, pbdma_intr_0_r(i), 0xFFFFFFFF); -- cgit v1.2.2