From 3885fe099af0bda910ac8ee64f2cd1a5bbea3ab0 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Mon, 6 Feb 2017 16:49:24 +0530 Subject: gpu: nvgpu: move pmuif/* to drivers/gpu/nvgpu/include/nvgpu MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Moved pmuif/* headers to drivers/gpu/nvgpu/include/nvgpu folder to support cross platform feature implementation. Made changes to files which accessed “include pmuif/*” to reflect pmuif/* movement changes. Deleted includes of gk20a.h/pmu_gk20a.h from pmuif/*.h files. Jira NVGPU-19 Change-Id: Iace4e107c24bdaff08a407eae3b147959173e485 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1299823 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/boardobj/boardobj.c | 4 +- drivers/gpu/nvgpu/boardobj/boardobj.h | 4 +- drivers/gpu/nvgpu/boardobj/boardobjgrp.h | 3 +- drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.c | 3 +- drivers/gpu/nvgpu/boardobj/boardobjgrp_e32.c | 3 +- drivers/gpu/nvgpu/clk/clk.c | 5 +- drivers/gpu/nvgpu/clk/clk_domain.c | 4 +- drivers/gpu/nvgpu/clk/clk_domain.h | 4 +- drivers/gpu/nvgpu/clk/clk_fll.c | 4 +- drivers/gpu/nvgpu/clk/clk_fll.h | 4 +- drivers/gpu/nvgpu/clk/clk_freq_controller.c | 4 +- drivers/gpu/nvgpu/clk/clk_mclk.c | 6 +- drivers/gpu/nvgpu/clk/clk_prog.c | 2 - drivers/gpu/nvgpu/clk/clk_prog.h | 4 +- drivers/gpu/nvgpu/clk/clk_vf_point.c | 4 +- drivers/gpu/nvgpu/clk/clk_vf_point.h | 4 +- drivers/gpu/nvgpu/clk/clk_vin.c | 3 +- drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 2 +- drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h | 104 +++++ drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_ap.h | 247 +++++++++++ drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h | 121 ++++++ .../gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h | 178 ++++++++ drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h | 311 ++++++++++++++ .../gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg_rppg.h | 101 +++++ drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h | 215 ++++++++++ drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifbios.h | 41 ++ .../gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h | 195 +++++++++ drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h | 455 +++++++++++++++++++++ drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h | 117 ++++++ .../gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h | 220 ++++++++++ drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifpmgr.h | 434 ++++++++++++++++++++ drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifseq.h | 73 ++++ .../gpu/nvgpu/include/nvgpu/pmuif/gpmuiftherm.h | 93 +++++ .../nvgpu/include/nvgpu/pmuif/gpmuifthermsensor.h | 74 ++++ drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h | 326 +++++++++++++++ .../nvgpu/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h | 89 ++++ drivers/gpu/nvgpu/lpwr/rppg.c | 2 +- drivers/gpu/nvgpu/perf/perf.c | 4 +- drivers/gpu/nvgpu/perf/perf.h | 3 +- drivers/gpu/nvgpu/perf/vfe_equ.c | 5 +- drivers/gpu/nvgpu/perf/vfe_equ.h | 5 +- drivers/gpu/nvgpu/perf/vfe_var.c | 3 - drivers/gpu/nvgpu/perf/vfe_var.h | 5 +- drivers/gpu/nvgpu/pmgr/pmgrpmu.c | 5 +- drivers/gpu/nvgpu/pmgr/pwrdev.c | 4 +- drivers/gpu/nvgpu/pmgr/pwrdev.h | 4 +- drivers/gpu/nvgpu/pmgr/pwrmonitor.c | 4 +- drivers/gpu/nvgpu/pmgr/pwrmonitor.h | 4 +- drivers/gpu/nvgpu/pmgr/pwrpolicy.c | 2 - drivers/gpu/nvgpu/pmgr/pwrpolicy.h | 4 +- drivers/gpu/nvgpu/pmuif/gpmuif_acr.h | 104 ----- drivers/gpu/nvgpu/pmuif/gpmuif_ap.h | 247 ----------- drivers/gpu/nvgpu/pmuif/gpmuif_cmn.h | 121 ------ drivers/gpu/nvgpu/pmuif/gpmuif_perfmon.h | 178 -------- drivers/gpu/nvgpu/pmuif/gpmuif_pg.h | 311 -------------- drivers/gpu/nvgpu/pmuif/gpmuif_pg_rppg.h | 101 ----- drivers/gpu/nvgpu/pmuif/gpmuif_pmu.h | 215 ---------- drivers/gpu/nvgpu/pmuif/gpmuifbios.h | 41 -- drivers/gpu/nvgpu/pmuif/gpmuifboardobj.h | 195 --------- drivers/gpu/nvgpu/pmuif/gpmuifclk.h | 455 --------------------- drivers/gpu/nvgpu/pmuif/gpmuifperf.h | 117 ------ drivers/gpu/nvgpu/pmuif/gpmuifperfvfe.h | 220 ---------- drivers/gpu/nvgpu/pmuif/gpmuifpmgr.h | 434 -------------------- drivers/gpu/nvgpu/pmuif/gpmuifseq.h | 73 ---- drivers/gpu/nvgpu/pmuif/gpmuiftherm.h | 93 ----- drivers/gpu/nvgpu/pmuif/gpmuifthermsensor.h | 74 ---- drivers/gpu/nvgpu/pmuif/gpmuifvolt.h | 326 --------------- drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h | 86 ---- drivers/gpu/nvgpu/therm/thrmchannel.c | 5 +- drivers/gpu/nvgpu/therm/thrmdev.c | 5 +- drivers/gpu/nvgpu/therm/thrmpmu.c | 5 +- drivers/gpu/nvgpu/volt/volt_dev.c | 5 +- drivers/gpu/nvgpu/volt/volt_pmu.c | 6 +- drivers/gpu/nvgpu/volt/volt_policy.c | 5 +- drivers/gpu/nvgpu/volt/volt_rail.c | 5 +- 75 files changed, 3451 insertions(+), 3491 deletions(-) create mode 100644 drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_ap.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg_rppg.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifbios.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifpmgr.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifseq.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuiftherm.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifthermsensor.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h create mode 100644 drivers/gpu/nvgpu/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h delete mode 100644 drivers/gpu/nvgpu/pmuif/gpmuif_acr.h delete mode 100644 drivers/gpu/nvgpu/pmuif/gpmuif_ap.h delete mode 100644 drivers/gpu/nvgpu/pmuif/gpmuif_cmn.h delete mode 100644 drivers/gpu/nvgpu/pmuif/gpmuif_perfmon.h delete mode 100644 drivers/gpu/nvgpu/pmuif/gpmuif_pg.h delete mode 100644 drivers/gpu/nvgpu/pmuif/gpmuif_pg_rppg.h delete mode 100644 drivers/gpu/nvgpu/pmuif/gpmuif_pmu.h delete mode 100644 drivers/gpu/nvgpu/pmuif/gpmuifbios.h delete mode 100644 drivers/gpu/nvgpu/pmuif/gpmuifboardobj.h delete mode 100644 drivers/gpu/nvgpu/pmuif/gpmuifclk.h delete mode 100644 drivers/gpu/nvgpu/pmuif/gpmuifperf.h delete mode 100644 drivers/gpu/nvgpu/pmuif/gpmuifperfvfe.h delete mode 100644 drivers/gpu/nvgpu/pmuif/gpmuifpmgr.h delete mode 100644 drivers/gpu/nvgpu/pmuif/gpmuifseq.h delete mode 100644 drivers/gpu/nvgpu/pmuif/gpmuiftherm.h delete mode 100644 drivers/gpu/nvgpu/pmuif/gpmuifthermsensor.h delete mode 100644 drivers/gpu/nvgpu/pmuif/gpmuifvolt.h delete mode 100644 drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/boardobj/boardobj.c b/drivers/gpu/nvgpu/boardobj/boardobj.c index 6cd3e2b1..0fa8f6b6 100644 --- a/drivers/gpu/nvgpu/boardobj/boardobj.c +++ b/drivers/gpu/nvgpu/boardobj/boardobj.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,8 +17,6 @@ #include #include "boardobj.h" #include "ctrl/ctrlboardobj.h" -#include "pmuif/gpmuifboardobj.h" - u32 boardobj_construct_super(struct gk20a *g, struct boardobj **ppboardobj, u16 size, void *args) diff --git a/drivers/gpu/nvgpu/boardobj/boardobj.h b/drivers/gpu/nvgpu/boardobj/boardobj.h index 3d437a82..138b3acc 100644 --- a/drivers/gpu/nvgpu/boardobj/boardobj.h +++ b/drivers/gpu/nvgpu/boardobj/boardobj.h @@ -1,5 +1,5 @@ /* -* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. +* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -20,7 +20,7 @@ struct boardobj; #include "gk20a/gk20a.h" #include "gk20a/pmu_gk20a.h" #include "ctrl/ctrlboardobj.h" -#include "pmuif/gpmuifboardobj.h" +#include /* * check whether the specified BOARDOBJ object implements the queried diff --git a/drivers/gpu/nvgpu/boardobj/boardobjgrp.h b/drivers/gpu/nvgpu/boardobj/boardobjgrp.h index 303c9288..f41ae48e 100644 --- a/drivers/gpu/nvgpu/boardobj/boardobjgrp.h +++ b/drivers/gpu/nvgpu/boardobj/boardobjgrp.h @@ -1,5 +1,5 @@ /* -* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. +* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -23,7 +23,6 @@ struct boardobjgrp; #include "ctrl/ctrlboardobj.h" #include "boardobj.h" #include "boardobjgrpmask.h" -#include "pmuif/gpmuifboardobj.h" /* * Board Object Group destructor. diff --git a/drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.c b/drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.c index a56dca9b..2510f636 100644 --- a/drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.c +++ b/drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.c @@ -1,5 +1,5 @@ /* -* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. +* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,7 +15,6 @@ #include "boardobj.h" #include "boardobjgrp_e255.h" #include "ctrl/ctrlboardobj.h" -#include "pmuif/gpmuifboardobj.h" #include "boardobjgrp.h" #include "boardobjgrpmask.h" diff --git a/drivers/gpu/nvgpu/boardobj/boardobjgrp_e32.c b/drivers/gpu/nvgpu/boardobj/boardobjgrp_e32.c index 95610aba..70b3c8f0 100644 --- a/drivers/gpu/nvgpu/boardobj/boardobjgrp_e32.c +++ b/drivers/gpu/nvgpu/boardobj/boardobjgrp_e32.c @@ -1,5 +1,5 @@ /* -* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. +* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,7 +16,6 @@ #include "boardobjgrp.h" #include "boardobjgrp_e32.h" #include "ctrl/ctrlboardobj.h" -#include "pmuif/gpmuifboardobj.h" #include "boardobjgrpmask.h" diff --git a/drivers/gpu/nvgpu/clk/clk.c b/drivers/gpu/nvgpu/clk/clk.c index ecd53c02..e809b5e9 100644 --- a/drivers/gpu/nvgpu/clk/clk.c +++ b/drivers/gpu/nvgpu/clk/clk.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -13,8 +13,7 @@ #include "gk20a/gk20a.h" #include "clk.h" -#include "pmuif/gpmuifclk.h" -#include "pmuif/gpmuifvolt.h" +#include #include "ctrl/ctrlclk.h" #include "ctrl/ctrlvolt.h" #include "volt/volt.h" diff --git a/drivers/gpu/nvgpu/clk/clk_domain.c b/drivers/gpu/nvgpu/clk/clk_domain.c index 892437de..b53d3708 100644 --- a/drivers/gpu/nvgpu/clk/clk_domain.c +++ b/drivers/gpu/nvgpu/clk/clk_domain.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -18,8 +18,6 @@ #include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" -#include "pmuif/gpmuifboardobj.h" -#include "pmuif/gpmuifclk.h" #include "gm206/bios_gm206.h" #include "ctrl/ctrlclk.h" #include "ctrl/ctrlvolt.h" diff --git a/drivers/gpu/nvgpu/clk/clk_domain.h b/drivers/gpu/nvgpu/clk/clk_domain.h index 443e1c4c..532b7ca5 100644 --- a/drivers/gpu/nvgpu/clk/clk_domain.h +++ b/drivers/gpu/nvgpu/clk/clk_domain.h @@ -1,5 +1,5 @@ /* -* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. +* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,7 +16,7 @@ #include "ctrl/ctrlclk.h" #include "ctrl/ctrlboardobj.h" -#include "pmuif/gpmuifclk.h" +#include #include "boardobj/boardobjgrp_e32.h" #include "boardobj/boardobjgrpmask.h" diff --git a/drivers/gpu/nvgpu/clk/clk_fll.c b/drivers/gpu/nvgpu/clk/clk_fll.c index d83f3e15..91cd0e20 100644 --- a/drivers/gpu/nvgpu/clk/clk_fll.c +++ b/drivers/gpu/nvgpu/clk/clk_fll.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,8 +17,6 @@ #include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" -#include "pmuif/gpmuifboardobj.h" -#include "pmuif/gpmuifclk.h" #include "gm206/bios_gm206.h" #include "ctrl/ctrlclk.h" #include "ctrl/ctrlvolt.h" diff --git a/drivers/gpu/nvgpu/clk/clk_fll.h b/drivers/gpu/nvgpu/clk/clk_fll.h index 06872f48..89415b4b 100644 --- a/drivers/gpu/nvgpu/clk/clk_fll.h +++ b/drivers/gpu/nvgpu/clk/clk_fll.h @@ -1,5 +1,5 @@ /* -* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. +* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -14,7 +14,7 @@ #ifndef _CLKFLL_H_ #define _CLKFLL_H_ -#include "pmuif/gpmuifclk.h" +#include #include "boardobj/boardobjgrp_e32.h" #include "boardobj/boardobjgrpmask.h" diff --git a/drivers/gpu/nvgpu/clk/clk_freq_controller.c b/drivers/gpu/nvgpu/clk/clk_freq_controller.c index 17f79168..6fa2db5a 100644 --- a/drivers/gpu/nvgpu/clk/clk_freq_controller.c +++ b/drivers/gpu/nvgpu/clk/clk_freq_controller.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -19,8 +19,6 @@ #include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" -#include "pmuif/gpmuifboardobj.h" -#include "pmuif/gpmuifclk.h" #include "gm206/bios_gm206.h" #include "ctrl/ctrlclk.h" #include "ctrl/ctrlvolt.h" diff --git a/drivers/gpu/nvgpu/clk/clk_mclk.c b/drivers/gpu/nvgpu/clk/clk_mclk.c index 0f191b6f..479fbb0e 100644 --- a/drivers/gpu/nvgpu/clk/clk_mclk.c +++ b/drivers/gpu/nvgpu/clk/clk_mclk.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,9 +15,7 @@ #include "gk20a/gk20a.h" #include "gk20a/pmu_gk20a.h" - -#include "pmuif/gpmuifseq.h" - +#include #include "gm206/bios_gm206.h" #include "include/bios.h" diff --git a/drivers/gpu/nvgpu/clk/clk_prog.c b/drivers/gpu/nvgpu/clk/clk_prog.c index 4135f767..38654b66 100644 --- a/drivers/gpu/nvgpu/clk/clk_prog.c +++ b/drivers/gpu/nvgpu/clk/clk_prog.c @@ -18,8 +18,6 @@ #include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" -#include "pmuif/gpmuifboardobj.h" -#include "pmuif/gpmuifclk.h" #include "gm206/bios_gm206.h" #include "ctrl/ctrlclk.h" #include "ctrl/ctrlvolt.h" diff --git a/drivers/gpu/nvgpu/clk/clk_prog.h b/drivers/gpu/nvgpu/clk/clk_prog.h index 541f04cb..e392870b 100644 --- a/drivers/gpu/nvgpu/clk/clk_prog.h +++ b/drivers/gpu/nvgpu/clk/clk_prog.h @@ -1,5 +1,5 @@ /* -* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. +* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,7 +15,7 @@ #define _CLKPROG_H_ #include "ctrl/ctrlclk.h" #include "ctrl/ctrlboardobj.h" -#include "pmuif/gpmuifclk.h" +#include #include "boardobj/boardobjgrp_e32.h" #include "boardobj/boardobjgrp_e255.h" #include "boardobj/boardobjgrpmask.h" diff --git a/drivers/gpu/nvgpu/clk/clk_vf_point.c b/drivers/gpu/nvgpu/clk/clk_vf_point.c index 4fde7226..58eeb6c2 100644 --- a/drivers/gpu/nvgpu/clk/clk_vf_point.c +++ b/drivers/gpu/nvgpu/clk/clk_vf_point.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,8 +17,6 @@ #include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" -#include "pmuif/gpmuifboardobj.h" -#include "pmuif/gpmuifclk.h" #include "gm206/bios_gm206.h" #include "ctrl/ctrlclk.h" #include "ctrl/ctrlvolt.h" diff --git a/drivers/gpu/nvgpu/clk/clk_vf_point.h b/drivers/gpu/nvgpu/clk/clk_vf_point.h index 15920066..8c4fdecd 100644 --- a/drivers/gpu/nvgpu/clk/clk_vf_point.h +++ b/drivers/gpu/nvgpu/clk/clk_vf_point.h @@ -1,5 +1,5 @@ /* -* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. +* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,7 +15,7 @@ #define _CLKVFPOINT_H_ #include "ctrl/ctrlclk.h" #include "ctrl/ctrlboardobj.h" -#include "pmuif/gpmuifclk.h" +#include #include "boardobj/boardobjgrp_e32.h" #include "boardobj/boardobjgrpmask.h" diff --git a/drivers/gpu/nvgpu/clk/clk_vin.c b/drivers/gpu/nvgpu/clk/clk_vin.c index 1ababe55..13358335 100644 --- a/drivers/gpu/nvgpu/clk/clk_vin.c +++ b/drivers/gpu/nvgpu/clk/clk_vin.c @@ -18,8 +18,7 @@ #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" -#include "pmuif/gpmuifboardobj.h" -#include "pmuif/gpmuifclk.h" +#include #include "ctrl/ctrlvolt.h" diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 47c2a4b3..e4513457 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h @@ -23,7 +23,7 @@ #include #include -#include "pmuif/nvgpu_gpmu_cmdif.h" +#include /* defined by pmu hw spec */ #define GK20A_PMU_VA_SIZE (512 * 1024 * 1024) diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h new file mode 100644 index 00000000..440ffbaa --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _GPMUIFACR_H_ +#define _GPMUIFACR_H_ + +/* ACR Commands/Message structures */ + +enum { + PMU_ACR_CMD_ID_INIT_WPR_REGION = 0x0, + PMU_ACR_CMD_ID_BOOTSTRAP_FALCON, + PMU_ACR_CMD_ID_RESERVED, + PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS, +}; + +/* + * Initializes the WPR region details + */ +struct pmu_acr_cmd_init_wpr_details { + u8 cmd_type; + u32 regionid; + u32 wproffset; + +}; + +/* + * falcon ID to bootstrap + */ +struct pmu_acr_cmd_bootstrap_falcon { + u8 cmd_type; + u32 flags; + u32 falconid; +}; + +/* + * falcon ID to bootstrap + */ +struct pmu_acr_cmd_bootstrap_multiple_falcons { + u8 cmd_type; + u32 flags; + u32 falconidmask; + u32 usevamask; + struct falc_u64 wprvirtualbase; +}; + +#define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_NO 1 +#define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0 + + +struct pmu_acr_cmd { + union { + u8 cmd_type; + struct pmu_acr_cmd_bootstrap_falcon bootstrap_falcon; + struct pmu_acr_cmd_init_wpr_details init_wpr; + struct pmu_acr_cmd_bootstrap_multiple_falcons boot_falcons; + }; +}; + +/* acr messages */ + +/* + * returns the WPR region init information + */ +#define PMU_ACR_MSG_ID_INIT_WPR_REGION 0 + +/* + * Returns the Bootstrapped falcon ID to RM + */ +#define PMU_ACR_MSG_ID_BOOTSTRAP_FALCON 1 + +/* + * Returns the WPR init status + */ +#define PMU_ACR_SUCCESS 0 +#define PMU_ACR_ERROR 1 + +/* + * PMU notifies about bootstrap status of falcon + */ +struct pmu_acr_msg_bootstrap_falcon { + u8 msg_type; + union { + u32 errorcode; + u32 falconid; + }; +}; + +struct pmu_acr_msg { + union { + u8 msg_type; + struct pmu_acr_msg_bootstrap_falcon acrmsg; + }; +}; + +#endif /* _GPMUIFACR_H_ */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_ap.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_ap.h new file mode 100644 index 00000000..7e2f546c --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_ap.h @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _GPMUIFAP_H_ +#define _GPMUIFAP_H_ + +/* PMU Command/Message Interfaces for Adaptive Power */ +/* Macro to get Histogram index */ +#define PMU_AP_HISTOGRAM(idx) (idx) +#define PMU_AP_HISTOGRAM_CONT (4) + +/* Total number of histogram bins */ +#define PMU_AP_CFG_HISTOGRAM_BIN_N (16) + +/* Mapping between Idle counters and histograms */ +#define PMU_AP_IDLE_MASK_HIST_IDX_0 (2) +#define PMU_AP_IDLE_MASK_HIST_IDX_1 (3) +#define PMU_AP_IDLE_MASK_HIST_IDX_2 (5) +#define PMU_AP_IDLE_MASK_HIST_IDX_3 (6) + + +/* Mapping between AP_CTRLs and Histograms */ +#define PMU_AP_HISTOGRAM_IDX_GRAPHICS (PMU_AP_HISTOGRAM(1)) + +/* Mapping between AP_CTRLs and Idle counters */ +#define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1) + +/* Adaptive Power Controls (AP_CTRL) */ +enum { + PMU_AP_CTRL_ID_GRAPHICS = 0x0, + PMU_AP_CTRL_ID_MAX, +}; + +/* AP_CTRL Statistics */ +struct pmu_ap_ctrl_stat { + /* + * Represents whether AP is active or not + */ + u8 b_active; + + /* Idle filter represented by histogram bin index */ + u8 idle_filter_x; + u8 rsvd[2]; + + /* Total predicted power saving cycles. */ + s32 power_saving_h_cycles; + + /* Counts how many times AP gave us -ve power benefits. */ + u32 bad_decision_count; + + /* + * Number of times ap structure needs to skip AP iterations + * KICK_CTRL from kernel updates this parameter. + */ + u32 skip_count; + u8 bin[PMU_AP_CFG_HISTOGRAM_BIN_N]; +}; + +/* Parameters initialized by INITn APCTRL command */ +struct pmu_ap_ctrl_init_params { + /* Minimum idle filter value in Us */ + u32 min_idle_filter_us; + + /* + * Minimum Targeted Saving in Us. AP will update idle thresholds only + * if power saving achieved by updating idle thresholds is greater than + * Minimum targeted saving. + */ + u32 min_target_saving_us; + + /* Minimum targeted residency of power feature in Us */ + u32 power_break_even_us; + + /* + * Maximum number of allowed power feature cycles per sample. + * + * We are allowing at max "pgPerSampleMax" cycles in one iteration of AP + * AKA pgPerSampleMax in original algorithm. + */ + u32 cycles_per_sample_max; +}; + +/* AP Commands/Message structures */ + +/* + * Structure for Generic AP Commands + */ +struct pmu_ap_cmd_common { + u8 cmd_type; + u16 cmd_id; +}; + +/* + * Structure for INIT AP command + */ +struct pmu_ap_cmd_init { + u8 cmd_type; + u16 cmd_id; + u8 rsvd; + u32 pg_sampling_period_us; +}; + +/* + * Structure for Enable/Disable ApCtrl Commands + */ +struct pmu_ap_cmd_enable_ctrl { + u8 cmd_type; + u16 cmd_id; + + u8 ctrl_id; +}; + +struct pmu_ap_cmd_disable_ctrl { + u8 cmd_type; + u16 cmd_id; + + u8 ctrl_id; +}; + +/* + * Structure for INIT command + */ +struct pmu_ap_cmd_init_ctrl { + u8 cmd_type; + u16 cmd_id; + u8 ctrl_id; + struct pmu_ap_ctrl_init_params params; +}; + +struct pmu_ap_cmd_init_and_enable_ctrl { + u8 cmd_type; + u16 cmd_id; + u8 ctrl_id; + struct pmu_ap_ctrl_init_params params; +}; + +/* + * Structure for KICK_CTRL command + */ +struct pmu_ap_cmd_kick_ctrl { + u8 cmd_type; + u16 cmd_id; + u8 ctrl_id; + + u32 skip_count; +}; + +/* + * Structure for PARAM command + */ +struct pmu_ap_cmd_param { + u8 cmd_type; + u16 cmd_id; + u8 ctrl_id; + + u32 data; +}; + +/* + * Defines for AP commands + */ +enum { + PMU_AP_CMD_ID_INIT = 0x0, + PMU_AP_CMD_ID_INIT_AND_ENABLE_CTRL, + PMU_AP_CMD_ID_ENABLE_CTRL, + PMU_AP_CMD_ID_DISABLE_CTRL, + PMU_AP_CMD_ID_KICK_CTRL, +}; + +/* + * AP Command + */ +union pmu_ap_cmd { + u8 cmd_type; + struct pmu_ap_cmd_common cmn; + struct pmu_ap_cmd_init init; + struct pmu_ap_cmd_init_and_enable_ctrl init_and_enable_ctrl; + struct pmu_ap_cmd_enable_ctrl enable_ctrl; + struct pmu_ap_cmd_disable_ctrl disable_ctrl; + struct pmu_ap_cmd_kick_ctrl kick_ctrl; +}; + +/* + * Structure for generic AP Message + */ +struct pmu_ap_msg_common { + u8 msg_type; + u16 msg_id; +}; + +/* + * Structure for INIT_ACK Message + */ +struct pmu_ap_msg_init_ack { + u8 msg_type; + u16 msg_id; + u8 ctrl_id; + u32 stats_dmem_offset; +}; + +/* + * Defines for AP messages + */ +enum { + PMU_AP_MSG_ID_INIT_ACK = 0x0, +}; + +/* + * AP Message + */ +union pmu_ap_msg { + u8 msg_type; + struct pmu_ap_msg_common cmn; + struct pmu_ap_msg_init_ack init_ack; +}; + +/* + * Adaptive Power Controller + */ +struct ap_ctrl { + u32 stats_dmem_offset; + u32 disable_reason_mask; + struct pmu_ap_ctrl_stat stat_cache; + u8 b_ready; +}; + +/* + * Adaptive Power structure + * + * ap structure provides generic infrastructure to make any power feature + * adaptive. + */ +struct pmu_ap { + u32 supported_mask; + struct ap_ctrl ap_ctrl[PMU_AP_CTRL_ID_MAX]; +}; + +#endif /* _GPMUIFAP_H_*/ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h new file mode 100644 index 00000000..1d200129 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _GPMUIFCMN_H_ +#define _GPMUIFCMN_H_ + +/* + * Defines the logical queue IDs that must be used when submitting + * commands to the PMU + */ +/* write by sw, read by pmu, protected by sw mutex lock */ +#define PMU_COMMAND_QUEUE_HPQ 0 +/* write by sw, read by pmu, protected by sw mutex lock */ +#define PMU_COMMAND_QUEUE_LPQ 1 +/* read/write by sw/hw, protected by hw pmu mutex, id = 2 */ +#define PMU_COMMAND_QUEUE_BIOS 2 +/* read/write by sw/hw, protected by hw pmu mutex, id = 3 */ +#define PMU_COMMAND_QUEUE_SMI 3 +/* write by pmu, read by sw, accessed by interrupt handler, no lock */ +#define PMU_MESSAGE_QUEUE 4 +#define PMU_QUEUE_COUNT 5 + +#define PMU_IS_COMMAND_QUEUE(id) \ + ((id) < PMU_MESSAGE_QUEUE) + +#define PMU_IS_SW_COMMAND_QUEUE(id) \ + (((id) == PMU_COMMAND_QUEUE_HPQ) || \ + ((id) == PMU_COMMAND_QUEUE_LPQ)) + +#define PMU_IS_MESSAGE_QUEUE(id) \ + ((id) == PMU_MESSAGE_QUEUE) + +enum { + OFLAG_READ = 0, + OFLAG_WRITE +}; + +#define QUEUE_SET (true) +#define QUEUE_GET (false) + +#define QUEUE_ALIGNMENT (4) + +/* An enumeration containing all valid logical mutex identifiers */ +enum { + PMU_MUTEX_ID_RSVD1 = 0, + PMU_MUTEX_ID_GPUSER, + PMU_MUTEX_ID_QUEUE_BIOS, + PMU_MUTEX_ID_QUEUE_SMI, + PMU_MUTEX_ID_GPMUTEX, + PMU_MUTEX_ID_I2C, + PMU_MUTEX_ID_RMLOCK, + PMU_MUTEX_ID_MSGBOX, + PMU_MUTEX_ID_FIFO, + PMU_MUTEX_ID_PG, + PMU_MUTEX_ID_GR, + PMU_MUTEX_ID_CLK, + PMU_MUTEX_ID_RSVD6, + PMU_MUTEX_ID_RSVD7, + PMU_MUTEX_ID_RSVD8, + PMU_MUTEX_ID_RSVD9, + PMU_MUTEX_ID_INVALID +}; + +#define PMU_MUTEX_ID_IS_VALID(id) \ + ((id) < PMU_MUTEX_ID_INVALID) + +#define PMU_INVALID_MUTEX_OWNER_ID (0) + +/* + * The PMU's frame-buffer interface block has several slots/indices + * which can be bound to support DMA to various surfaces in memory + */ +enum { + PMU_DMAIDX_UCODE = 0, + PMU_DMAIDX_VIRT = 1, + PMU_DMAIDX_PHYS_VID = 2, + PMU_DMAIDX_PHYS_SYS_COH = 3, + PMU_DMAIDX_PHYS_SYS_NCOH = 4, + PMU_DMAIDX_RSVD = 5, + PMU_DMAIDX_PELPG = 6, + PMU_DMAIDX_END = 7 +}; + +/* + * Falcon PMU DMA's minimum size in bytes. + */ +#define PMU_DMA_MIN_READ_SIZE_BYTES 16 +#define PMU_DMA_MIN_WRITE_SIZE_BYTES 4 + +#define PMU_FB_COPY_RW_ALIGNMENT \ + ((PMU_DMA_MIN_READ_SIZE_BYTES > PMU_DMA_MIN_WRITE_SIZE_BYTES) ? \ + PMU_DMA_MIN_READ_SIZE_BYTES : PMU_DMA_MIN_WRITE_SIZE_BYTES) + +/* + * Macros to make aligned versions of RM_PMU_XXX structures. PMU needs aligned + * data structures to issue DMA read/write operations. + */ +#define NV_PMU_MAKE_ALIGNED_STRUCT(name, size) \ +union name##_aligned { \ + struct name data; \ + u8 pad[ALIGN_UP(sizeof(struct name), \ + (PMU_FB_COPY_RW_ALIGNMENT))]; \ +} + +#define NV_PMU_MAKE_ALIGNED_UNION(name, size) \ +union name##_aligned { \ + union name data; \ + u8 pad[ALIGN_UP(sizeof(union name), \ + (PMU_FB_COPY_RW_ALIGNMENT))]; \ +} + +#endif /* _GPMUIFCMN_H_*/ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h new file mode 100644 index 00000000..098d0305 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h @@ -0,0 +1,178 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _GPMUIFPERFMON_H_ +#define _GPMUIFPERFMON_H_ + +/*perfmon task defines*/ + +#define PMU_DOMAIN_GROUP_PSTATE 0 +#define PMU_DOMAIN_GROUP_GPC2CLK 1 +#define PMU_DOMAIN_GROUP_NUM 2 + +#define PMU_PERFMON_FLAG_ENABLE_INCREASE (0x00000001) +#define PMU_PERFMON_FLAG_ENABLE_DECREASE (0x00000002) +#define PMU_PERFMON_FLAG_CLEAR_PREV (0x00000004) + +enum pmu_perfmon_cmd_start_fields { + COUNTER_ALLOC +}; + +enum { + PMU_PERFMON_CMD_ID_START = 0, + PMU_PERFMON_CMD_ID_STOP = 1, + PMU_PERFMON_CMD_ID_INIT = 2 +}; + +struct pmu_perfmon_counter_v0 { + u8 index; + u8 flags; + u8 group_id; + u8 valid; + u16 upper_threshold; /* units of 0.01% */ + u16 lower_threshold; /* units of 0.01% */ +}; + +struct pmu_perfmon_counter_v2 { + u8 index; + u8 flags; + u8 group_id; + u8 valid; + u16 upper_threshold; /* units of 0.01% */ + u16 lower_threshold; /* units of 0.01% */ + u32 scale; +}; + +struct pmu_perfmon_cmd_start_v3 { + u8 cmd_type; + u8 group_id; + u8 state_id; + u8 flags; + struct pmu_allocation_v3 counter_alloc; +}; + +struct pmu_perfmon_cmd_start_v2 { + u8 cmd_type; + u8 group_id; + u8 state_id; + u8 flags; + struct pmu_allocation_v2 counter_alloc; +}; + +struct pmu_perfmon_cmd_start_v1 { + u8 cmd_type; + u8 group_id; + u8 state_id; + u8 flags; + struct pmu_allocation_v1 counter_alloc; +}; + +struct pmu_perfmon_cmd_start_v0 { + u8 cmd_type; + u8 group_id; + u8 state_id; + u8 flags; + struct pmu_allocation_v0 counter_alloc; +}; + +struct pmu_perfmon_cmd_stop { + u8 cmd_type; +}; + +struct pmu_perfmon_cmd_init_v3 { + u8 cmd_type; + u8 to_decrease_count; + u8 base_counter_id; + u32 sample_period_us; + struct pmu_allocation_v3 counter_alloc; + u8 num_counters; + u8 samples_in_moving_avg; + u16 sample_buffer; +}; + +struct pmu_perfmon_cmd_init_v2 { + u8 cmd_type; + u8 to_decrease_count; + u8 base_counter_id; + u32 sample_period_us; + struct pmu_allocation_v2 counter_alloc; + u8 num_counters; + u8 samples_in_moving_avg; + u16 sample_buffer; +}; + +struct pmu_perfmon_cmd_init_v1 { + u8 cmd_type; + u8 to_decrease_count; + u8 base_counter_id; + u32 sample_period_us; + struct pmu_allocation_v1 counter_alloc; + u8 num_counters; + u8 samples_in_moving_avg; + u16 sample_buffer; +}; + +struct pmu_perfmon_cmd_init_v0 { + u8 cmd_type; + u8 to_decrease_count; + u8 base_counter_id; + u32 sample_period_us; + struct pmu_allocation_v0 counter_alloc; + u8 num_counters; + u8 samples_in_moving_avg; + u16 sample_buffer; +}; + +struct pmu_perfmon_cmd { + union { + u8 cmd_type; + struct pmu_perfmon_cmd_start_v0 start_v0; + struct pmu_perfmon_cmd_start_v1 start_v1; + struct pmu_perfmon_cmd_start_v2 start_v2; + struct pmu_perfmon_cmd_start_v3 start_v3; + struct pmu_perfmon_cmd_stop stop; + struct pmu_perfmon_cmd_init_v0 init_v0; + struct pmu_perfmon_cmd_init_v1 init_v1; + struct pmu_perfmon_cmd_init_v2 init_v2; + struct pmu_perfmon_cmd_init_v3 init_v3; + }; +}; + +struct pmu_zbc_cmd { + u8 cmd_type; + u8 pad; + u16 entry_mask; +}; + +/* PERFMON MSG */ +enum { + PMU_PERFMON_MSG_ID_INCREASE_EVENT = 0, + PMU_PERFMON_MSG_ID_DECREASE_EVENT = 1, + PMU_PERFMON_MSG_ID_INIT_EVENT = 2, + PMU_PERFMON_MSG_ID_ACK = 3 +}; + +struct pmu_perfmon_msg_generic { + u8 msg_type; + u8 state_id; + u8 group_id; + u8 data; +}; + +struct pmu_perfmon_msg { + union { + u8 msg_type; + struct pmu_perfmon_msg_generic gen; + }; +}; + +#endif /* _GPMUIFPERFMON_H_ */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h new file mode 100644 index 00000000..8c71e2a2 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h @@ -0,0 +1,311 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _GPMUIFPG_H_ +#define _GPMUIFPG_H_ + +#include "gpmuif_ap.h" +#include "gpmuif_pg_rppg.h" + +/*PG defines*/ + +/* Identifier for each PG */ +#define PMU_PG_ELPG_ENGINE_ID_GRAPHICS (0x00000000) +#define PMU_PG_ELPG_ENGINE_ID_MS (0x00000004) +#define PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE (0x00000005) +#define PMU_PG_ELPG_ENGINE_MAX PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE + +/* PG message */ +enum { + PMU_PG_ELPG_MSG_INIT_ACK, + PMU_PG_ELPG_MSG_DISALLOW_ACK, + PMU_PG_ELPG_MSG_ALLOW_ACK, + PMU_PG_ELPG_MSG_FREEZE_ACK, + PMU_PG_ELPG_MSG_FREEZE_ABORT, + PMU_PG_ELPG_MSG_UNFREEZE_ACK, +}; + +struct pmu_pg_msg_elpg_msg { + u8 msg_type; + u8 engine_id; + u16 msg; +}; + +enum { + PMU_PG_STAT_MSG_RESP_DMEM_OFFSET = 0, +}; + +struct pmu_pg_msg_stat { + u8 msg_type; + u8 engine_id; + u16 sub_msg_id; + u32 data; +}; + +enum { + PMU_PG_MSG_ENG_BUF_LOADED, + PMU_PG_MSG_ENG_BUF_UNLOADED, + PMU_PG_MSG_ENG_BUF_FAILED, +}; + +struct pmu_pg_msg_eng_buf_stat { + u8 msg_type; + u8 engine_id; + u8 buf_idx; + u8 status; +}; + +struct pmu_pg_msg { + union { + u8 msg_type; + struct pmu_pg_msg_elpg_msg elpg_msg; + struct pmu_pg_msg_stat stat; + struct pmu_pg_msg_eng_buf_stat eng_buf_stat; + /* TBD: other pg messages */ + union pmu_ap_msg ap_msg; + struct nv_pmu_rppg_msg rppg_msg; + }; +}; + +/* PG commands */ +enum { + PMU_PG_ELPG_CMD_INIT, + PMU_PG_ELPG_CMD_DISALLOW, + PMU_PG_ELPG_CMD_ALLOW, + PMU_PG_ELPG_CMD_FREEZE, + PMU_PG_ELPG_CMD_UNFREEZE, +}; + +enum { + PMU_PG_CMD_ID_ELPG_CMD = 0, + PMU_PG_CMD_ID_ENG_BUF_LOAD, + PMU_PG_CMD_ID_ENG_BUF_UNLOAD, + PMU_PG_CMD_ID_PG_STAT, + PMU_PG_CMD_ID_PG_LOG_INIT, + PMU_PG_CMD_ID_PG_LOG_FLUSH, + PMU_PG_CMD_ID_PG_PARAM, + PMU_PG_CMD_ID_ELPG_INIT, + PMU_PG_CMD_ID_ELPG_POLL_CTXSAVE, + PMU_PG_CMD_ID_ELPG_ABORT_POLL, + PMU_PG_CMD_ID_ELPG_PWR_UP, + PMU_PG_CMD_ID_ELPG_DISALLOW, + PMU_PG_CMD_ID_ELPG_ALLOW, + PMU_PG_CMD_ID_AP, + RM_PMU_PG_CMD_ID_PSI, + RM_PMU_PG_CMD_ID_CG, + PMU_PG_CMD_ID_ZBC_TABLE_UPDATE, + PMU_PG_CMD_ID_PWR_RAIL_GATE_DISABLE = 0x20, + PMU_PG_CMD_ID_PWR_RAIL_GATE_ENABLE, + PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE, + PMU_PMU_PG_CMD_ID_RPPG = 0x24, +}; + +enum { + PMU_PG_STAT_CMD_ALLOC_DMEM = 0, +}; + +#define PMU_PG_PARAM_CMD_GR_INIT_PARAM 0x0 +#define PMU_PG_PARAM_CMD_MS_INIT_PARAM 0x01 +#define PMU_PG_PARAM_CMD_MCLK_CHANGE 0x04 +#define PMU_PG_PARAM_CMD_POST_INIT 0x06 + +#define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0) +#define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED (1 << 2) +#define PMU_PG_FEATURE_GR_RPPG_ENABLED (1 << 3) + +#define NVGPU_PMU_GR_FEATURE_MASK_RPPG (1 << 3) +#define NVGPU_PMU_GR_FEATURE_MASK_ALL \ + ( \ + NVGPU_PMU_GR_FEATURE_MASK_RPPG \ + ) + +#define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING (1 << 0) +#define NVGPU_PMU_MS_FEATURE_MASK_SW_ASR (1 << 1) +#define NVGPU_PMU_MS_FEATURE_MASK_RPPG (1 << 8) +#define NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING (1 << 5) + +#define NVGPU_PMU_MS_FEATURE_MASK_ALL \ + ( \ + NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING |\ + NVGPU_PMU_MS_FEATURE_MASK_SW_ASR |\ + NVGPU_PMU_MS_FEATURE_MASK_RPPG |\ + NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING \ + ) + + +struct pmu_pg_cmd_elpg_cmd { + u8 cmd_type; + u8 engine_id; + u16 cmd; +}; + +struct pmu_pg_cmd_eng_buf_load_v0 { + u8 cmd_type; + u8 engine_id; + u8 buf_idx; + u8 pad; + u16 buf_size; + u32 dma_base; + u8 dma_offset; + u8 dma_idx; +}; + +struct pmu_pg_cmd_eng_buf_load_v1 { + u8 cmd_type; + u8 engine_id; + u8 buf_idx; + u8 pad; + struct flcn_mem_desc { + struct falc_u64 dma_addr; + u16 dma_size; + u8 dma_idx; + } dma_desc; +}; + +struct pmu_pg_cmd_eng_buf_load_v2 { + u8 cmd_type; + u8 engine_id; + u8 buf_idx; + u8 pad; + struct flcn_mem_desc_v0 dma_desc; +}; + +struct pmu_pg_cmd_gr_init_param { + u8 cmd_type; + u16 sub_cmd_id; + u8 featuremask; +}; + +struct pmu_pg_cmd_ms_init_param { + u8 cmd_type; + u16 cmd_id; + u8 psi; + u8 idle_flipped_test_enabled; + u16 psiSettleTimeUs; + u8 rsvd[2]; + u32 support_mask; + u32 abort_timeout_us; +}; + +struct pmu_pg_cmd_mclk_change { + u8 cmd_type; + u16 cmd_id; + u8 rsvd; + u32 data; +}; + +#define PG_VOLT_RAIL_IDX_MAX 2 + +struct pmu_pg_volt_rail { + u8 volt_rail_idx; + u8 sleep_volt_dev_idx; + u8 sleep_vfe_idx; + u32 sleep_voltage_uv; + u32 therm_vid0_cache; + u32 therm_vid1_cache; +}; + +struct pmu_pg_cmd_post_init_param { + u8 cmd_type; + u16 cmd_id; + struct pmu_pg_volt_rail pg_volt_rail[PG_VOLT_RAIL_IDX_MAX]; +}; + +struct pmu_pg_cmd_stat { + u8 cmd_type; + u8 engine_id; + u16 sub_cmd_id; + u32 data; +}; + +struct pmu_pg_cmd { + union { + u8 cmd_type; + struct pmu_pg_cmd_elpg_cmd elpg_cmd; + struct pmu_pg_cmd_eng_buf_load_v0 eng_buf_load_v0; + struct pmu_pg_cmd_eng_buf_load_v1 eng_buf_load_v1; + struct pmu_pg_cmd_eng_buf_load_v2 eng_buf_load_v2; + struct pmu_pg_cmd_stat stat; + struct pmu_pg_cmd_gr_init_param gr_init_param; + struct pmu_pg_cmd_ms_init_param ms_init_param; + struct pmu_pg_cmd_mclk_change mclk_change; + struct pmu_pg_cmd_post_init_param post_init; + /* TBD: other pg commands */ + union pmu_ap_cmd ap_cmd; + struct nv_pmu_rppg_cmd rppg_cmd; + }; +}; + +/* Statistics structure for PG features */ +struct pmu_pg_stats_v2 { + u32 entry_count; + u32 exit_count; + u32 abort_count; + u32 detection_count; + u32 prevention_activate_count; + u32 prevention_deactivate_count; + u32 powered_up_time_us; + u32 entry_latency_us; + u32 exit_latency_us; + u32 resident_time_us; + u32 entry_latency_avg_us; + u32 exit_latency_avg_us; + u32 entry_latency_max_us; + u32 exit_latency_max_us; + u32 total_sleep_time_us; + u32 total_non_sleep_time_us; +}; + +struct pmu_pg_stats_v1 { + /* Number of time PMU successfully engaged sleep state */ + u32 entry_count; + /* Number of time PMU exit sleep state */ + u32 exit_count; + /* Number of time PMU aborted in entry sequence */ + u32 abort_count; + /* + * Time for which GPU was neither in Sleep state not + * executing sleep sequence. + */ + u32 poweredup_timeus; + /* Entry and exit latency of current sleep cycle */ + u32 entry_latency_us; + u32 exitlatencyus; + /* Resident time for current sleep cycle. */ + u32 resident_timeus; + /* Rolling average entry and exit latencies */ + u32 entrylatency_avgus; + u32 exitlatency_avgus; + /* Max entry and exit latencies */ + u32 entrylatency_maxus; + u32 exitlatency_maxus; + /* Total time spent in sleep and non-sleep state */ + u32 total_sleep_timeus; + u32 total_nonsleep_timeus; +}; + +struct pmu_pg_stats { + u64 pg_entry_start_timestamp; + u64 pg_ingating_start_timestamp; + u64 pg_exit_start_timestamp; + u64 pg_ungating_start_timestamp; + u32 pg_avg_entry_time_us; + u32 pg_ingating_cnt; + u32 pg_ingating_time_us; + u32 pg_avg_exit_time_us; + u32 pg_ungating_count; + u32 pg_ungating_time_us; + u32 pg_gating_cnt; + u32 pg_gating_deny_cnt; +}; + +#endif /* _GPMUIFPG_H_*/ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg_rppg.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg_rppg.h new file mode 100644 index 00000000..d2f23011 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg_rppg.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _GPMUIFRPPG_H_ +#define _GPMUIFRPPG_H_ + +#define NV_PMU_RPPG_CTRL_ID_GR (0x0000) +#define NV_PMU_RPPG_CTRL_ID_MS (0x0001) +#define NV_PMU_RPPG_CTRL_ID_DI (0x0002) +#define NV_PMU_RPPG_CTRL_ID_MAX (0x0003) + +#define NV_PMU_RPPG_CTRL_MASK_ENABLE_ALL (BIT(NV_PMU_RPPG_CTRL_ID_GR) |\ + BIT(NV_PMU_RPPG_CTRL_ID_MS) |\ + BIT(NV_PMU_RPPG_CTRL_ID_DI)) + +#define NV_PMU_RPPG_CTRL_MASK_DISABLE_ALL 0 + +enum { + NV_PMU_RPPG_DOMAIN_ID_GFX = 0x0, + NV_PMU_RPPG_DOMAIN_ID_NON_GFX, +}; + +struct nv_pmu_rppg_ctrl_stats { + u32 entry_count; + u32 exit_count; +}; + +struct nv_pmu_rppg_cmd_common { + u8 cmd_type; + u8 cmd_id; +}; + +struct nv_pmu_rppg_cmd_init { + u8 cmd_type; + u8 cmd_id; +}; + +struct nv_pmu_rppg_cmd_init_ctrl { + u8 cmd_type; + u8 cmd_id; + u8 ctrl_id; + u8 domain_id; +}; + +struct nv_pmu_rppg_cmd_stats_reset { + u8 cmd_type; + u8 cmd_id; + u8 ctrl_id; +}; + +struct nv_pmu_rppg_cmd { + union { + u8 cmd_type; + struct nv_pmu_rppg_cmd_common cmn; + struct nv_pmu_rppg_cmd_init init; + struct nv_pmu_rppg_cmd_init_ctrl init_ctrl; + struct nv_pmu_rppg_cmd_stats_reset stats_reset; + }; +}; + +enum { + NV_PMU_RPPG_CMD_ID_INIT = 0x0, + NV_PMU_RPPG_CMD_ID_INIT_CTRL, + NV_PMU_RPPG_CMD_ID_STATS_RESET, +}; + + +struct nv_pmu_rppg_msg_common { + u8 msg_type; + u8 msg_id; +}; + +struct nv_pmu_rppg_msg_init_ctrl_ack { + u8 msg_type; + u8 msg_id; + u8 ctrl_id; + u32 stats_dmem_offset; +}; + +struct nv_pmu_rppg_msg { + union { + u8 msg_type; + struct nv_pmu_rppg_msg_common cmn; + struct nv_pmu_rppg_msg_init_ctrl_ack init_ctrl_ack; + }; +}; + +enum { + NV_PMU_RPPG_MSG_ID_INIT_CTRL_ACK = 0x0, +}; + +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h new file mode 100644 index 00000000..6df92c1d --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pmu.h @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _GPMUIFPMU_H_ +#define _GPMUIFPMU_H_ + +#include +#include "gpmuif_cmn.h" + +/* Make sure size of this structure is a multiple of 4 bytes */ +struct pmu_cmdline_args_v0 { + u32 cpu_freq_hz; + u32 falc_trace_size; + u32 falc_trace_dma_base; + u32 falc_trace_dma_idx; + struct pmu_mem_v0 gc6_ctx; +}; + +struct pmu_cmdline_args_v1 { + u32 cpu_freq_hz; + u32 falc_trace_size; + u32 falc_trace_dma_base; + u32 falc_trace_dma_idx; + u8 secure_mode; + struct pmu_mem_v1 gc6_ctx; +}; + +struct pmu_cmdline_args_v2 { + u32 cpu_freq_hz; + u32 falc_trace_size; + u32 falc_trace_dma_base; + u32 falc_trace_dma_idx; + u8 secure_mode; + u8 raise_priv_sec; + struct pmu_mem_v1 gc6_ctx; +}; + +struct pmu_cmdline_args_v3 { + u32 reserved; + u32 cpu_freq_hz; + u32 falc_trace_size; + u32 falc_trace_dma_base; + u32 falc_trace_dma_idx; + u8 secure_mode; + u8 raise_priv_sec; + struct pmu_mem_v1 gc6_ctx; +}; + +struct pmu_cmdline_args_v4 { + u32 reserved; + u32 cpu_freq_hz; + u32 falc_trace_size; + struct falc_dma_addr dma_addr; + u32 falc_trace_dma_idx; + u8 secure_mode; + u8 raise_priv_sec; + struct pmu_mem_desc_v0 gc6_ctx; + u8 pad; +}; + +struct pmu_cmdline_args_v5 { + u32 cpu_freq_hz; + struct flcn_mem_desc_v0 trace_buf; + u8 secure_mode; + u8 raise_priv_sec; + struct flcn_mem_desc_v0 gc6_ctx; + struct flcn_mem_desc_v0 init_data_dma_info; + u32 dummy; +}; + +/* GPU ID */ +#define PMU_SHA1_GID_SIGNATURE 0xA7C66AD2 +#define PMU_SHA1_GID_SIGNATURE_SIZE 4 + +#define PMU_SHA1_GID_SIZE 16 + +struct pmu_sha1_gid { + bool valid; + u8 gid[PMU_SHA1_GID_SIZE]; +}; + +struct pmu_sha1_gid_data { + u8 signature[PMU_SHA1_GID_SIGNATURE_SIZE]; + u8 gid[PMU_SHA1_GID_SIZE]; +}; + +/* PMU INIT MSG */ +enum { + PMU_INIT_MSG_TYPE_PMU_INIT = 0, +}; + +struct pmu_init_msg_pmu_v0 { + u8 msg_type; + u8 pad; + + struct { + u16 size; + u16 offset; + u8 index; + u8 pad; + } queue_info[PMU_QUEUE_COUNT]; + + u16 sw_managed_area_offset; + u16 sw_managed_area_size; +}; + +struct pmu_init_msg_pmu_v1 { + u8 msg_type; + u8 pad; + u16 os_debug_entry_point; + + struct { + u16 size; + u16 offset; + u8 index; + u8 pad; + } queue_info[PMU_QUEUE_COUNT]; + + u16 sw_managed_area_offset; + u16 sw_managed_area_size; +}; +struct pmu_init_msg_pmu_v2 { + u8 msg_type; + u8 pad; + u16 os_debug_entry_point; + + struct { + u16 size; + u16 offset; + u8 index; + u8 pad; + } queue_info[PMU_QUEUE_COUNT]; + + u16 sw_managed_area_offset; + u16 sw_managed_area_size; + u8 dummy[18]; +}; + +#define PMU_QUEUE_COUNT_FOR_V4 5 +#define PMU_QUEUE_COUNT_FOR_V3 3 +#define PMU_QUEUE_HPQ_IDX_FOR_V3 0 +#define PMU_QUEUE_LPQ_IDX_FOR_V3 1 +#define PMU_QUEUE_MSG_IDX_FOR_V3 2 +struct pmu_init_msg_pmu_v3 { + u8 msg_type; + u8 queue_index[PMU_QUEUE_COUNT_FOR_V3]; + u16 queue_size[PMU_QUEUE_COUNT_FOR_V3]; + u16 queue_offset; + + u16 sw_managed_area_offset; + u16 sw_managed_area_size; + + u16 os_debug_entry_point; + + u8 dummy[18]; +}; + +struct pmu_init_msg_pmu_v4 { + u8 msg_type; + u8 queue_index[PMU_QUEUE_COUNT_FOR_V4]; + u16 queue_size[PMU_QUEUE_COUNT_FOR_V4]; + u16 queue_offset; + + u16 sw_managed_area_offset; + u16 sw_managed_area_size; + + u16 os_debug_entry_point; + + u8 dummy[18]; +}; + +union pmu_init_msg_pmu { + struct pmu_init_msg_pmu_v0 v0; + struct pmu_init_msg_pmu_v1 v1; + struct pmu_init_msg_pmu_v2 v2; + struct pmu_init_msg_pmu_v3 v3; + struct pmu_init_msg_pmu_v4 v4; +}; + +struct pmu_init_msg { + union { + u8 msg_type; + struct pmu_init_msg_pmu_v1 pmu_init_v1; + struct pmu_init_msg_pmu_v0 pmu_init_v0; + struct pmu_init_msg_pmu_v2 pmu_init_v2; + struct pmu_init_msg_pmu_v3 pmu_init_v3; + struct pmu_init_msg_pmu_v4 pmu_init_v4; + }; +}; + +/* robust channel (RC) messages */ +enum { + PMU_RC_MSG_TYPE_UNHANDLED_CMD = 0, +}; + +struct pmu_rc_msg_unhandled_cmd { + u8 msg_type; + u8 unit_id; +}; + +struct pmu_rc_msg { + u8 msg_type; + struct pmu_rc_msg_unhandled_cmd unhandled_cmd; +}; + +#endif /* _GPMUIFPMU_H_*/ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifbios.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifbios.h new file mode 100644 index 00000000..eaa44bc2 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifbios.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _GPMUIFBIOS_H_ +#define _GPMUIFBIOS_H_ + +struct nv_pmu_bios_vfield_register_segment_super { + u8 type; + u8 low_bit; + u8 high_bit; +}; + +struct nv_pmu_bios_vfield_register_segment_reg { + struct nv_pmu_bios_vfield_register_segment_super super; + u32 addr; +}; + +struct nv_pmu_bios_vfield_register_segment_index_reg { + struct nv_pmu_bios_vfield_register_segment_super super; + u32 addr; + u32 reg_index; + u32 index; +}; + +union nv_pmu_bios_vfield_register_segment { + struct nv_pmu_bios_vfield_register_segment_super super; + struct nv_pmu_bios_vfield_register_segment_reg reg; + struct nv_pmu_bios_vfield_register_segment_index_reg index_reg; +}; + + +#endif /* _GPMUIFBIOS_H_*/ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h new file mode 100644 index 00000000..8da31469 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifboardobj.h @@ -0,0 +1,195 @@ +/* +* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms and conditions of the GNU General Public License, +* version 2, as published by the Free Software Foundation. +* +* This program is distributed in the hope it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +*/ +#ifndef _GPMUIFBOARDOBJ_H_ +#define _GPMUIFBOARDOBJ_H_ + +#include +#include "ctrl/ctrlboardobj.h" + +/* + * Base structure describing a BOARDOBJ for communication between Kernel and + * PMU. + */ +struct nv_pmu_boardobj { + u8 type; +}; + +/* + * Base structure describing a BOARDOBJ for Query interface between Kernel and + * PMU. + */ +struct nv_pmu_boardobj_query { + u8 type; +}; + +/* + * Virtual base structure describing a BOARDOBJGRP interface between Kernel and + * PMU. + */ +struct nv_pmu_boardobjgrp_super { + u8 type; + u8 class_id; + u8 obj_slots; + u8 rsvd; +}; + +struct nv_pmu_boardobjgrp { + struct nv_pmu_boardobjgrp_super super; + u32 obj_mask; +}; + +struct nv_pmu_boardobjgrp_e32 { + struct nv_pmu_boardobjgrp_super super; + struct ctrl_boardobjgrp_mask_e32 obj_mask; +}; + +struct nv_pmu_boardobjgrp_e255 { + struct nv_pmu_boardobjgrp_super super; + struct ctrl_boardobjgrp_mask_e255 obj_mask; +}; + +struct nv_pmu_boardobj_cmd_grp_payload { + struct pmu_allocation_v3 dmem_buf; + struct flcn_mem_desc_v0 fb; + u8 hdr_size; + u8 entry_size; +}; + +struct nv_pmu_boardobj_cmd_grp { + u8 cmd_type; + u8 pad[2]; + u8 class_id; + struct nv_pmu_boardobj_cmd_grp_payload grp; +}; + +#define NV_PMU_BOARDOBJ_GRP_ALLOC_OFFSET \ + (NV_OFFSETOF(NV_PMU_BOARDOBJ_CMD_GRP, grp)) + +struct nv_pmu_boardobj_cmd { + union { + u8 cmd_type; + struct nv_pmu_boardobj_cmd_grp grp; + struct nv_pmu_boardobj_cmd_grp grp_set; + struct nv_pmu_boardobj_cmd_grp grp_get_status; + }; +}; + +struct nv_pmu_boardobj_msg_grp { + u8 msg_type; + bool b_success; + flcn_status flcn_status; + u8 class_id; +}; + +struct nv_pmu_boardobj_msg { + union { + u8 msg_type; + struct nv_pmu_boardobj_msg_grp grp; + struct nv_pmu_boardobj_msg_grp grp_set; + struct nv_pmu_boardobj_msg_grp grp_get_status; + }; +}; + +/* +* Macro generating structures describing classes which implement +* NV_PMU_BOARDOBJGRP via the NV_PMU_BOARDBOBJ_CMD_GRP SET interface. +* +* @para _eng Name of implementing engine in which this structure is +* found. +* @param _class Class ID of Objects within Board Object Group. +* @param _slots Max number of elements this group can contain. +*/ +#define NV_PMU_BOARDOBJ_GRP_SET_MAKE(_eng, _class, _slots) \ + NV_PMU_MAKE_ALIGNED_STRUCT( \ + nv_pmu_##_eng##_##_class##_boardobjgrp_set_header, one_structure); \ + NV_PMU_MAKE_ALIGNED_UNION( \ + nv_pmu_##_eng##_##_class##_boardobj_set_union, one_union); \ + struct nv_pmu_##_eng##_##_class##_boardobj_grp_set { \ + union nv_pmu_##_eng##_##_class##_boardobjgrp_set_header_aligned hdr; \ + union nv_pmu_##_eng##_##_class##_boardobj_set_union_aligned objects[(_slots)];\ + } + +/* +* Macro generating structures describing classes which implement +* NV_PMU_BOARDOBJGRP_E32 via the NV_PMU_BOARDBOBJ_CMD_GRP SET interface. +* +* @para _eng Name of implementing engine in which this structure is +* found. +* @param _class Class ID of Objects within Board Object Group. +*/ +#define NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(_eng, _class) \ + NV_PMU_BOARDOBJ_GRP_SET_MAKE(_eng, _class, \ + CTRL_BOARDOBJGRP_E32_MAX_OBJECTS) + +/* +* Macro generating structures describing classes which implement +* NV_PMU_BOARDOBJGRP_E255 via the NV_PMU_BOARDBOBJ_CMD_GRP SET interface. +* +* @para _eng Name of implementing engine in which this structure is +* found. +* @param _class Class ID of Objects within Board Object Group. +*/ +#define NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(_eng, _class) \ + NV_PMU_BOARDOBJ_GRP_SET_MAKE(_eng, _class, \ + CTRL_BOARDOBJGRP_E255_MAX_OBJECTS) + +/* +* Macro generating structures for querying dynamic state for classes which +* implement NV_PMU_BOARDOBJGRP via the NV_PMU_BOARDOBJ_CMD_GRP GET_STATUS +* interface. +* +* @para _eng Name of implementing engine in which this structure is +* found. +* @param _class Class ID of Objects within Board Object Group. +* @param _slots Max number of elements this group can contain. +*/ +#define NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE(_eng, _class, _slots) \ + NV_PMU_MAKE_ALIGNED_STRUCT( \ + nv_pmu_##_eng##_##_class##_boardobjgrp_get_status_header, struct); \ + NV_PMU_MAKE_ALIGNED_UNION( \ + nv_pmu_##_eng##_##_class##_boardobj_get_status_union, union); \ + struct nv_pmu_##_eng##_##_class##_boardobj_grp_get_status { \ + union nv_pmu_##_eng##_##_class##_boardobjgrp_get_status_header_aligned \ + hdr; \ + union nv_pmu_##_eng##_##_class##_boardobj_get_status_union_aligned \ + objects[(_slots)]; \ + } + +/* +* Macro generating structures for querying dynamic state for classes which +* implement NV_PMU_BOARDOBJGRP_E32 via the NV_PMU_BOARDOBJ_CMD_GRP GET_STATUS +* interface. +* +* @para _eng Name of implementing engine in which this structure is +* found. +* @param _class Class ID of Objects within Board Object Group. +*/ +#define NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(_eng, _class) \ + NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE(_eng, _class, \ + CTRL_BOARDOBJGRP_E32_MAX_OBJECTS) + +/* +* Macro generating structures for querying dynamic state for classes which +* implement NV_PMU_BOARDOBJGRP_E255 via the NV_PMU_BOARDOBJ_CMD_GRP GET_STATUS +* interface. +* +* @para _eng Name of implementing engine in which this structure is +* found. +* @param _class Class ID of Objects within Board Object Group. +*/ +#define NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E255(_eng, _class) \ + NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE(_eng, _class, \ + CTRL_BOARDOBJGRP_E255_MAX_OBJECTS) + + +#endif /* _GPMUIFBOARDOBJ_H_ */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h new file mode 100644 index 00000000..c080197f --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h @@ -0,0 +1,455 @@ +/* +* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms and conditions of the GNU General Public License, +* version 2, as published by the Free Software Foundation. +* +* This program is distributed in the hope it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +*/ + +#ifndef _GPMUIFCLK_H_ +#define _GPMUIFCLK_H_ + +#include "ctrl/ctrlboardobj.h" +#include "ctrl/ctrlvolt.h" +#include "ctrl/ctrlperf.h" +#include "ctrl/ctrlclk.h" +#include "gpmuifboardobj.h" +#include "gpmuifvolt.h" +#include + +enum nv_pmu_clk_clkwhich { + clkwhich_mclk = 5, + clkwhich_dispclk = 7, + clkwhich_gpc2clk = 17, + clkwhich_xbar2clk = 19, + clkwhich_sys2clk = 20, + clkwhich_hub2clk = 21, + clkwhich_pwrclk = 24, + clkwhich_nvdclk = 25, + clkwhich_pciegenclk = 31, +}; + +/* + * Enumeration of BOARDOBJGRP class IDs within OBJCLK. Used as "classId" + * argument for communications between Kernel and PMU via the various generic + * BOARDOBJGRP interfaces. + */ +#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_DOMAIN 0x00 +#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_PROG 0x01 +#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_VIN_DEVICE 0x02 +#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_FLL_DEVICE 0x03 +#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_VF_POINT 0x04 +#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_FREQ_CONTROLLER 0x05 + +/*! +* CLK_DOMAIN BOARDOBJGRP Header structure. Describes global state about the +* CLK_DOMAIN feature. +*/ +struct nv_pmu_clk_clk_domain_boardobjgrp_set_header { + struct nv_pmu_boardobjgrp_e32 super; + u32 vbios_domains; + struct ctrl_boardobjgrp_mask_e32 master_domains_mask; + u16 cntr_sampling_periodms; + bool b_override_o_v_o_c; + bool b_debug_mode; + bool b_enforce_vf_monotonicity; + bool b_enforce_vf_smoothening; + u8 volt_rails_max; + struct ctrl_clk_clk_delta deltas; +}; + +struct nv_pmu_clk_clk_domain_boardobj_set { + struct nv_pmu_boardobj super; + enum nv_pmu_clk_clkwhich domain; + u32 api_domain; + u8 perf_domain_grp_idx; +}; + +struct nv_pmu_clk_clk_domain_3x_boardobj_set { + struct nv_pmu_clk_clk_domain_boardobj_set super; + bool b_noise_aware_capable; +}; + +struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set { + struct nv_pmu_clk_clk_domain_3x_boardobj_set super; + u16 freq_mhz; +}; + +struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set { + struct nv_pmu_clk_clk_domain_3x_boardobj_set super; + u8 clk_prog_idx_first; + u8 clk_prog_idx_last; + u8 noise_unaware_ordering_index; + u8 noise_aware_ordering_index; + bool b_force_noise_unaware_ordering; + int factory_offset_khz; + short freq_delta_min_mhz; + short freq_delta_max_mhz; + struct ctrl_clk_clk_delta deltas; +}; + +struct nv_pmu_clk_clk_domain_3x_master_boardobj_set { + struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; + u32 slave_idxs_mask; +}; + +struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set { + struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; + u8 master_idx; +}; + +union nv_pmu_clk_clk_domain_boardobj_set_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_clk_clk_domain_boardobj_set super; + struct nv_pmu_clk_clk_domain_3x_boardobj_set v3x; + struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set v3x_fixed; + struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set v3x_prog; + struct nv_pmu_clk_clk_domain_3x_master_boardobj_set v3x_master; + struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set v3x_slave; +}; + +NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_domain); + +struct nv_pmu_clk_clk_prog_boardobjgrp_set_header { + struct nv_pmu_boardobjgrp_e255 super; + u8 slave_entry_count; + u8 vf_entry_count; +}; + +struct nv_pmu_clk_clk_prog_boardobj_set { + struct nv_pmu_boardobj super; +}; + +struct nv_pmu_clk_clk_prog_1x_boardobj_set { + struct nv_pmu_clk_clk_prog_boardobj_set super; + u8 source; + u16 freq_max_mhz; + union ctrl_clk_clk_prog_1x_source_data source_data; +}; + +struct nv_pmu_clk_clk_prog_1x_master_boardobj_set { + struct nv_pmu_clk_clk_prog_1x_boardobj_set super; + bool b_o_c_o_v_enabled; + struct ctrl_clk_clk_prog_1x_master_vf_entry vf_entries[ + CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES]; + union ctrl_clk_clk_prog_1x_master_source_data source_data; + struct ctrl_clk_clk_delta deltas; +}; + +struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set { + struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super; + struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry slave_entries[ + CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES]; +}; + +struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set { + struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super; + struct ctrl_clk_clk_prog_1x_master_table_slave_entry + slave_entries[CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES]; +}; + +union nv_pmu_clk_clk_prog_boardobj_set_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_clk_clk_prog_boardobj_set super; + struct nv_pmu_clk_clk_prog_1x_boardobj_set v1x; + struct nv_pmu_clk_clk_prog_1x_master_boardobj_set v1x_master; + struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set v1x_master_ratio; + struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set v1x_master_table; +}; + +NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(clk, clk_prog); + +struct nv_pmu_clk_lut_device_desc { + u8 vselect_mode; + u16 hysteresis_threshold; +}; + +struct nv_pmu_clk_regime_desc { + u8 regime_id; + u16 fixed_freq_regime_limit_mhz; +}; + +struct nv_pmu_clk_clk_fll_device_boardobjgrp_set_header { + struct nv_pmu_boardobjgrp_e32 super; + struct ctrl_boardobjgrp_mask_e32 lut_prog_master_mask; + u32 lut_step_size_uv; + u32 lut_min_voltage_uv; + u8 lut_num_entries; + u16 max_min_freq_mhz; +}; + +struct nv_pmu_clk_clk_fll_device_boardobj_set { + struct nv_pmu_boardobj super; + u8 id; + u8 mdiv; + u8 vin_idx_logic; + u8 vin_idx_sram; + u8 rail_idx_for_lut; + u16 input_freq_mhz; + u32 clk_domain; + struct nv_pmu_clk_lut_device_desc lut_device; + struct nv_pmu_clk_regime_desc regime_desc; + u8 min_freq_vfe_idx; + u8 freq_ctrl_idx; + struct ctrl_boardobjgrp_mask_e32 lut_prog_broadcast_slave_mask; +}; + +union nv_pmu_clk_clk_fll_device_boardobj_set_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_clk_clk_fll_device_boardobj_set super; +}; + +NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_fll_device); + +struct nv_pmu_clk_clk_vin_device_boardobjgrp_set_header { + struct nv_pmu_boardobjgrp_e32 super; + bool b_vin_is_disable_allowed; +}; + +struct nv_pmu_clk_clk_vin_device_boardobj_set { + struct nv_pmu_boardobj super; + u8 id; + u8 volt_domain; + u32 slope; + u32 intercept; + u32 flls_shared_mask; +}; + +union nv_pmu_clk_clk_vin_device_boardobj_set_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_clk_clk_vin_device_boardobj_set super; +}; + +NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_vin_device); + +struct nv_pmu_clk_clk_vf_point_boardobjgrp_set_header { + struct nv_pmu_boardobjgrp_e255 super; +}; + +struct nv_pmu_clk_clk_vf_point_boardobj_set { + struct nv_pmu_boardobj super; + u8 vfe_equ_idx; + u8 volt_rail_idx; +}; + +struct nv_pmu_clk_clk_vf_point_freq_boardobj_set { + struct nv_pmu_clk_clk_vf_point_boardobj_set super; + u16 freq_mhz; + int volt_delta_uv; +}; + +struct nv_pmu_clk_clk_vf_point_volt_boardobj_set { + struct nv_pmu_clk_clk_vf_point_boardobj_set super; + u32 source_voltage_uv; + int freq_delta_khz; +}; + +union nv_pmu_clk_clk_vf_point_boardobj_set_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_clk_clk_vf_point_boardobj_set super; + struct nv_pmu_clk_clk_vf_point_freq_boardobj_set freq; + struct nv_pmu_clk_clk_vf_point_volt_boardobj_set volt; +}; + +NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(clk, clk_vf_point); + +struct nv_pmu_clk_clk_vf_point_boardobjgrp_get_status_header { + struct nv_pmu_boardobjgrp_e255 super; +}; + +struct nv_pmu_clk_clk_vf_point_boardobj_get_status { + struct nv_pmu_boardobj super; + struct ctrl_clk_vf_pair pair; +}; + +struct nv_pmu_clk_clk_vf_point_volt_boardobj_get_status { + struct nv_pmu_clk_clk_vf_point_boardobj_get_status super; + u16 vf_gain_value; +}; + +union nv_pmu_clk_clk_vf_point_boardobj_get_status_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_clk_clk_vf_point_boardobj_get_status super; + struct nv_pmu_clk_clk_vf_point_volt_boardobj_get_status volt; +}; + +NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E255(clk, clk_vf_point); + +#define NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS (12) + +struct nv_pmu_clk_clk_domain_list { + u8 num_domains; + struct ctrl_clk_clk_domain_list_item clk_domains[ + NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS]; +}; + +struct nv_pmu_clk_vf_change_inject { + u8 flags; + struct nv_pmu_clk_clk_domain_list clk_list; + struct nv_pmu_volt_volt_rail_list volt_list; +}; + +#define NV_NV_PMU_CLK_LOAD_FEATURE_VIN (0x00000002) +#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_VIN_HW_CAL_PROGRAM_YES (0x00000001) + +struct nv_pmu_clk_load_payload_freq_controllers { + struct ctrl_boardobjgrp_mask_e32 load_mask; +}; + +struct nv_pmu_clk_load { + u8 feature; + u32 action_mask; + union { + struct nv_pmu_clk_load_payload_freq_controllers freq_controllers; + } payload; +}; +/* CLK_FREQ_CONTROLLER */ +#define NV_NV_PMU_CLK_LOAD_FEATURE_FREQ_CONTROLLER (0x00000003) + +#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_NO (0x00000000) +#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_YES (0x00000002) + +struct nv_pmu_clk_clk_freq_controller_boardobjgrp_set_header { + struct nv_pmu_boardobjgrp_e32 super; + u32 sampling_period_ms; + u8 volt_policy_idx; +}; + +struct nv_pmu_clk_clk_freq_controller_boardobj_set { + struct nv_pmu_boardobj super; + u8 controller_id; + u8 parts_freq_mode; + bool bdisable; + u32 clk_domain; + s16 freq_cap_noise_unaware_vmin_above; + s16 freq_cap_noise_unaware_vmin_below; + s16 freq_hyst_pos_mhz; + s16 freq_hyst_neg_mhz; +}; + +struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set { + struct nv_pmu_clk_clk_freq_controller_boardobj_set super; + s32 prop_gain; + s32 integ_gain; + s32 integ_decay; + s32 volt_delta_min; + s32 volt_delta_max; + u8 slowdown_pct_min; + bool bpoison; +}; + +union nv_pmu_clk_clk_freq_controller_boardobj_set_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_clk_clk_freq_controller_boardobj_set super; + struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set pi; +}; + +NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_freq_controller); + +/* CLK CMD ID definitions. */ +#define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_SET (0x00000000) +#define NV_PMU_CLK_CMD_ID_RPC (0x00000001) +#define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) + +#define NV_PMU_CLK_RPC_ID_LOAD (0x00000002) +#define NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT (0x00000001) + +struct nv_pmu_clk_cmd_rpc { + u8 cmd_type; + u8 pad[3]; + struct nv_pmu_allocation request; +}; + +#define NV_PMU_CLK_CMD_RPC_ALLOC_OFFSET \ + (offsetof(struct nv_pmu_clk_cmd_rpc, request)) + +struct nv_pmu_clk_cmd { + union { + u8 cmd_type; + struct nv_pmu_boardobj_cmd_grp grp_set; + struct nv_pmu_clk_cmd_rpc rpc; + struct nv_pmu_boardobj_cmd_grp grp_get_status; + }; +}; + +struct nv_pmu_clk_rpc { + u8 function; + bool b_supported; + bool b_success; + flcn_status flcn_status; + union { + struct nv_pmu_clk_vf_change_inject clk_vf_change_inject; + struct nv_pmu_clk_load clk_load; + } params; +}; + +/* CLK MSG ID definitions */ +#define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_SET (0x00000000) +#define NV_PMU_CLK_MSG_ID_RPC (0x00000001) +#define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) + +struct nv_pmu_clk_msg_rpc { + u8 msg_type; + u8 rsvd[3]; + struct nv_pmu_allocation response; +}; + +#define NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET \ + offsetof(struct nv_pmu_clk_msg_rpc, response) + +struct nv_pmu_clk_msg { + union { + u8 msg_type; + struct nv_pmu_boardobj_msg_grp grp_set; + struct nv_pmu_clk_msg_rpc rpc; + struct nv_pmu_boardobj_msg_grp grp_get_status; + }; +}; + +struct nv_pmu_clk_clk_vin_device_boardobjgrp_get_status_header { + struct nv_pmu_boardobjgrp_e32 super; +}; + +struct nv_pmu_clk_clk_vin_device_boardobj_get_status { + struct nv_pmu_boardobj_query super; + u32 actual_voltage_uv; + u32 corrected_voltage_uv; + u8 sampled_code; + u8 override_code; +}; + +union nv_pmu_clk_clk_vin_device_boardobj_get_status_union { + struct nv_pmu_boardobj_query board_obj; + struct nv_pmu_clk_clk_vin_device_boardobj_get_status super; +}; + +NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(clk, clk_vin_device); + +struct nv_pmu_clk_lut_vf_entry { + u32 entry; +}; + +struct nv_pmu_clk_clk_fll_device_boardobjgrp_get_status_header { + struct nv_pmu_boardobjgrp_e32 super; +}; + +struct nv_pmu_clk_clk_fll_device_boardobj_get_status { + struct nv_pmu_boardobj_query super; + u8 current_regime_id; + u16 min_freq_mhz; + struct nv_pmu_clk_lut_vf_entry lut_vf_curve[NV_UNSIGNED_ROUNDED_DIV(CTRL_CLK_LUT_NUM_ENTRIES, 2)]; +}; + +union nv_pmu_clk_clk_fll_device_boardobj_get_status_union { + struct nv_pmu_boardobj_query board_obj; + struct nv_pmu_clk_clk_fll_device_boardobj_get_status super; +}; + +NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(clk, clk_fll_device); + +#endif /*_GPMUIFCLK_H_*/ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h new file mode 100644 index 00000000..9a9a92be --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperf.h @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _GPMUIFPERF_H_ +#define _GPMUIFPERF_H_ + +#include "gpmuifvolt.h" +#include "gpmuifperfvfe.h" + +/* +* Enumeration of BOARDOBJGRP class IDs within OBJPERF. Used as "classId" +* argument for communications between Kernel and PMU via the various generic +* BOARDOBJGRP interfaces. +*/ +#define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_VAR 0x00 +#define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_EQU 0x01 + +#define NV_PMU_PERF_CMD_ID_RPC (0x00000002) +#define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_SET (0x00000003) +#define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000004) + +struct nv_pmu_perf_cmd_set_object { + u8 cmd_type; + u8 pad[2]; + u8 object_type; + struct nv_pmu_allocation object; +}; + +#define NV_PMU_PERF_SET_OBJECT_ALLOC_OFFSET \ + (offsetof(struct nv_pmu_perf_cmd_set_object, object)) + +/* RPC IDs */ +#define NV_PMU_PERF_RPC_ID_VFE_LOAD (0x00000001) + +/*! +* Command requesting execution of the perf RPC. +*/ +struct nv_pmu_perf_cmd_rpc { + u8 cmd_type; + u8 pad[3]; + struct nv_pmu_allocation request; +}; + +#define NV_PMU_PERF_CMD_RPC_ALLOC_OFFSET \ + offsetof(struct nv_pmu_perf_cmd_rpc, request) + +/*! +* Simply a union of all specific PERF commands. Forms the general packet +* exchanged between the Kernel and PMU when sending and receiving PERF commands +* (respectively). +*/ +struct nv_pmu_perf_cmd { + union { + u8 cmd_type; + struct nv_pmu_perf_cmd_set_object set_object; + struct nv_pmu_boardobj_cmd_grp grp_set; + struct nv_pmu_boardobj_cmd_grp grp_get_status; + }; +}; + +/*! +* Defines the data structure used to invoke PMU perf RPCs. Same structure is +* used to return the result of the RPC execution. +*/ +struct nv_pmu_perf_rpc { + u8 function; + bool b_supported; + bool b_success; + flcn_status flcn_status; + union { + struct nv_pmu_perf_rpc_vfe_equ_eval vfe_equ_eval; + struct nv_pmu_perf_rpc_vfe_load vfe_load; + } params; +}; + + +/* PERF Message-type Definitions */ +#define NV_PMU_PERF_MSG_ID_RPC (0x00000003) +#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_SET (0x00000004) +#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000006) +#define NV_PMU_PERF_MSG_ID_VFE_CALLBACK (0x00000005) + +/*! +* Message carrying the result of the perf RPC execution. +*/ +struct nv_pmu_perf_msg_rpc { + u8 msg_type; + u8 rsvd[3]; + struct nv_pmu_allocation response; +}; + +#define NV_PMU_PERF_MSG_RPC_ALLOC_OFFSET \ + (offsetof(struct nv_pmu_perf_msg_rpc, response)) + +/*! +* Simply a union of all specific PERF messages. Forms the general packet +* exchanged between the Kernel and PMU when sending and receiving PERF messages +* (respectively). +*/ +struct nv_pmu_perf_msg { + union { + u8 msg_type; + struct nv_pmu_perf_msg_rpc rpc; + struct nv_pmu_boardobj_msg_grp grp_set; + }; +}; + +#endif /* _GPMUIFPERF_H_*/ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h new file mode 100644 index 00000000..5f5cafbf --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _GPMUIFPERFVFE_H_ +#define _GPMUIFPERFVFE_H_ + +#include "gpmuifbios.h" +#include "gpmuifboardobj.h" + +#define CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT 0x03 +#define NV_PMU_PERF_RPC_VFE_EQU_EVAL_VAR_COUNT_MAX 2 +#define NV_PMU_PERF_RPC_VFE_EQU_MONITOR_COUNT_MAX 16 +#define NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX 1 + +struct nv_pmu_perf_vfe_var_value { + u8 var_type; + u8 reserved[3]; + u32 var_value; +}; + +union nv_pmu_perf_vfe_equ_result { + u32 freq_m_hz; + u32 voltu_v; + u32 vf_gain; + int volt_deltau_v; +}; + +struct nv_pmu_perf_rpc_vfe_equ_eval { + u8 equ_idx; + u8 var_count; + u8 output_type; + struct nv_pmu_perf_vfe_var_value var_values[ + NV_PMU_PERF_RPC_VFE_EQU_EVAL_VAR_COUNT_MAX]; + union nv_pmu_perf_vfe_equ_result result; +}; + +struct nv_pmu_perf_rpc_vfe_load { + bool b_load; +}; + +struct nv_pmu_perf_vfe_var_boardobjgrp_get_status_header { + struct nv_pmu_boardobjgrp_e32 super; +}; + +struct nv_pmu_perf_vfe_var_get_status_super { + struct nv_pmu_boardobj_query board_obj; +}; + +struct nv_pmu_perf_vfe_var_single_sensed_fuse_get_status { + struct nv_pmu_perf_vfe_var_get_status_super super; + u32 fuse_value_integer; + u32 fuse_value_hw_integer; + u8 fuse_version; + bool b_version_check_failed; +}; + +union nv_pmu_perf_vfe_var_boardobj_get_status_union { + struct nv_pmu_boardobj_query board_obj; + struct nv_pmu_perf_vfe_var_get_status_super super; + struct nv_pmu_perf_vfe_var_single_sensed_fuse_get_status fuse_status; +}; + +NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(perf, vfe_var); + +struct nv_pmu_vfe_var { + struct nv_pmu_boardobj super; + u32 out_range_min; + u32 out_range_max; +}; + +struct nv_pmu_vfe_var_derived { + struct nv_pmu_vfe_var super; +}; + +struct nv_pmu_vfe_var_derived_product { + struct nv_pmu_vfe_var_derived super; + u8 var_idx0; + u8 var_idx1; +}; + +struct nv_pmu_vfe_var_derived_sum { + struct nv_pmu_vfe_var_derived super; + u8 var_idx0; + u8 var_idx1; +}; + +struct nv_pmu_vfe_var_single { + struct nv_pmu_vfe_var super; + u8 override_type; + u32 override_value; +}; + +struct nv_pmu_vfe_var_single_frequency { + struct nv_pmu_vfe_var_single super; +}; + +struct nv_pmu_vfe_var_single_sensed { + struct nv_pmu_vfe_var_single super; +}; + +struct nv_pmu_vfe_var_single_sensed_fuse_info { + u8 segment_count; + union nv_pmu_bios_vfield_register_segment segments[ + NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX]; +}; + +struct nv_pmu_vfe_var_single_sensed_fuse_vfield_info { + struct nv_pmu_vfe_var_single_sensed_fuse_info fuse; + u32 fuse_val_default; + int hw_correction_scale; + int hw_correction_offset; + u8 v_field_id; +}; + +struct nv_pmu_vfe_var_single_sensed_fuse_ver_vfield_info { + struct nv_pmu_vfe_var_single_sensed_fuse_info fuse; + u8 ver_expected; + bool b_ver_check; + bool b_use_default_on_ver_check_fail; + u8 v_field_id_ver; +}; + +struct nv_pmu_vfe_var_single_sensed_fuse_override_info { + u32 fuse_val_override; + bool b_fuse_regkey_override; +}; + +struct nv_pmu_vfe_var_single_sensed_fuse { + struct nv_pmu_vfe_var_single_sensed super; + struct nv_pmu_vfe_var_single_sensed_fuse_override_info override_info; + struct nv_pmu_vfe_var_single_sensed_fuse_vfield_info vfield_info; + struct nv_pmu_vfe_var_single_sensed_fuse_ver_vfield_info vfield_ver_info; +}; + +struct nv_pmu_vfe_var_single_sensed_temp { + struct nv_pmu_vfe_var_single_sensed super; + u8 therm_channel_index; + int temp_hysteresis_positive; + int temp_hysteresis_negative; + int temp_default; +}; + +struct nv_pmu_vfe_var_single_voltage { + struct nv_pmu_vfe_var_single super; +}; + +struct nv_pmu_perf_vfe_var_boardobjgrp_set_header { + struct nv_pmu_boardobjgrp_e32 super; + u8 polling_periodms; +}; + +union nv_pmu_perf_vfe_var_boardobj_set_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_vfe_var var; + struct nv_pmu_vfe_var_derived var_derived; + struct nv_pmu_vfe_var_derived_product var_derived_product; + struct nv_pmu_vfe_var_derived_sum var_derived_sum; + struct nv_pmu_vfe_var_single var_single; + struct nv_pmu_vfe_var_single_frequency var_single_frequiency; + struct nv_pmu_vfe_var_single_sensed var_single_sensed; + struct nv_pmu_vfe_var_single_sensed_fuse var_single_sensed_fuse; + struct nv_pmu_vfe_var_single_sensed_temp var_single_sensed_temp; + struct nv_pmu_vfe_var_single_voltage var_single_voltage; +}; + +NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(perf, vfe_var); + +struct nv_pmu_vfe_equ { + struct nv_pmu_boardobj super; + u8 var_idx; + u8 equ_idx_next; + u8 output_type; + u32 out_range_min; + u32 out_range_max; +}; + +struct nv_pmu_vfe_equ_compare { + struct nv_pmu_vfe_equ super; + u8 func_id; + u8 equ_idx_true; + u8 equ_idx_false; + u32 criteria; +}; + +struct nv_pmu_vfe_equ_minmax { + struct nv_pmu_vfe_equ super; + bool b_max; + u8 equ_idx0; + u8 equ_idx1; +}; + +struct nv_pmu_vfe_equ_quadratic { + struct nv_pmu_vfe_equ super; + u32 coeffs[CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT]; +}; + +struct nv_pmu_perf_vfe_equ_boardobjgrp_set_header { + struct nv_pmu_boardobjgrp_e255 super; +}; + +union nv_pmu_perf_vfe_equ_boardobj_set_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_vfe_equ equ; + struct nv_pmu_vfe_equ_compare equ_comapre; + struct nv_pmu_vfe_equ_minmax equ_minmax; + struct nv_pmu_vfe_equ_quadratic equ_quadratic; +}; + +NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(perf, vfe_equ); + +#endif /* _GPMUIFPERFVFE_H_*/ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifpmgr.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifpmgr.h new file mode 100644 index 00000000..f956ab76 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifpmgr.h @@ -0,0 +1,434 @@ +/* +* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms and conditions of the GNU General Public License, +* version 2, as published by the Free Software Foundation. +* +* This program is distributed in the hope it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +*/ + +#ifndef _GPMUIFPMGR_H_ +#define _GPMUIFPMGR_H_ + +#include "ctrl/ctrlpmgr.h" +#include "gpmuifboardobj.h" +#include + +struct nv_pmu_pmgr_i2c_device_desc { + struct nv_pmu_boardobj super; + u8 dcb_index; + u16 i2c_address; + u32 i2c_flags; + u8 i2c_port; +}; + +#define NV_PMU_PMGR_I2C_DEVICE_DESC_TABLE_MAX_DEVICES (32) + +struct nv_pmu_pmgr_i2c_device_desc_table { + u32 dev_mask; + struct nv_pmu_pmgr_i2c_device_desc + devices[NV_PMU_PMGR_I2C_DEVICE_DESC_TABLE_MAX_DEVICES]; +}; + +struct nv_pmu_pmgr_pwr_device_desc { + struct nv_pmu_boardobj super; + u32 power_corr_factor; +}; + +#define NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM 0x03 + +struct nv_pmu_pmgr_pwr_device_desc_ina3221 { + struct nv_pmu_pmgr_pwr_device_desc super; + u8 i2c_dev_idx; + struct ctrl_pmgr_pwr_device_info_rshunt + r_shuntm_ohm[NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM]; + u16 configuration; + u16 mask_enable; + u32 event_mask; + u16 curr_correct_m; + s16 curr_correct_b; +}; + +union nv_pmu_pmgr_pwr_device_desc_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_pmgr_pwr_device_desc pwr_dev; + struct nv_pmu_pmgr_pwr_device_desc_ina3221 ina3221; +}; + +struct nv_pmu_pmgr_pwr_device_ba_info { + bool b_initialized_and_used; +}; + +struct nv_pmu_pmgr_pwr_device_desc_table_header { + struct nv_pmu_boardobjgrp_e32 super; + struct nv_pmu_pmgr_pwr_device_ba_info ba_info; +}; + +NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_device_desc_table_header, + sizeof(struct nv_pmu_pmgr_pwr_device_desc_table_header)); +NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_device_desc_union, + sizeof(union nv_pmu_pmgr_pwr_device_desc_union)); + +struct nv_pmu_pmgr_pwr_device_desc_table { + union nv_pmu_pmgr_pwr_device_desc_table_header_aligned hdr; + union nv_pmu_pmgr_pwr_device_desc_union_aligned + devices[CTRL_PMGR_PWR_DEVICES_MAX_DEVICES]; +}; + +union nv_pmu_pmgr_pwr_device_dmem_size { + union nv_pmu_pmgr_pwr_device_desc_table_header_aligned pwr_device_hdr; + union nv_pmu_pmgr_pwr_device_desc_union_aligned pwr_device; +}; + +struct nv_pmu_pmgr_pwr_channel { + struct nv_pmu_boardobj super; + u8 pwr_rail; + u8 ch_idx; + u32 volt_fixedu_v; + u32 pwr_corr_slope; + s32 pwr_corr_offsetm_w; + u32 curr_corr_slope; + s32 curr_corr_offsetm_a; + u32 dependent_ch_mask; +}; + +#define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHANNELS 16 + +#define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHRELATIONSHIPS 16 + +struct nv_pmu_pmgr_pwr_channel_sensor { + struct nv_pmu_pmgr_pwr_channel super; + u8 pwr_dev_idx; + u8 pwr_dev_prov_idx; +}; + +struct nv_pmu_pmgr_pwr_channel_pmu_compactible { + u8 pmu_compactible_data[56]; +}; + +union nv_pmu_pmgr_pwr_channel_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_pmgr_pwr_channel pwr_channel; + struct nv_pmu_pmgr_pwr_channel_sensor sensor; + struct nv_pmu_pmgr_pwr_channel_pmu_compactible pmu_pwr_channel; +}; + +#define NV_PMU_PMGR_PWR_MONITOR_TYPE_NO_POLLING 0x02 + +struct nv_pmu_pmgr_pwr_monitor_pstate { + u32 hw_channel_mask; +}; + +union nv_pmu_pmgr_pwr_monitor_type_specific { + struct nv_pmu_pmgr_pwr_monitor_pstate pstate; +}; + +struct nv_pmu_pmgr_pwr_chrelationship_pmu_compactible { + u8 pmu_compactible_data[28]; +}; + +union nv_pmu_pmgr_pwr_chrelationship_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_pmgr_pwr_chrelationship_pmu_compactible pmu_pwr_chrelationship; +}; + +struct nv_pmu_pmgr_pwr_channel_header { + struct nv_pmu_boardobjgrp_e32 super; + u8 type; + union nv_pmu_pmgr_pwr_monitor_type_specific type_specific; + u8 sample_count; + u16 sampling_periodms; + u16 sampling_period_low_powerms; + u32 total_gpu_power_channel_mask; + u32 physical_channel_mask; +}; + +struct nv_pmu_pmgr_pwr_chrelationship_header { + struct nv_pmu_boardobjgrp_e32 super; +}; + +NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_channel_header, + sizeof(struct nv_pmu_pmgr_pwr_channel_header)); +NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_chrelationship_header, + sizeof(struct nv_pmu_pmgr_pwr_chrelationship_header)); +NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_chrelationship_union, + sizeof(union nv_pmu_pmgr_pwr_chrelationship_union)); +NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_channel_union, + sizeof(union nv_pmu_pmgr_pwr_channel_union)); + +struct nv_pmu_pmgr_pwr_channel_desc { + union nv_pmu_pmgr_pwr_channel_header_aligned hdr; + union nv_pmu_pmgr_pwr_channel_union_aligned + channels[NV_PMU_PMGR_PWR_CHANNEL_MAX_CHANNELS]; +}; + +struct nv_pmu_pmgr_pwr_chrelationship_desc { + union nv_pmu_pmgr_pwr_chrelationship_header_aligned hdr; + union nv_pmu_pmgr_pwr_chrelationship_union_aligned + ch_rels[NV_PMU_PMGR_PWR_CHANNEL_MAX_CHRELATIONSHIPS]; +}; + +union nv_pmu_pmgr_pwr_monitor_dmem_size { + union nv_pmu_pmgr_pwr_channel_header_aligned channel_hdr; + union nv_pmu_pmgr_pwr_channel_union_aligned channel; + union nv_pmu_pmgr_pwr_chrelationship_header_aligned ch_rels_hdr; + union nv_pmu_pmgr_pwr_chrelationship_union_aligned ch_rels; +}; + +struct nv_pmu_pmgr_pwr_monitor_pack { + struct nv_pmu_pmgr_pwr_channel_desc channels; + struct nv_pmu_pmgr_pwr_chrelationship_desc ch_rels; +}; + +#define NV_PMU_PMGR_PWR_POLICY_MAX_POLICIES 32 + +#define NV_PMU_PMGR_PWR_POLICY_MAX_POLICY_RELATIONSHIPS 32 + +struct nv_pmu_pmgr_pwr_policy { + struct nv_pmu_boardobj super; + u8 ch_idx; + u8 num_limit_inputs; + u8 limit_unit; + u8 sample_mult; + u32 limit_curr; + u32 limit_min; + u32 limit_max; + struct ctrl_pmgr_pwr_policy_info_integral integral; + enum ctrl_pmgr_pwr_policy_filter_type filter_type; + union ctrl_pmgr_pwr_policy_filter_param filter_param; +}; + +struct nv_pmu_pmgr_pwr_policy_hw_threshold { + struct nv_pmu_pmgr_pwr_policy super; + u8 threshold_idx; + u8 low_threshold_idx; + bool b_use_low_threshold; + u16 low_threshold_value; +}; + +struct nv_pmu_pmgr_pwr_policy_sw_threshold { + struct nv_pmu_pmgr_pwr_policy super; + u8 threshold_idx; + u8 low_threshold_idx; + bool b_use_low_threshold; + u16 low_threshold_value; + u8 event_id; +}; + +struct nv_pmu_pmgr_pwr_policy_pmu_compactible { + u8 pmu_compactible_data[68]; +}; + +union nv_pmu_pmgr_pwr_policy_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_pmgr_pwr_policy pwr_policy; + struct nv_pmu_pmgr_pwr_policy_hw_threshold hw_threshold; + struct nv_pmu_pmgr_pwr_policy_sw_threshold sw_threshold; + struct nv_pmu_pmgr_pwr_policy_pmu_compactible pmu_pwr_policy; +}; + +struct nv_pmu_pmgr_pwr_policy_relationship_pmu_compactible { + u8 pmu_compactible_data[24]; +}; + +union nv_pmu_pmgr_pwr_policy_relationship_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_pmgr_pwr_policy_relationship_pmu_compactible pmu_pwr_relationship; +}; + +struct nv_pmu_pmgr_pwr_violation_pmu_compactible { + u8 pmu_compactible_data[16]; +}; + +union nv_pmu_pmgr_pwr_violation_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_pmgr_pwr_violation_pmu_compactible violation; +}; + +#define NV_PMU_PMGR_PWR_POLICY_DESC_TABLE_VERSION_3X 0x30 + +NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_policy_union, + sizeof(union nv_pmu_pmgr_pwr_policy_union)); +NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_policy_relationship_union, + sizeof(union nv_pmu_pmgr_pwr_policy_relationship_union)); + +#define NV_PMU_PERF_DOMAIN_GROUP_MAX_GROUPS 2 + +struct nv_pmu_perf_domain_group_limits +{ + u32 values[NV_PMU_PERF_DOMAIN_GROUP_MAX_GROUPS]; +} ; + +#define NV_PMU_PMGR_RESERVED_PWR_POLICY_MASK_COUNT 0x6 + +struct nv_pmu_pmgr_pwr_policy_desc_header { + struct nv_pmu_boardobjgrp_e32 super; + u8 version; + bool b_enabled; + u8 low_sampling_mult; + u8 semantic_policy_tbl[CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES]; + u16 base_sample_period; + u16 min_client_sample_period; + u32 reserved_pmu_policy_mask[NV_PMU_PMGR_RESERVED_PWR_POLICY_MASK_COUNT]; + struct nv_pmu_perf_domain_group_limits global_ceiling; +}; + +NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_policy_desc_header , + sizeof(struct nv_pmu_pmgr_pwr_policy_desc_header )); + +struct nv_pmu_pmgr_pwr_policyrel_desc_header { + struct nv_pmu_boardobjgrp_e32 super; +}; + +NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_policyrel_desc_header, + sizeof(struct nv_pmu_pmgr_pwr_policyrel_desc_header)); + +struct nv_pmu_pmgr_pwr_violation_desc_header { + struct nv_pmu_boardobjgrp_e32 super; +}; + +NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_violation_desc_header, + sizeof(struct nv_pmu_pmgr_pwr_violation_desc_header)); +NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_violation_union, + sizeof(union nv_pmu_pmgr_pwr_violation_union)); + +struct nv_pmu_pmgr_pwr_policy_desc { + union nv_pmu_pmgr_pwr_policy_desc_header_aligned hdr; + union nv_pmu_pmgr_pwr_policy_union_aligned + policies[NV_PMU_PMGR_PWR_POLICY_MAX_POLICIES]; +}; + +struct nv_pmu_pmgr_pwr_policyrel_desc { + union nv_pmu_pmgr_pwr_policyrel_desc_header_aligned hdr; + union nv_pmu_pmgr_pwr_policy_relationship_union_aligned + policy_rels[NV_PMU_PMGR_PWR_POLICY_MAX_POLICY_RELATIONSHIPS]; +}; + +struct nv_pmu_pmgr_pwr_violation_desc { + union nv_pmu_pmgr_pwr_violation_desc_header_aligned hdr; + union nv_pmu_pmgr_pwr_violation_union_aligned + violations[CTRL_PMGR_PWR_VIOLATION_MAX]; +}; + +union nv_pmu_pmgr_pwr_policy_dmem_size { + union nv_pmu_pmgr_pwr_policy_desc_header_aligned policy_hdr; + union nv_pmu_pmgr_pwr_policy_union_aligned policy; + union nv_pmu_pmgr_pwr_policyrel_desc_header_aligned policy_rels_hdr; + union nv_pmu_pmgr_pwr_policy_relationship_union_aligned policy_rels; + union nv_pmu_pmgr_pwr_violation_desc_header_aligned violation_hdr; + union nv_pmu_pmgr_pwr_violation_union_aligned violation; +}; + +struct nv_pmu_pmgr_pwr_policy_pack { + struct nv_pmu_pmgr_pwr_policy_desc policies; + struct nv_pmu_pmgr_pwr_policyrel_desc policy_rels; + struct nv_pmu_pmgr_pwr_violation_desc violations; +}; + +#define NV_PMU_PMGR_CMD_ID_SET_OBJECT (0x00000000) + +#define NV_PMU_PMGR_MSG_ID_QUERY (0x00000002) + +#define NV_PMU_PMGR_CMD_ID_PWR_DEVICES_QUERY (0x00000001) + +#define NV_PMU_PMGR_CMD_ID_LOAD (0x00000006) + +#define NV_PMU_PMGR_CMD_ID_UNLOAD (0x00000007) + +struct nv_pmu_pmgr_cmd_set_object { + u8 cmd_type; + u8 pad[2]; + u8 object_type; + struct nv_pmu_allocation object; +}; + +#define NV_PMU_PMGR_SET_OBJECT_ALLOC_OFFSET (0x04) + +#define NV_PMU_PMGR_OBJECT_I2C_DEVICE_DESC_TABLE (0x00000000) + +#define NV_PMU_PMGR_OBJECT_PWR_DEVICE_DESC_TABLE (0x00000001) + +#define NV_PMU_PMGR_OBJECT_PWR_MONITOR (0x00000002) + +#define NV_PMU_PMGR_OBJECT_PWR_POLICY (0x00000005) + +struct nv_pmu_pmgr_pwr_devices_query_payload { + struct { + u32 powerm_w; + u32 voltageu_v; + u32 currentm_a; + } devices[CTRL_PMGR_PWR_DEVICES_MAX_DEVICES]; +}; + +struct nv_pmu_pmgr_cmd_pwr_devices_query { + u8 cmd_type; + u8 pad[3]; + u32 dev_mask; + struct nv_pmu_allocation payload; +}; + +#define NV_PMU_PMGR_PWR_DEVICES_QUERY_ALLOC_OFFSET (0x08) + +struct nv_pmu_pmgr_cmd_load { + u8 cmd_type; +}; + +struct nv_pmu_pmgr_cmd_unload { + u8 cmd_type; +}; + +struct nv_pmu_pmgr_cmd { + union { + u8 cmd_type; + struct nv_pmu_pmgr_cmd_set_object set_object; + struct nv_pmu_pmgr_cmd_pwr_devices_query pwr_dev_query; + struct nv_pmu_pmgr_cmd_load load; + struct nv_pmu_pmgr_cmd_unload unload; + }; +}; + +#define NV_PMU_PMGR_MSG_ID_SET_OBJECT (0x00000000) + +#define NV_PMU_PMGR_MSG_ID_LOAD (0x00000004) + +#define NV_PMU_PMGR_MSG_ID_UNLOAD (0x00000005) + +struct nv_pmu_pmgr_msg_set_object { + u8 msg_type; + bool b_success; + flcn_status flcnstatus; + u8 object_type; +}; + +struct nv_pmu_pmgr_msg_query { + u8 msg_type; + bool b_success; + flcn_status flcnstatus; + u8 cmd_type; +}; + +struct nv_pmu_pmgr_msg_load { + u8 msg_type; + bool b_success; + flcn_status flcnstatus; +}; + +struct nv_pmu_pmgr_msg_unload { + u8 msg_type; +}; + +struct nv_pmu_pmgr_msg { + union { + u8 msg_type; + struct nv_pmu_pmgr_msg_set_object set_object; + struct nv_pmu_pmgr_msg_query query; + struct nv_pmu_pmgr_msg_load load; + struct nv_pmu_pmgr_msg_unload unload; + }; +}; + +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifseq.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifseq.h new file mode 100644 index 00000000..2927206f --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifseq.h @@ -0,0 +1,73 @@ +/* +* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms and conditions of the GNU General Public License, +* version 2, as published by the Free Software Foundation. +* +* This program is distributed in the hope it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +*/ +#ifndef _GPMUIFSEQ_H_ +#define _GPMUIFSEQ_H_ + +#include + +#define PMU_UNIT_SEQ (0x02) + +/*! +* @file gpmuifseq.h +* @brief PMU Command/Message Interfaces - Sequencer +*/ + +/*! +* Defines the identifiers various high-level types of sequencer commands. +* +* _RUN_SCRIPT @ref NV_PMU_SEQ_CMD_RUN_SCRIPT +*/ +enum { + NV_PMU_SEQ_CMD_ID_RUN_SCRIPT = 0, +}; + +struct nv_pmu_seq_cmd_run_script { + u8 cmd_type; + u8 pad[3]; + struct pmu_allocation_v3 script_alloc; + struct pmu_allocation_v3 reg_alloc; +}; + +#define NV_PMU_SEQ_CMD_ALLOC_OFFSET 4 + +#define NV_PMU_SEQ_MSG_ALLOC_OFFSET \ + (NV_PMU_SEQ_CMD_ALLOC_OFFSET + NV_PMU_CMD_ALLOC_SIZE) + +struct nv_pmu_seq_cmd { + struct pmu_hdr hdr; + union { + u8 cmd_type; + struct nv_pmu_seq_cmd_run_script run_script; + }; +}; + +enum { + NV_PMU_SEQ_MSG_ID_RUN_SCRIPT = 0, +}; + +struct nv_pmu_seq_msg_run_script { + u8 msg_type; + u8 error_code; + u16 error_pc; + u32 timeout_stat; +}; + +struct nv_pmu_seq_msg { + struct pmu_hdr hdr; + union { + u8 msg_type; + struct nv_pmu_seq_msg_run_script run_script; + }; +}; + +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuiftherm.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuiftherm.h new file mode 100644 index 00000000..27e811ff --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuiftherm.h @@ -0,0 +1,93 @@ +/* +* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms and conditions of the GNU General Public License, +* version 2, as published by the Free Software Foundation. +* +* This program is distributed in the hope it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +*/ + +#ifndef _GPMUIFTHERM_H_ +#define _GPMUIFTHERM_H_ + +#include + +#define NV_PMU_THERM_CMD_ID_RPC 0x00000002 +#define NV_PMU_THERM_MSG_ID_RPC 0x00000002 +#define NV_PMU_THERM_RPC_ID_SLCT 0x00000000 +#define NV_PMU_THERM_RPC_ID_SLCT_EVENT_TEMP_TH_SET 0x00000006 +#define NV_PMU_THERM_EVENT_THERMAL_1 0x00000004 +#define NV_PMU_THERM_CMD_ID_HW_SLOWDOWN_NOTIFICATION 0x00000001 +#define NV_RM_PMU_THERM_HW_SLOWDOWN_NOTIFICATION_REQUEST_ENABLE 0x00000001 +#define NV_PMU_THERM_MSG_ID_EVENT_HW_SLOWDOWN_NOTIFICATION 0x00000001 + +struct nv_pmu_therm_rpc_slct_event_temp_th_set { + s32 temp_threshold; + u8 event_id; + flcn_status flcn_stat; +}; + +struct nv_pmu_therm_rpc_slct { + u32 mask_enabled; + flcn_status flcn_stat; +}; + +struct nv_pmu_therm_rpc { + u8 function; + bool b_supported; + union { + struct nv_pmu_therm_rpc_slct slct; + struct nv_pmu_therm_rpc_slct_event_temp_th_set slct_event_temp_th_set; + } params; +}; + +struct nv_pmu_therm_cmd_rpc { + u8 cmd_type; + u8 pad[3]; + struct nv_pmu_allocation request; +}; + +struct nv_pmu_therm_cmd_hw_slowdown_notification { + u8 cmd_type; + u8 request; +}; + +#define NV_PMU_THERM_CMD_RPC_ALLOC_OFFSET \ + offsetof(struct nv_pmu_therm_cmd_rpc, request) + +struct nv_pmu_therm_cmd { + union { + u8 cmd_type; + struct nv_pmu_therm_cmd_rpc rpc; + struct nv_pmu_therm_cmd_hw_slowdown_notification hw_slct_notification; + }; +}; + +struct nv_pmu_therm_msg_rpc { + u8 msg_type; + u8 rsvd[3]; + struct nv_pmu_allocation response; +}; + +struct nv_pmu_therm_msg_event_hw_slowdown_notification { + u8 msg_type; + u32 mask; +}; + +#define NV_PMU_THERM_MSG_RPC_ALLOC_OFFSET \ + offsetof(struct nv_pmu_therm_msg_rpc, response) + +struct nv_pmu_therm_msg { + union { + u8 msg_type; + struct nv_pmu_therm_msg_rpc rpc; + struct nv_pmu_therm_msg_event_hw_slowdown_notification hw_slct_msg; + }; +}; + +#endif + diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifthermsensor.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifthermsensor.h new file mode 100644 index 00000000..d240b344 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifthermsensor.h @@ -0,0 +1,74 @@ +/* +* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms and conditions of the GNU General Public License, +* version 2, as published by the Free Software Foundation. +* +* This program is distributed in the hope it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +*/ + +#ifndef _GPMUIFTHERMSENSOR_H_ +#define _GPMUIFTHERMSENSOR_H_ + +#include "ctrl/ctrltherm.h" +#include "gpmuifboardobj.h" +#include + +#define NV_PMU_THERM_BOARDOBJGRP_CLASS_ID_THERM_DEVICE 0x00 +#define NV_PMU_THERM_BOARDOBJGRP_CLASS_ID_THERM_CHANNEL 0x01 + +#define NV_PMU_THERM_CMD_ID_BOARDOBJ_GRP_SET 0x0000000B +#define NV_PMU_THERM_MSG_ID_BOARDOBJ_GRP_SET 0x00000008 + +struct nv_pmu_therm_therm_device_boardobjgrp_set_header { + struct nv_pmu_boardobjgrp_e32 super; +}; + +struct nv_pmu_therm_therm_device_boardobj_set { + struct nv_pmu_boardobj super; +}; + +struct nv_pmu_therm_therm_device_i2c_boardobj_set { + struct nv_pmu_therm_therm_device_boardobj_set super; + u8 i2c_dev_idx; +}; + +union nv_pmu_therm_therm_device_boardobj_set_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_therm_therm_device_boardobj_set therm_device; + struct nv_pmu_therm_therm_device_i2c_boardobj_set i2c; +}; + +NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(therm, therm_device); + +struct nv_pmu_therm_therm_channel_boardobjgrp_set_header { + struct nv_pmu_boardobjgrp_e32 super; +}; + +struct nv_pmu_therm_therm_channel_boardobj_set { + struct nv_pmu_boardobj super; + s16 scaling; + s16 offset; + s32 temp_min; + s32 temp_max; +}; + +struct nv_pmu_therm_therm_channel_device_boardobj_set { + struct nv_pmu_therm_therm_channel_boardobj_set super; + u8 therm_dev_idx; + u8 therm_dev_prov_idx; +}; + +union nv_pmu_therm_therm_channel_boardobj_set_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_therm_therm_channel_boardobj_set therm_channel; + struct nv_pmu_therm_therm_channel_device_boardobj_set device; +}; + +NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(therm, therm_channel); + +#endif diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h new file mode 100644 index 00000000..7a18caa6 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h @@ -0,0 +1,326 @@ +/* +* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. +* +* This program is free software; you can redistribute it and/or modify it +* under the terms and conditions of the GNU General Public License, +* version 2, as published by the Free Software Foundation. +* +* This program is distributed in the hope it will be useful, but WITHOUT +* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +* more details. +*/ +#ifndef _GPMUIFVOLT_H_ +#define _GPMUIFVOLT_H_ + +#include "gpmuifboardobj.h" +#include +#include "ctrl/ctrlvolt.h" + +#define NV_PMU_VOLT_VALUE_0V_IN_UV (0) + +/* ------------- VOLT_RAIL's GRP_SET defines and structures ------------- */ + +#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_RAIL 0x00 +#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_DEVICE 0x01 +#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_POLICY 0x02 + + +struct nv_pmu_volt_volt_rail_boardobjgrp_set_header { + struct nv_pmu_boardobjgrp_e32 super; +}; + +struct nv_pmu_volt_volt_rail_boardobj_set { + + struct nv_pmu_boardobj super; + u8 rel_limit_vfe_equ_idx; + u8 alt_rel_limit_vfe_equ_idx; + u8 ov_limit_vfe_equ_idx; + u8 vmin_limit_vfe_equ_idx; + u8 volt_margin_limit_vfe_equ_idx; + u8 pwr_equ_idx; + u8 volt_dev_idx_default; + struct ctrl_boardobjgrp_mask_e32 volt_dev_mask; + s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES]; +}; + +union nv_pmu_volt_volt_rail_boardobj_set_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_volt_volt_rail_boardobj_set super; +}; + +NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_rail); + +/* ------------ VOLT_DEVICE's GRP_SET defines and structures ------------ */ + +struct nv_pmu_volt_volt_device_boardobjgrp_set_header { + struct nv_pmu_boardobjgrp_e32 super; +}; + +struct nv_pmu_volt_volt_device_boardobj_set { + struct nv_pmu_boardobj super; + u32 switch_delay_us; + u32 voltage_min_uv; + u32 voltage_max_uv; + u32 volt_step_uv; +}; + +struct nv_pmu_volt_volt_device_vid_boardobj_set { + struct nv_pmu_volt_volt_device_boardobj_set super; + s32 voltage_base_uv; + s32 voltage_offset_scale_uv; + u8 gpio_pin[CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES]; + u8 vsel_mask; +}; + +struct nv_pmu_volt_volt_device_pwm_boardobj_set { + struct nv_pmu_volt_volt_device_boardobj_set super; + u32 raw_period; + s32 voltage_base_uv; + s32 voltage_offset_scale_uv; + enum nv_pmu_pmgr_pwm_source pwm_source; +}; + +union nv_pmu_volt_volt_device_boardobj_set_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_volt_volt_device_boardobj_set super; + struct nv_pmu_volt_volt_device_vid_boardobj_set vid; + struct nv_pmu_volt_volt_device_pwm_boardobj_set pwm; +}; + +NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_device); + +/* ------------ VOLT_POLICY's GRP_SET defines and structures ------------ */ +struct nv_pmu_volt_volt_policy_boardobjgrp_set_header { + + struct nv_pmu_boardobjgrp_e32 super; +}; + +struct nv_pmu_volt_volt_policy_boardobj_set { + struct nv_pmu_boardobj super; +}; +struct nv_pmu_volt_volt_policy_sr_boardobj_set { + struct nv_pmu_volt_volt_policy_boardobj_set super; + u8 rail_idx; +}; + +struct nv_pmu_volt_volt_policy_splt_r_boardobj_set { + struct nv_pmu_volt_volt_policy_boardobj_set super; + u8 rail_idx_master; + u8 rail_idx_slave; + u8 delta_min_vfe_equ_idx; + u8 delta_max_vfe_equ_idx; + s32 offset_delta_min_uv; + s32 offset_delta_max_uv; +}; + +struct nv_pmu_volt_volt_policy_srms_boardobj_set { + struct nv_pmu_volt_volt_policy_splt_r_boardobj_set super; + u16 inter_switch_delayus; +}; + +/* sr - > single_rail */ +struct nv_pmu_volt_volt_policy_srss_boardobj_set { + struct nv_pmu_volt_volt_policy_splt_r_boardobj_set super; +}; + +union nv_pmu_volt_volt_policy_boardobj_set_union { + struct nv_pmu_boardobj board_obj; + struct nv_pmu_volt_volt_policy_boardobj_set super; + struct nv_pmu_volt_volt_policy_sr_boardobj_set single_rail; + struct nv_pmu_volt_volt_policy_splt_r_boardobj_set split_rail; + struct nv_pmu_volt_volt_policy_srms_boardobj_set + split_rail_m_s; + struct nv_pmu_volt_volt_policy_srss_boardobj_set + split_rail_s_s; +}; + +NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_policy); + +/* ----------- VOLT_RAIL's GRP_GET_STATUS defines and structures ----------- */ +struct nv_pmu_volt_volt_rail_boardobjgrp_get_status_header { + struct nv_pmu_boardobjgrp_e32 super; +}; + +struct nv_pmu_volt_volt_rail_boardobj_get_status { + struct nv_pmu_boardobj_query super; + u32 curr_volt_defaultu_v; + u32 rel_limitu_v; + u32 alt_rel_limitu_v; + u32 ov_limitu_v; + u32 max_limitu_v; + u32 vmin_limitu_v; + s32 volt_margin_limitu_v; + u32 rsvd; +}; + +union nv_pmu_volt_volt_rail_boardobj_get_status_union { + struct nv_pmu_boardobj_query board_obj; + struct nv_pmu_volt_volt_rail_boardobj_get_status super; +}; + +NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_rail); + +/* ---------- VOLT_DEVICE's GRP_GET_STATUS defines and structures ---------- */ +struct nv_pmu_volt_volt_device_boardobjgrp_get_status_header { + struct nv_pmu_boardobjgrp_e32 super; +}; + +struct nv_pmu_volt_volt_device_boardobj_get_status { + struct nv_pmu_boardobj_query super; +}; + +union nv_pmu_volt_volt_device_boardobj_get_status_union { + struct nv_pmu_boardobj_query board_obj; + struct nv_pmu_volt_volt_device_boardobj_get_status super; +}; + +NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_device); + +/* ---------- VOLT_POLICY's GRP_GET_STATUS defines and structures ---------- */ +struct nv_pmu_volt_volt_policy_boardobjgrp_get_status_header { + struct nv_pmu_boardobjgrp_e32 super; +}; + +struct nv_pmu_volt_volt_policy_boardobj_get_status { + struct nv_pmu_boardobj_query super; + u32 offset_volt_requ_v; + u32 offset_volt_curru_v; +}; + +struct nv_pmu_volt_volt_policy_sr_boardobj_get_status { + struct nv_pmu_volt_volt_policy_boardobj_get_status super; + u32 curr_voltu_v; +}; + +struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status { + struct nv_pmu_volt_volt_policy_boardobj_get_status super; + s32 delta_minu_v; + s32 delta_maxu_v; + s32 orig_delta_minu_v; + s32 orig_delta_maxu_v; + u32 curr_volt_masteru_v; + u32 curr_volt_slaveu_v; + bool b_violation; +}; + +/* srms -> split_rail_multi_step */ +struct nv_pmu_volt_volt_policy_srms_boardobj_get_status { + struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status super; +}; + +/* srss -> split_rail_single_step */ +struct nv_pmu_volt_volt_policy_srss_boardobj_get_status { + struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status super; +}; + +union nv_pmu_volt_volt_policy_boardobj_get_status_union { + struct nv_pmu_boardobj_query board_obj; + struct nv_pmu_volt_volt_policy_boardobj_get_status super; + struct nv_pmu_volt_volt_policy_sr_boardobj_get_status single_rail; + struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status split_rail; + struct nv_pmu_volt_volt_policy_srms_boardobj_get_status + split_rail_m_s; + struct nv_pmu_volt_volt_policy_srss_boardobj_get_status + split_rail_s_s; +}; + +NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_policy); + +struct nv_pmu_volt_policy_voltage_data { + u8 policy_idx; + struct ctrl_perf_volt_rail_list + rail_list; +}; + +struct nv_pmu_volt_rail_get_voltage { + u8 rail_idx; + u32 voltage_uv; +}; + +struct nv_pmu_volt_volt_rail_set_noise_unaware_vmin { + u8 num_rails; + struct ctrl_volt_volt_rail_list + rail_list; +}; + +#define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_SET (0x00000000) +#define NV_PMU_VOLT_CMD_ID_RPC (0x00000001) +#define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) +#define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_SET_NOISE_UNAWARE_VMIN (0x00000004) + +/*! +* PMU VOLT RPC calls. +*/ +#define NV_PMU_VOLT_RPC_ID_LOAD (0x00000000) +#define NV_PMU_VOLT_RPC_ID_VOLT_POLICY_SET_VOLTAGE (0x00000002) +#define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_GET_VOLTAGE (0x00000003) + +struct nv_pmu_volt_cmd_rpc { + u8 cmd_type; + u8 pad[3]; + struct nv_pmu_allocation request; +}; + +#define NV_PMU_VOLT_CMD_RPC_ALLOC_OFFSET \ + offsetof(struct nv_pmu_volt_cmd_rpc, request) + +struct nv_pmu_volt_cmd { + union { + u8 cmd_type; + struct nv_pmu_boardobj_cmd_grp grp_set; + struct nv_pmu_volt_cmd_rpc rpc; + struct nv_pmu_boardobj_cmd_grp grp_get_status; + }; +}; + +struct nv_pmu_volt_rpc { + u8 function; + bool b_supported; + bool b_success; + flcn_status flcn_status; + union { + struct nv_pmu_volt_policy_voltage_data volt_policy_voltage_data; + struct nv_pmu_volt_rail_get_voltage volt_rail_get_voltage; + struct nv_pmu_volt_volt_rail_set_noise_unaware_vmin + volt_rail_set_noise_unaware_vmin; + } params; +}; + +/*! +* VOLT MSG ID definitions +*/ +#define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_SET (0x00000000) +#define NV_PMU_VOLT_MSG_ID_RPC (0x00000001) +#define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) + +/*! +* Message carrying the result of the VOLT RPC execution. +*/ +struct nv_pmu_volt_msg_rpc { + u8 msg_type; + u8 rsvd[3]; + struct nv_pmu_allocation response; +}; + +#define NV_PMU_VOLT_MSG_RPC_ALLOC_OFFSET \ + offsetof(struct nv_pmu_volt_msg_rpc, response) + +struct nv_pmu_volt_msg { + union { + u8 msg_type; + struct nv_pmu_boardobj_msg_grp grp_set; + struct nv_pmu_volt_msg_rpc rpc; + struct nv_pmu_boardobj_msg_grp grp_get_status; + }; +}; + +#define NV_PMU_VF_INJECT_MAX_VOLT_RAILS (2) + +struct nv_pmu_volt_volt_rail_list { + u8 num_rails; + struct ctrl_perf_volt_rail_list_item + rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS]; +}; + +#endif /* _GPMUIFVOLT_H_*/ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h new file mode 100644 index 00000000..01cd2743 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _NVGPUGPMUCMDIF_H_ +#define _NVGPUGPMUCMDIF_H_ + +#include +#include "gpmuif_cmn.h" +#include "gpmuif_pmu.h" +#include "gpmuif_ap.h" +#include "gpmuif_pg.h" +#include "gpmuif_perfmon.h" +#include "gpmuif_acr.h" +#include "gpmuifboardobj.h" +#include "gpmuifclk.h" +#include "gpmuifperf.h" +#include "gpmuifperfvfe.h" +#include "gpmuifpmgr.h" +#include "gpmuifvolt.h" +#include "gpmuiftherm.h" +#include "gpmuifthermsensor.h" +#include "gpmuifseq.h" + +struct pmu_cmd { + struct pmu_hdr hdr; + union { + struct pmu_perfmon_cmd perfmon; + struct pmu_pg_cmd pg; + struct pmu_zbc_cmd zbc; + struct pmu_acr_cmd acr; + struct nv_pmu_boardobj_cmd boardobj; + struct nv_pmu_perf_cmd perf; + struct nv_pmu_volt_cmd volt; + struct nv_pmu_clk_cmd clk; + struct nv_pmu_pmgr_cmd pmgr; + struct nv_pmu_therm_cmd therm; + } cmd; +}; + +struct pmu_msg { + struct pmu_hdr hdr; + union { + struct pmu_init_msg init; + struct pmu_perfmon_msg perfmon; + struct pmu_pg_msg pg; + struct pmu_rc_msg rc; + struct pmu_acr_msg acr; + struct nv_pmu_boardobj_msg boardobj; + struct nv_pmu_perf_msg perf; + struct nv_pmu_volt_msg volt; + struct nv_pmu_clk_msg clk; + struct nv_pmu_pmgr_msg pmgr; + struct nv_pmu_therm_msg therm; + } msg; +}; + +#define PMU_UNIT_REWIND (0x00) +#define PMU_UNIT_PG (0x03) +#define PMU_UNIT_INIT (0x07) +#define PMU_UNIT_ACR (0x0A) +#define PMU_UNIT_PERFMON_T18X (0x11) +#define PMU_UNIT_PERFMON (0x12) +#define PMU_UNIT_PERF (0x13) +#define PMU_UNIT_RC (0x1F) +#define PMU_UNIT_FECS_MEM_OVERRIDE (0x1E) +#define PMU_UNIT_CLK (0x0D) +#define PMU_UNIT_THERM (0x14) +#define PMU_UNIT_PMGR (0x18) +#define PMU_UNIT_VOLT (0x0E) + +#define PMU_UNIT_END (0x23) + +#define PMU_UNIT_TEST_START (0xFE) +#define PMU_UNIT_END_SIM (0xFF) +#define PMU_UNIT_TEST_END (0xFF) + +#define PMU_UNIT_ID_IS_VALID(id) \ + (((id) < PMU_UNIT_END) || ((id) >= PMU_UNIT_TEST_START)) + +#endif /* _NVGPUGPMUCMDIF_H_*/ diff --git a/drivers/gpu/nvgpu/lpwr/rppg.c b/drivers/gpu/nvgpu/lpwr/rppg.c index cde57bf0..3cc12840 100644 --- a/drivers/gpu/nvgpu/lpwr/rppg.c +++ b/drivers/gpu/nvgpu/lpwr/rppg.c @@ -17,7 +17,7 @@ #include "gm206/bios_gm206.h" #include "pstate/pstate.h" #include "include/bios.h" -#include "pmuif/gpmuif_pg_rppg.h" +#include static void pmu_handle_rppg_init_msg(struct gk20a *g, struct pmu_msg *msg, void *param, u32 handle, u32 status) diff --git a/drivers/gpu/nvgpu/perf/perf.c b/drivers/gpu/nvgpu/perf/perf.c index 41ebb315..58efdd6c 100644 --- a/drivers/gpu/nvgpu/perf/perf.c +++ b/drivers/gpu/nvgpu/perf/perf.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -13,8 +13,6 @@ #include "gk20a/gk20a.h" #include "perf.h" -#include "pmuif/gpmuifperf.h" -#include "pmuif/gpmuifperfvfe.h" #include "gk20a/pmu_gk20a.h" #include "clk/clk_arb.h" diff --git a/drivers/gpu/nvgpu/perf/perf.h b/drivers/gpu/nvgpu/perf/perf.h index fe52bad9..ef15d240 100644 --- a/drivers/gpu/nvgpu/perf/perf.h +++ b/drivers/gpu/nvgpu/perf/perf.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -13,6 +13,7 @@ #ifndef _PERF_H_ #define _PERF_H_ +#include #include "vfe_equ.h" #include "vfe_var.h" #include "pstate/pstate.h" diff --git a/drivers/gpu/nvgpu/perf/vfe_equ.c b/drivers/gpu/nvgpu/perf/vfe_equ.c index 78a7c57c..3a5b9f45 100644 --- a/drivers/gpu/nvgpu/perf/vfe_equ.c +++ b/drivers/gpu/nvgpu/perf/vfe_equ.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,9 +17,6 @@ #include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e255.h" -#include "pmuif/gpmuifboardobj.h" -#include "pmuif/gpmuifperf.h" -#include "pmuif/gpmuifperfvfe.h" #include "gm206/bios_gm206.h" #include "ctrl/ctrlclk.h" #include "ctrl/ctrlvolt.h" diff --git a/drivers/gpu/nvgpu/perf/vfe_equ.h b/drivers/gpu/nvgpu/perf/vfe_equ.h index 8aaddccd..3ca7fb10 100644 --- a/drivers/gpu/nvgpu/perf/vfe_equ.h +++ b/drivers/gpu/nvgpu/perf/vfe_equ.h @@ -1,7 +1,7 @@ /* * general perf structures & definitions * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,8 +17,7 @@ #include "boardobj/boardobjgrp.h" #include "perf/vfe_var.h" -#include "pmuif/gpmuifperf.h" -#include "pmuif/gpmuifperfvfe.h" +#include u32 vfe_equ_sw_setup(struct gk20a *g); u32 vfe_equ_pmu_setup(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/perf/vfe_var.c b/drivers/gpu/nvgpu/perf/vfe_var.c index 35061a1f..d1e1d76c 100644 --- a/drivers/gpu/nvgpu/perf/vfe_var.c +++ b/drivers/gpu/nvgpu/perf/vfe_var.c @@ -17,9 +17,6 @@ #include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" -#include "pmuif/gpmuifboardobj.h" -#include "pmuif/gpmuifperf.h" -#include "pmuif/gpmuifperfvfe.h" #include "gm206/bios_gm206.h" #include "ctrl/ctrlclk.h" #include "ctrl/ctrlvolt.h" diff --git a/drivers/gpu/nvgpu/perf/vfe_var.h b/drivers/gpu/nvgpu/perf/vfe_var.h index fc43311b..41db6e22 100644 --- a/drivers/gpu/nvgpu/perf/vfe_var.h +++ b/drivers/gpu/nvgpu/perf/vfe_var.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,8 +15,7 @@ #define _VFE_VAR_H_ #include "boardobj/boardobjgrp.h" -#include "pmuif/gpmuifperf.h" -#include "pmuif/gpmuifperfvfe.h" +#include u32 vfe_var_sw_setup(struct gk20a *g); u32 vfe_var_pmu_setup(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c index ea070060..53241734 100644 --- a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c +++ b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,8 +16,7 @@ #include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" -#include "pmuif/gpmuifboardobj.h" -#include "pmuif/gpmuifpmgr.h" +#include #include "gm206/bios_gm206.h" #include "gk20a/pmu_gk20a.h" #include "pmgrpmu.h" diff --git a/drivers/gpu/nvgpu/pmgr/pwrdev.c b/drivers/gpu/nvgpu/pmgr/pwrdev.c index da034b31..e831126b 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrdev.c +++ b/drivers/gpu/nvgpu/pmgr/pwrdev.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,8 +16,6 @@ #include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" -#include "pmuif/gpmuifboardobj.h" -#include "pmuif/gpmuifpmgr.h" #include "gm206/bios_gm206.h" #include "gk20a/pmu_gk20a.h" diff --git a/drivers/gpu/nvgpu/pmgr/pwrdev.h b/drivers/gpu/nvgpu/pmgr/pwrdev.h index b8592a18..144113e2 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrdev.h +++ b/drivers/gpu/nvgpu/pmgr/pwrdev.h @@ -1,7 +1,7 @@ /* * general power device structures & definitions * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,7 +16,7 @@ #define _PWRDEV_H_ #include "boardobj/boardobj.h" -#include "pmuif/gpmuifpmgr.h" +#include #include "ctrl/ctrlpmgr.h" #define PWRDEV_I2CDEV_DEVICE_INDEX_NONE (0xFF) diff --git a/drivers/gpu/nvgpu/pmgr/pwrmonitor.c b/drivers/gpu/nvgpu/pmgr/pwrmonitor.c index f14bac07..ab2460eb 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrmonitor.c +++ b/drivers/gpu/nvgpu/pmgr/pwrmonitor.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,8 +16,6 @@ #include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" -#include "pmuif/gpmuifboardobj.h" -#include "pmuif/gpmuifpmgr.h" #include "gm206/bios_gm206.h" #include "gk20a/pmu_gk20a.h" diff --git a/drivers/gpu/nvgpu/pmgr/pwrmonitor.h b/drivers/gpu/nvgpu/pmgr/pwrmonitor.h index 7cd6b8c9..9ef5c821 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrmonitor.h +++ b/drivers/gpu/nvgpu/pmgr/pwrmonitor.h @@ -1,7 +1,7 @@ /* * general power channel structures & definitions * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,9 +15,9 @@ #ifndef _PWRMONITOR_H_ #define _PWRMONITOR_H_ +#include #include "boardobj/boardobjgrp.h" #include "boardobj/boardobj.h" -#include "pmuif/gpmuifpmgr.h" #include "ctrl/ctrlpmgr.h" struct pwr_channel { diff --git a/drivers/gpu/nvgpu/pmgr/pwrpolicy.c b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c index 2b0be8d8..d19f9a1c 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrpolicy.c +++ b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c @@ -16,8 +16,6 @@ #include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" -#include "pmuif/gpmuifboardobj.h" -#include "pmuif/gpmuifpmgr.h" #include "gm206/bios_gm206.h" #include "gk20a/pmu_gk20a.h" diff --git a/drivers/gpu/nvgpu/pmgr/pwrpolicy.h b/drivers/gpu/nvgpu/pmgr/pwrpolicy.h index 008282d3..e14369ea 100644 --- a/drivers/gpu/nvgpu/pmgr/pwrpolicy.h +++ b/drivers/gpu/nvgpu/pmgr/pwrpolicy.h @@ -1,7 +1,7 @@ /* * general power channel structures & definitions * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,9 +15,9 @@ #ifndef _PWRPOLICY_H_ #define _PWRPOLICY_H_ +#include #include "boardobj/boardobjgrp.h" #include "boardobj/boardobj.h" -#include "pmuif/gpmuifpmgr.h" #include "ctrl/ctrlpmgr.h" #define PWR_POLICY_EXT_POWER_STATE_ID_COUNT 0x4 diff --git a/drivers/gpu/nvgpu/pmuif/gpmuif_acr.h b/drivers/gpu/nvgpu/pmuif/gpmuif_acr.h deleted file mode 100644 index 440ffbaa..00000000 --- a/drivers/gpu/nvgpu/pmuif/gpmuif_acr.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ -#ifndef _GPMUIFACR_H_ -#define _GPMUIFACR_H_ - -/* ACR Commands/Message structures */ - -enum { - PMU_ACR_CMD_ID_INIT_WPR_REGION = 0x0, - PMU_ACR_CMD_ID_BOOTSTRAP_FALCON, - PMU_ACR_CMD_ID_RESERVED, - PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS, -}; - -/* - * Initializes the WPR region details - */ -struct pmu_acr_cmd_init_wpr_details { - u8 cmd_type; - u32 regionid; - u32 wproffset; - -}; - -/* - * falcon ID to bootstrap - */ -struct pmu_acr_cmd_bootstrap_falcon { - u8 cmd_type; - u32 flags; - u32 falconid; -}; - -/* - * falcon ID to bootstrap - */ -struct pmu_acr_cmd_bootstrap_multiple_falcons { - u8 cmd_type; - u32 flags; - u32 falconidmask; - u32 usevamask; - struct falc_u64 wprvirtualbase; -}; - -#define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_NO 1 -#define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0 - - -struct pmu_acr_cmd { - union { - u8 cmd_type; - struct pmu_acr_cmd_bootstrap_falcon bootstrap_falcon; - struct pmu_acr_cmd_init_wpr_details init_wpr; - struct pmu_acr_cmd_bootstrap_multiple_falcons boot_falcons; - }; -}; - -/* acr messages */ - -/* - * returns the WPR region init information - */ -#define PMU_ACR_MSG_ID_INIT_WPR_REGION 0 - -/* - * Returns the Bootstrapped falcon ID to RM - */ -#define PMU_ACR_MSG_ID_BOOTSTRAP_FALCON 1 - -/* - * Returns the WPR init status - */ -#define PMU_ACR_SUCCESS 0 -#define PMU_ACR_ERROR 1 - -/* - * PMU notifies about bootstrap status of falcon - */ -struct pmu_acr_msg_bootstrap_falcon { - u8 msg_type; - union { - u32 errorcode; - u32 falconid; - }; -}; - -struct pmu_acr_msg { - union { - u8 msg_type; - struct pmu_acr_msg_bootstrap_falcon acrmsg; - }; -}; - -#endif /* _GPMUIFACR_H_ */ diff --git a/drivers/gpu/nvgpu/pmuif/gpmuif_ap.h b/drivers/gpu/nvgpu/pmuif/gpmuif_ap.h deleted file mode 100644 index 7e2f546c..00000000 --- a/drivers/gpu/nvgpu/pmuif/gpmuif_ap.h +++ /dev/null @@ -1,247 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ -#ifndef _GPMUIFAP_H_ -#define _GPMUIFAP_H_ - -/* PMU Command/Message Interfaces for Adaptive Power */ -/* Macro to get Histogram index */ -#define PMU_AP_HISTOGRAM(idx) (idx) -#define PMU_AP_HISTOGRAM_CONT (4) - -/* Total number of histogram bins */ -#define PMU_AP_CFG_HISTOGRAM_BIN_N (16) - -/* Mapping between Idle counters and histograms */ -#define PMU_AP_IDLE_MASK_HIST_IDX_0 (2) -#define PMU_AP_IDLE_MASK_HIST_IDX_1 (3) -#define PMU_AP_IDLE_MASK_HIST_IDX_2 (5) -#define PMU_AP_IDLE_MASK_HIST_IDX_3 (6) - - -/* Mapping between AP_CTRLs and Histograms */ -#define PMU_AP_HISTOGRAM_IDX_GRAPHICS (PMU_AP_HISTOGRAM(1)) - -/* Mapping between AP_CTRLs and Idle counters */ -#define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1) - -/* Adaptive Power Controls (AP_CTRL) */ -enum { - PMU_AP_CTRL_ID_GRAPHICS = 0x0, - PMU_AP_CTRL_ID_MAX, -}; - -/* AP_CTRL Statistics */ -struct pmu_ap_ctrl_stat { - /* - * Represents whether AP is active or not - */ - u8 b_active; - - /* Idle filter represented by histogram bin index */ - u8 idle_filter_x; - u8 rsvd[2]; - - /* Total predicted power saving cycles. */ - s32 power_saving_h_cycles; - - /* Counts how many times AP gave us -ve power benefits. */ - u32 bad_decision_count; - - /* - * Number of times ap structure needs to skip AP iterations - * KICK_CTRL from kernel updates this parameter. - */ - u32 skip_count; - u8 bin[PMU_AP_CFG_HISTOGRAM_BIN_N]; -}; - -/* Parameters initialized by INITn APCTRL command */ -struct pmu_ap_ctrl_init_params { - /* Minimum idle filter value in Us */ - u32 min_idle_filter_us; - - /* - * Minimum Targeted Saving in Us. AP will update idle thresholds only - * if power saving achieved by updating idle thresholds is greater than - * Minimum targeted saving. - */ - u32 min_target_saving_us; - - /* Minimum targeted residency of power feature in Us */ - u32 power_break_even_us; - - /* - * Maximum number of allowed power feature cycles per sample. - * - * We are allowing at max "pgPerSampleMax" cycles in one iteration of AP - * AKA pgPerSampleMax in original algorithm. - */ - u32 cycles_per_sample_max; -}; - -/* AP Commands/Message structures */ - -/* - * Structure for Generic AP Commands - */ -struct pmu_ap_cmd_common { - u8 cmd_type; - u16 cmd_id; -}; - -/* - * Structure for INIT AP command - */ -struct pmu_ap_cmd_init { - u8 cmd_type; - u16 cmd_id; - u8 rsvd; - u32 pg_sampling_period_us; -}; - -/* - * Structure for Enable/Disable ApCtrl Commands - */ -struct pmu_ap_cmd_enable_ctrl { - u8 cmd_type; - u16 cmd_id; - - u8 ctrl_id; -}; - -struct pmu_ap_cmd_disable_ctrl { - u8 cmd_type; - u16 cmd_id; - - u8 ctrl_id; -}; - -/* - * Structure for INIT command - */ -struct pmu_ap_cmd_init_ctrl { - u8 cmd_type; - u16 cmd_id; - u8 ctrl_id; - struct pmu_ap_ctrl_init_params params; -}; - -struct pmu_ap_cmd_init_and_enable_ctrl { - u8 cmd_type; - u16 cmd_id; - u8 ctrl_id; - struct pmu_ap_ctrl_init_params params; -}; - -/* - * Structure for KICK_CTRL command - */ -struct pmu_ap_cmd_kick_ctrl { - u8 cmd_type; - u16 cmd_id; - u8 ctrl_id; - - u32 skip_count; -}; - -/* - * Structure for PARAM command - */ -struct pmu_ap_cmd_param { - u8 cmd_type; - u16 cmd_id; - u8 ctrl_id; - - u32 data; -}; - -/* - * Defines for AP commands - */ -enum { - PMU_AP_CMD_ID_INIT = 0x0, - PMU_AP_CMD_ID_INIT_AND_ENABLE_CTRL, - PMU_AP_CMD_ID_ENABLE_CTRL, - PMU_AP_CMD_ID_DISABLE_CTRL, - PMU_AP_CMD_ID_KICK_CTRL, -}; - -/* - * AP Command - */ -union pmu_ap_cmd { - u8 cmd_type; - struct pmu_ap_cmd_common cmn; - struct pmu_ap_cmd_init init; - struct pmu_ap_cmd_init_and_enable_ctrl init_and_enable_ctrl; - struct pmu_ap_cmd_enable_ctrl enable_ctrl; - struct pmu_ap_cmd_disable_ctrl disable_ctrl; - struct pmu_ap_cmd_kick_ctrl kick_ctrl; -}; - -/* - * Structure for generic AP Message - */ -struct pmu_ap_msg_common { - u8 msg_type; - u16 msg_id; -}; - -/* - * Structure for INIT_ACK Message - */ -struct pmu_ap_msg_init_ack { - u8 msg_type; - u16 msg_id; - u8 ctrl_id; - u32 stats_dmem_offset; -}; - -/* - * Defines for AP messages - */ -enum { - PMU_AP_MSG_ID_INIT_ACK = 0x0, -}; - -/* - * AP Message - */ -union pmu_ap_msg { - u8 msg_type; - struct pmu_ap_msg_common cmn; - struct pmu_ap_msg_init_ack init_ack; -}; - -/* - * Adaptive Power Controller - */ -struct ap_ctrl { - u32 stats_dmem_offset; - u32 disable_reason_mask; - struct pmu_ap_ctrl_stat stat_cache; - u8 b_ready; -}; - -/* - * Adaptive Power structure - * - * ap structure provides generic infrastructure to make any power feature - * adaptive. - */ -struct pmu_ap { - u32 supported_mask; - struct ap_ctrl ap_ctrl[PMU_AP_CTRL_ID_MAX]; -}; - -#endif /* _GPMUIFAP_H_*/ diff --git a/drivers/gpu/nvgpu/pmuif/gpmuif_cmn.h b/drivers/gpu/nvgpu/pmuif/gpmuif_cmn.h deleted file mode 100644 index 1d200129..00000000 --- a/drivers/gpu/nvgpu/pmuif/gpmuif_cmn.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ -#ifndef _GPMUIFCMN_H_ -#define _GPMUIFCMN_H_ - -/* - * Defines the logical queue IDs that must be used when submitting - * commands to the PMU - */ -/* write by sw, read by pmu, protected by sw mutex lock */ -#define PMU_COMMAND_QUEUE_HPQ 0 -/* write by sw, read by pmu, protected by sw mutex lock */ -#define PMU_COMMAND_QUEUE_LPQ 1 -/* read/write by sw/hw, protected by hw pmu mutex, id = 2 */ -#define PMU_COMMAND_QUEUE_BIOS 2 -/* read/write by sw/hw, protected by hw pmu mutex, id = 3 */ -#define PMU_COMMAND_QUEUE_SMI 3 -/* write by pmu, read by sw, accessed by interrupt handler, no lock */ -#define PMU_MESSAGE_QUEUE 4 -#define PMU_QUEUE_COUNT 5 - -#define PMU_IS_COMMAND_QUEUE(id) \ - ((id) < PMU_MESSAGE_QUEUE) - -#define PMU_IS_SW_COMMAND_QUEUE(id) \ - (((id) == PMU_COMMAND_QUEUE_HPQ) || \ - ((id) == PMU_COMMAND_QUEUE_LPQ)) - -#define PMU_IS_MESSAGE_QUEUE(id) \ - ((id) == PMU_MESSAGE_QUEUE) - -enum { - OFLAG_READ = 0, - OFLAG_WRITE -}; - -#define QUEUE_SET (true) -#define QUEUE_GET (false) - -#define QUEUE_ALIGNMENT (4) - -/* An enumeration containing all valid logical mutex identifiers */ -enum { - PMU_MUTEX_ID_RSVD1 = 0, - PMU_MUTEX_ID_GPUSER, - PMU_MUTEX_ID_QUEUE_BIOS, - PMU_MUTEX_ID_QUEUE_SMI, - PMU_MUTEX_ID_GPMUTEX, - PMU_MUTEX_ID_I2C, - PMU_MUTEX_ID_RMLOCK, - PMU_MUTEX_ID_MSGBOX, - PMU_MUTEX_ID_FIFO, - PMU_MUTEX_ID_PG, - PMU_MUTEX_ID_GR, - PMU_MUTEX_ID_CLK, - PMU_MUTEX_ID_RSVD6, - PMU_MUTEX_ID_RSVD7, - PMU_MUTEX_ID_RSVD8, - PMU_MUTEX_ID_RSVD9, - PMU_MUTEX_ID_INVALID -}; - -#define PMU_MUTEX_ID_IS_VALID(id) \ - ((id) < PMU_MUTEX_ID_INVALID) - -#define PMU_INVALID_MUTEX_OWNER_ID (0) - -/* - * The PMU's frame-buffer interface block has several slots/indices - * which can be bound to support DMA to various surfaces in memory - */ -enum { - PMU_DMAIDX_UCODE = 0, - PMU_DMAIDX_VIRT = 1, - PMU_DMAIDX_PHYS_VID = 2, - PMU_DMAIDX_PHYS_SYS_COH = 3, - PMU_DMAIDX_PHYS_SYS_NCOH = 4, - PMU_DMAIDX_RSVD = 5, - PMU_DMAIDX_PELPG = 6, - PMU_DMAIDX_END = 7 -}; - -/* - * Falcon PMU DMA's minimum size in bytes. - */ -#define PMU_DMA_MIN_READ_SIZE_BYTES 16 -#define PMU_DMA_MIN_WRITE_SIZE_BYTES 4 - -#define PMU_FB_COPY_RW_ALIGNMENT \ - ((PMU_DMA_MIN_READ_SIZE_BYTES > PMU_DMA_MIN_WRITE_SIZE_BYTES) ? \ - PMU_DMA_MIN_READ_SIZE_BYTES : PMU_DMA_MIN_WRITE_SIZE_BYTES) - -/* - * Macros to make aligned versions of RM_PMU_XXX structures. PMU needs aligned - * data structures to issue DMA read/write operations. - */ -#define NV_PMU_MAKE_ALIGNED_STRUCT(name, size) \ -union name##_aligned { \ - struct name data; \ - u8 pad[ALIGN_UP(sizeof(struct name), \ - (PMU_FB_COPY_RW_ALIGNMENT))]; \ -} - -#define NV_PMU_MAKE_ALIGNED_UNION(name, size) \ -union name##_aligned { \ - union name data; \ - u8 pad[ALIGN_UP(sizeof(union name), \ - (PMU_FB_COPY_RW_ALIGNMENT))]; \ -} - -#endif /* _GPMUIFCMN_H_*/ diff --git a/drivers/gpu/nvgpu/pmuif/gpmuif_perfmon.h b/drivers/gpu/nvgpu/pmuif/gpmuif_perfmon.h deleted file mode 100644 index 098d0305..00000000 --- a/drivers/gpu/nvgpu/pmuif/gpmuif_perfmon.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ -#ifndef _GPMUIFPERFMON_H_ -#define _GPMUIFPERFMON_H_ - -/*perfmon task defines*/ - -#define PMU_DOMAIN_GROUP_PSTATE 0 -#define PMU_DOMAIN_GROUP_GPC2CLK 1 -#define PMU_DOMAIN_GROUP_NUM 2 - -#define PMU_PERFMON_FLAG_ENABLE_INCREASE (0x00000001) -#define PMU_PERFMON_FLAG_ENABLE_DECREASE (0x00000002) -#define PMU_PERFMON_FLAG_CLEAR_PREV (0x00000004) - -enum pmu_perfmon_cmd_start_fields { - COUNTER_ALLOC -}; - -enum { - PMU_PERFMON_CMD_ID_START = 0, - PMU_PERFMON_CMD_ID_STOP = 1, - PMU_PERFMON_CMD_ID_INIT = 2 -}; - -struct pmu_perfmon_counter_v0 { - u8 index; - u8 flags; - u8 group_id; - u8 valid; - u16 upper_threshold; /* units of 0.01% */ - u16 lower_threshold; /* units of 0.01% */ -}; - -struct pmu_perfmon_counter_v2 { - u8 index; - u8 flags; - u8 group_id; - u8 valid; - u16 upper_threshold; /* units of 0.01% */ - u16 lower_threshold; /* units of 0.01% */ - u32 scale; -}; - -struct pmu_perfmon_cmd_start_v3 { - u8 cmd_type; - u8 group_id; - u8 state_id; - u8 flags; - struct pmu_allocation_v3 counter_alloc; -}; - -struct pmu_perfmon_cmd_start_v2 { - u8 cmd_type; - u8 group_id; - u8 state_id; - u8 flags; - struct pmu_allocation_v2 counter_alloc; -}; - -struct pmu_perfmon_cmd_start_v1 { - u8 cmd_type; - u8 group_id; - u8 state_id; - u8 flags; - struct pmu_allocation_v1 counter_alloc; -}; - -struct pmu_perfmon_cmd_start_v0 { - u8 cmd_type; - u8 group_id; - u8 state_id; - u8 flags; - struct pmu_allocation_v0 counter_alloc; -}; - -struct pmu_perfmon_cmd_stop { - u8 cmd_type; -}; - -struct pmu_perfmon_cmd_init_v3 { - u8 cmd_type; - u8 to_decrease_count; - u8 base_counter_id; - u32 sample_period_us; - struct pmu_allocation_v3 counter_alloc; - u8 num_counters; - u8 samples_in_moving_avg; - u16 sample_buffer; -}; - -struct pmu_perfmon_cmd_init_v2 { - u8 cmd_type; - u8 to_decrease_count; - u8 base_counter_id; - u32 sample_period_us; - struct pmu_allocation_v2 counter_alloc; - u8 num_counters; - u8 samples_in_moving_avg; - u16 sample_buffer; -}; - -struct pmu_perfmon_cmd_init_v1 { - u8 cmd_type; - u8 to_decrease_count; - u8 base_counter_id; - u32 sample_period_us; - struct pmu_allocation_v1 counter_alloc; - u8 num_counters; - u8 samples_in_moving_avg; - u16 sample_buffer; -}; - -struct pmu_perfmon_cmd_init_v0 { - u8 cmd_type; - u8 to_decrease_count; - u8 base_counter_id; - u32 sample_period_us; - struct pmu_allocation_v0 counter_alloc; - u8 num_counters; - u8 samples_in_moving_avg; - u16 sample_buffer; -}; - -struct pmu_perfmon_cmd { - union { - u8 cmd_type; - struct pmu_perfmon_cmd_start_v0 start_v0; - struct pmu_perfmon_cmd_start_v1 start_v1; - struct pmu_perfmon_cmd_start_v2 start_v2; - struct pmu_perfmon_cmd_start_v3 start_v3; - struct pmu_perfmon_cmd_stop stop; - struct pmu_perfmon_cmd_init_v0 init_v0; - struct pmu_perfmon_cmd_init_v1 init_v1; - struct pmu_perfmon_cmd_init_v2 init_v2; - struct pmu_perfmon_cmd_init_v3 init_v3; - }; -}; - -struct pmu_zbc_cmd { - u8 cmd_type; - u8 pad; - u16 entry_mask; -}; - -/* PERFMON MSG */ -enum { - PMU_PERFMON_MSG_ID_INCREASE_EVENT = 0, - PMU_PERFMON_MSG_ID_DECREASE_EVENT = 1, - PMU_PERFMON_MSG_ID_INIT_EVENT = 2, - PMU_PERFMON_MSG_ID_ACK = 3 -}; - -struct pmu_perfmon_msg_generic { - u8 msg_type; - u8 state_id; - u8 group_id; - u8 data; -}; - -struct pmu_perfmon_msg { - union { - u8 msg_type; - struct pmu_perfmon_msg_generic gen; - }; -}; - -#endif /* _GPMUIFPERFMON_H_ */ diff --git a/drivers/gpu/nvgpu/pmuif/gpmuif_pg.h b/drivers/gpu/nvgpu/pmuif/gpmuif_pg.h deleted file mode 100644 index 8c71e2a2..00000000 --- a/drivers/gpu/nvgpu/pmuif/gpmuif_pg.h +++ /dev/null @@ -1,311 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ -#ifndef _GPMUIFPG_H_ -#define _GPMUIFPG_H_ - -#include "gpmuif_ap.h" -#include "gpmuif_pg_rppg.h" - -/*PG defines*/ - -/* Identifier for each PG */ -#define PMU_PG_ELPG_ENGINE_ID_GRAPHICS (0x00000000) -#define PMU_PG_ELPG_ENGINE_ID_MS (0x00000004) -#define PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE (0x00000005) -#define PMU_PG_ELPG_ENGINE_MAX PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE - -/* PG message */ -enum { - PMU_PG_ELPG_MSG_INIT_ACK, - PMU_PG_ELPG_MSG_DISALLOW_ACK, - PMU_PG_ELPG_MSG_ALLOW_ACK, - PMU_PG_ELPG_MSG_FREEZE_ACK, - PMU_PG_ELPG_MSG_FREEZE_ABORT, - PMU_PG_ELPG_MSG_UNFREEZE_ACK, -}; - -struct pmu_pg_msg_elpg_msg { - u8 msg_type; - u8 engine_id; - u16 msg; -}; - -enum { - PMU_PG_STAT_MSG_RESP_DMEM_OFFSET = 0, -}; - -struct pmu_pg_msg_stat { - u8 msg_type; - u8 engine_id; - u16 sub_msg_id; - u32 data; -}; - -enum { - PMU_PG_MSG_ENG_BUF_LOADED, - PMU_PG_MSG_ENG_BUF_UNLOADED, - PMU_PG_MSG_ENG_BUF_FAILED, -}; - -struct pmu_pg_msg_eng_buf_stat { - u8 msg_type; - u8 engine_id; - u8 buf_idx; - u8 status; -}; - -struct pmu_pg_msg { - union { - u8 msg_type; - struct pmu_pg_msg_elpg_msg elpg_msg; - struct pmu_pg_msg_stat stat; - struct pmu_pg_msg_eng_buf_stat eng_buf_stat; - /* TBD: other pg messages */ - union pmu_ap_msg ap_msg; - struct nv_pmu_rppg_msg rppg_msg; - }; -}; - -/* PG commands */ -enum { - PMU_PG_ELPG_CMD_INIT, - PMU_PG_ELPG_CMD_DISALLOW, - PMU_PG_ELPG_CMD_ALLOW, - PMU_PG_ELPG_CMD_FREEZE, - PMU_PG_ELPG_CMD_UNFREEZE, -}; - -enum { - PMU_PG_CMD_ID_ELPG_CMD = 0, - PMU_PG_CMD_ID_ENG_BUF_LOAD, - PMU_PG_CMD_ID_ENG_BUF_UNLOAD, - PMU_PG_CMD_ID_PG_STAT, - PMU_PG_CMD_ID_PG_LOG_INIT, - PMU_PG_CMD_ID_PG_LOG_FLUSH, - PMU_PG_CMD_ID_PG_PARAM, - PMU_PG_CMD_ID_ELPG_INIT, - PMU_PG_CMD_ID_ELPG_POLL_CTXSAVE, - PMU_PG_CMD_ID_ELPG_ABORT_POLL, - PMU_PG_CMD_ID_ELPG_PWR_UP, - PMU_PG_CMD_ID_ELPG_DISALLOW, - PMU_PG_CMD_ID_ELPG_ALLOW, - PMU_PG_CMD_ID_AP, - RM_PMU_PG_CMD_ID_PSI, - RM_PMU_PG_CMD_ID_CG, - PMU_PG_CMD_ID_ZBC_TABLE_UPDATE, - PMU_PG_CMD_ID_PWR_RAIL_GATE_DISABLE = 0x20, - PMU_PG_CMD_ID_PWR_RAIL_GATE_ENABLE, - PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE, - PMU_PMU_PG_CMD_ID_RPPG = 0x24, -}; - -enum { - PMU_PG_STAT_CMD_ALLOC_DMEM = 0, -}; - -#define PMU_PG_PARAM_CMD_GR_INIT_PARAM 0x0 -#define PMU_PG_PARAM_CMD_MS_INIT_PARAM 0x01 -#define PMU_PG_PARAM_CMD_MCLK_CHANGE 0x04 -#define PMU_PG_PARAM_CMD_POST_INIT 0x06 - -#define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0) -#define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED (1 << 2) -#define PMU_PG_FEATURE_GR_RPPG_ENABLED (1 << 3) - -#define NVGPU_PMU_GR_FEATURE_MASK_RPPG (1 << 3) -#define NVGPU_PMU_GR_FEATURE_MASK_ALL \ - ( \ - NVGPU_PMU_GR_FEATURE_MASK_RPPG \ - ) - -#define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING (1 << 0) -#define NVGPU_PMU_MS_FEATURE_MASK_SW_ASR (1 << 1) -#define NVGPU_PMU_MS_FEATURE_MASK_RPPG (1 << 8) -#define NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING (1 << 5) - -#define NVGPU_PMU_MS_FEATURE_MASK_ALL \ - ( \ - NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING |\ - NVGPU_PMU_MS_FEATURE_MASK_SW_ASR |\ - NVGPU_PMU_MS_FEATURE_MASK_RPPG |\ - NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING \ - ) - - -struct pmu_pg_cmd_elpg_cmd { - u8 cmd_type; - u8 engine_id; - u16 cmd; -}; - -struct pmu_pg_cmd_eng_buf_load_v0 { - u8 cmd_type; - u8 engine_id; - u8 buf_idx; - u8 pad; - u16 buf_size; - u32 dma_base; - u8 dma_offset; - u8 dma_idx; -}; - -struct pmu_pg_cmd_eng_buf_load_v1 { - u8 cmd_type; - u8 engine_id; - u8 buf_idx; - u8 pad; - struct flcn_mem_desc { - struct falc_u64 dma_addr; - u16 dma_size; - u8 dma_idx; - } dma_desc; -}; - -struct pmu_pg_cmd_eng_buf_load_v2 { - u8 cmd_type; - u8 engine_id; - u8 buf_idx; - u8 pad; - struct flcn_mem_desc_v0 dma_desc; -}; - -struct pmu_pg_cmd_gr_init_param { - u8 cmd_type; - u16 sub_cmd_id; - u8 featuremask; -}; - -struct pmu_pg_cmd_ms_init_param { - u8 cmd_type; - u16 cmd_id; - u8 psi; - u8 idle_flipped_test_enabled; - u16 psiSettleTimeUs; - u8 rsvd[2]; - u32 support_mask; - u32 abort_timeout_us; -}; - -struct pmu_pg_cmd_mclk_change { - u8 cmd_type; - u16 cmd_id; - u8 rsvd; - u32 data; -}; - -#define PG_VOLT_RAIL_IDX_MAX 2 - -struct pmu_pg_volt_rail { - u8 volt_rail_idx; - u8 sleep_volt_dev_idx; - u8 sleep_vfe_idx; - u32 sleep_voltage_uv; - u32 therm_vid0_cache; - u32 therm_vid1_cache; -}; - -struct pmu_pg_cmd_post_init_param { - u8 cmd_type; - u16 cmd_id; - struct pmu_pg_volt_rail pg_volt_rail[PG_VOLT_RAIL_IDX_MAX]; -}; - -struct pmu_pg_cmd_stat { - u8 cmd_type; - u8 engine_id; - u16 sub_cmd_id; - u32 data; -}; - -struct pmu_pg_cmd { - union { - u8 cmd_type; - struct pmu_pg_cmd_elpg_cmd elpg_cmd; - struct pmu_pg_cmd_eng_buf_load_v0 eng_buf_load_v0; - struct pmu_pg_cmd_eng_buf_load_v1 eng_buf_load_v1; - struct pmu_pg_cmd_eng_buf_load_v2 eng_buf_load_v2; - struct pmu_pg_cmd_stat stat; - struct pmu_pg_cmd_gr_init_param gr_init_param; - struct pmu_pg_cmd_ms_init_param ms_init_param; - struct pmu_pg_cmd_mclk_change mclk_change; - struct pmu_pg_cmd_post_init_param post_init; - /* TBD: other pg commands */ - union pmu_ap_cmd ap_cmd; - struct nv_pmu_rppg_cmd rppg_cmd; - }; -}; - -/* Statistics structure for PG features */ -struct pmu_pg_stats_v2 { - u32 entry_count; - u32 exit_count; - u32 abort_count; - u32 detection_count; - u32 prevention_activate_count; - u32 prevention_deactivate_count; - u32 powered_up_time_us; - u32 entry_latency_us; - u32 exit_latency_us; - u32 resident_time_us; - u32 entry_latency_avg_us; - u32 exit_latency_avg_us; - u32 entry_latency_max_us; - u32 exit_latency_max_us; - u32 total_sleep_time_us; - u32 total_non_sleep_time_us; -}; - -struct pmu_pg_stats_v1 { - /* Number of time PMU successfully engaged sleep state */ - u32 entry_count; - /* Number of time PMU exit sleep state */ - u32 exit_count; - /* Number of time PMU aborted in entry sequence */ - u32 abort_count; - /* - * Time for which GPU was neither in Sleep state not - * executing sleep sequence. - */ - u32 poweredup_timeus; - /* Entry and exit latency of current sleep cycle */ - u32 entry_latency_us; - u32 exitlatencyus; - /* Resident time for current sleep cycle. */ - u32 resident_timeus; - /* Rolling average entry and exit latencies */ - u32 entrylatency_avgus; - u32 exitlatency_avgus; - /* Max entry and exit latencies */ - u32 entrylatency_maxus; - u32 exitlatency_maxus; - /* Total time spent in sleep and non-sleep state */ - u32 total_sleep_timeus; - u32 total_nonsleep_timeus; -}; - -struct pmu_pg_stats { - u64 pg_entry_start_timestamp; - u64 pg_ingating_start_timestamp; - u64 pg_exit_start_timestamp; - u64 pg_ungating_start_timestamp; - u32 pg_avg_entry_time_us; - u32 pg_ingating_cnt; - u32 pg_ingating_time_us; - u32 pg_avg_exit_time_us; - u32 pg_ungating_count; - u32 pg_ungating_time_us; - u32 pg_gating_cnt; - u32 pg_gating_deny_cnt; -}; - -#endif /* _GPMUIFPG_H_*/ diff --git a/drivers/gpu/nvgpu/pmuif/gpmuif_pg_rppg.h b/drivers/gpu/nvgpu/pmuif/gpmuif_pg_rppg.h deleted file mode 100644 index 7d5c8d41..00000000 --- a/drivers/gpu/nvgpu/pmuif/gpmuif_pg_rppg.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ -#ifndef _GPMUIFRPPG_H_ -#define _GPMUIFRPPG_H_ - -#define NV_PMU_RPPG_CTRL_ID_GR (0x0000) -#define NV_PMU_RPPG_CTRL_ID_MS (0x0001) -#define NV_PMU_RPPG_CTRL_ID_DI (0x0002) -#define NV_PMU_RPPG_CTRL_ID_MAX (0x0003) - -#define NV_PMU_RPPG_CTRL_MASK_ENABLE_ALL (BIT(NV_PMU_RPPG_CTRL_ID_GR) |\ - BIT(NV_PMU_RPPG_CTRL_ID_MS) |\ - BIT(NV_PMU_RPPG_CTRL_ID_DI)) - -#define NV_PMU_RPPG_CTRL_MASK_DISABLE_ALL 0 - -enum { - NV_PMU_RPPG_DOMAIN_ID_GFX = 0x0, - NV_PMU_RPPG_DOMAIN_ID_NON_GFX, -}; - -struct nv_pmu_rppg_ctrl_stats { - u32 entry_count; - u32 exit_count; -}; - -struct nv_pmu_rppg_cmd_common { - u8 cmd_type; - u8 cmd_id; -}; - -struct nv_pmu_rppg_cmd_init { - u8 cmd_type; - u8 cmd_id; -}; - -struct nv_pmu_rppg_cmd_init_ctrl { - u8 cmd_type; - u8 cmd_id; - u8 ctrl_id; - u8 domain_id; -}; - -struct nv_pmu_rppg_cmd_stats_reset { - u8 cmd_type; - u8 cmd_id; - u8 ctrl_id; -}; - -struct nv_pmu_rppg_cmd { - union { - u8 cmd_type; - struct nv_pmu_rppg_cmd_common cmn; - struct nv_pmu_rppg_cmd_init init; - struct nv_pmu_rppg_cmd_init_ctrl init_ctrl; - struct nv_pmu_rppg_cmd_stats_reset stats_reset; - }; -}; - -enum { - NV_PMU_RPPG_CMD_ID_INIT = 0x0, - NV_PMU_RPPG_CMD_ID_INIT_CTRL, - NV_PMU_RPPG_CMD_ID_STATS_RESET, -}; - - -struct nv_pmu_rppg_msg_common { - u8 msg_type; - u8 msg_id; -}; - -struct nv_pmu_rppg_msg_init_ctrl_ack { - u8 msg_type; - u8 msg_id; - u8 ctrl_id; - u32 stats_dmem_offset; -}; - -struct nv_pmu_rppg_msg { - union { - u8 msg_type; - struct nv_pmu_rppg_msg_common cmn; - struct nv_pmu_rppg_msg_init_ctrl_ack init_ctrl_ack; - }; -}; - -enum { - NV_PMU_RPPG_MSG_ID_INIT_CTRL_ACK = 0x0, -}; - -#endif diff --git a/drivers/gpu/nvgpu/pmuif/gpmuif_pmu.h b/drivers/gpu/nvgpu/pmuif/gpmuif_pmu.h deleted file mode 100644 index 6df92c1d..00000000 --- a/drivers/gpu/nvgpu/pmuif/gpmuif_pmu.h +++ /dev/null @@ -1,215 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ -#ifndef _GPMUIFPMU_H_ -#define _GPMUIFPMU_H_ - -#include -#include "gpmuif_cmn.h" - -/* Make sure size of this structure is a multiple of 4 bytes */ -struct pmu_cmdline_args_v0 { - u32 cpu_freq_hz; - u32 falc_trace_size; - u32 falc_trace_dma_base; - u32 falc_trace_dma_idx; - struct pmu_mem_v0 gc6_ctx; -}; - -struct pmu_cmdline_args_v1 { - u32 cpu_freq_hz; - u32 falc_trace_size; - u32 falc_trace_dma_base; - u32 falc_trace_dma_idx; - u8 secure_mode; - struct pmu_mem_v1 gc6_ctx; -}; - -struct pmu_cmdline_args_v2 { - u32 cpu_freq_hz; - u32 falc_trace_size; - u32 falc_trace_dma_base; - u32 falc_trace_dma_idx; - u8 secure_mode; - u8 raise_priv_sec; - struct pmu_mem_v1 gc6_ctx; -}; - -struct pmu_cmdline_args_v3 { - u32 reserved; - u32 cpu_freq_hz; - u32 falc_trace_size; - u32 falc_trace_dma_base; - u32 falc_trace_dma_idx; - u8 secure_mode; - u8 raise_priv_sec; - struct pmu_mem_v1 gc6_ctx; -}; - -struct pmu_cmdline_args_v4 { - u32 reserved; - u32 cpu_freq_hz; - u32 falc_trace_size; - struct falc_dma_addr dma_addr; - u32 falc_trace_dma_idx; - u8 secure_mode; - u8 raise_priv_sec; - struct pmu_mem_desc_v0 gc6_ctx; - u8 pad; -}; - -struct pmu_cmdline_args_v5 { - u32 cpu_freq_hz; - struct flcn_mem_desc_v0 trace_buf; - u8 secure_mode; - u8 raise_priv_sec; - struct flcn_mem_desc_v0 gc6_ctx; - struct flcn_mem_desc_v0 init_data_dma_info; - u32 dummy; -}; - -/* GPU ID */ -#define PMU_SHA1_GID_SIGNATURE 0xA7C66AD2 -#define PMU_SHA1_GID_SIGNATURE_SIZE 4 - -#define PMU_SHA1_GID_SIZE 16 - -struct pmu_sha1_gid { - bool valid; - u8 gid[PMU_SHA1_GID_SIZE]; -}; - -struct pmu_sha1_gid_data { - u8 signature[PMU_SHA1_GID_SIGNATURE_SIZE]; - u8 gid[PMU_SHA1_GID_SIZE]; -}; - -/* PMU INIT MSG */ -enum { - PMU_INIT_MSG_TYPE_PMU_INIT = 0, -}; - -struct pmu_init_msg_pmu_v0 { - u8 msg_type; - u8 pad; - - struct { - u16 size; - u16 offset; - u8 index; - u8 pad; - } queue_info[PMU_QUEUE_COUNT]; - - u16 sw_managed_area_offset; - u16 sw_managed_area_size; -}; - -struct pmu_init_msg_pmu_v1 { - u8 msg_type; - u8 pad; - u16 os_debug_entry_point; - - struct { - u16 size; - u16 offset; - u8 index; - u8 pad; - } queue_info[PMU_QUEUE_COUNT]; - - u16 sw_managed_area_offset; - u16 sw_managed_area_size; -}; -struct pmu_init_msg_pmu_v2 { - u8 msg_type; - u8 pad; - u16 os_debug_entry_point; - - struct { - u16 size; - u16 offset; - u8 index; - u8 pad; - } queue_info[PMU_QUEUE_COUNT]; - - u16 sw_managed_area_offset; - u16 sw_managed_area_size; - u8 dummy[18]; -}; - -#define PMU_QUEUE_COUNT_FOR_V4 5 -#define PMU_QUEUE_COUNT_FOR_V3 3 -#define PMU_QUEUE_HPQ_IDX_FOR_V3 0 -#define PMU_QUEUE_LPQ_IDX_FOR_V3 1 -#define PMU_QUEUE_MSG_IDX_FOR_V3 2 -struct pmu_init_msg_pmu_v3 { - u8 msg_type; - u8 queue_index[PMU_QUEUE_COUNT_FOR_V3]; - u16 queue_size[PMU_QUEUE_COUNT_FOR_V3]; - u16 queue_offset; - - u16 sw_managed_area_offset; - u16 sw_managed_area_size; - - u16 os_debug_entry_point; - - u8 dummy[18]; -}; - -struct pmu_init_msg_pmu_v4 { - u8 msg_type; - u8 queue_index[PMU_QUEUE_COUNT_FOR_V4]; - u16 queue_size[PMU_QUEUE_COUNT_FOR_V4]; - u16 queue_offset; - - u16 sw_managed_area_offset; - u16 sw_managed_area_size; - - u16 os_debug_entry_point; - - u8 dummy[18]; -}; - -union pmu_init_msg_pmu { - struct pmu_init_msg_pmu_v0 v0; - struct pmu_init_msg_pmu_v1 v1; - struct pmu_init_msg_pmu_v2 v2; - struct pmu_init_msg_pmu_v3 v3; - struct pmu_init_msg_pmu_v4 v4; -}; - -struct pmu_init_msg { - union { - u8 msg_type; - struct pmu_init_msg_pmu_v1 pmu_init_v1; - struct pmu_init_msg_pmu_v0 pmu_init_v0; - struct pmu_init_msg_pmu_v2 pmu_init_v2; - struct pmu_init_msg_pmu_v3 pmu_init_v3; - struct pmu_init_msg_pmu_v4 pmu_init_v4; - }; -}; - -/* robust channel (RC) messages */ -enum { - PMU_RC_MSG_TYPE_UNHANDLED_CMD = 0, -}; - -struct pmu_rc_msg_unhandled_cmd { - u8 msg_type; - u8 unit_id; -}; - -struct pmu_rc_msg { - u8 msg_type; - struct pmu_rc_msg_unhandled_cmd unhandled_cmd; -}; - -#endif /* _GPMUIFPMU_H_*/ diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifbios.h b/drivers/gpu/nvgpu/pmuif/gpmuifbios.h deleted file mode 100644 index 2581d3fa..00000000 --- a/drivers/gpu/nvgpu/pmuif/gpmuifbios.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ -#ifndef _GPMUIFBIOS_H_ -#define _GPMUIFBIOS_H_ - -struct nv_pmu_bios_vfield_register_segment_super { - u8 type; - u8 low_bit; - u8 high_bit; -}; - -struct nv_pmu_bios_vfield_register_segment_reg { - struct nv_pmu_bios_vfield_register_segment_super super; - u32 addr; -}; - -struct nv_pmu_bios_vfield_register_segment_index_reg { - struct nv_pmu_bios_vfield_register_segment_super super; - u32 addr; - u32 reg_index; - u32 index; -}; - -union nv_pmu_bios_vfield_register_segment { - struct nv_pmu_bios_vfield_register_segment_super super; - struct nv_pmu_bios_vfield_register_segment_reg reg; - struct nv_pmu_bios_vfield_register_segment_index_reg index_reg; -}; - - -#endif /* _GPMUIFBIOS_H_*/ diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifboardobj.h b/drivers/gpu/nvgpu/pmuif/gpmuifboardobj.h deleted file mode 100644 index 8da31469..00000000 --- a/drivers/gpu/nvgpu/pmuif/gpmuifboardobj.h +++ /dev/null @@ -1,195 +0,0 @@ -/* -* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms and conditions of the GNU General Public License, -* version 2, as published by the Free Software Foundation. -* -* This program is distributed in the hope it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -*/ -#ifndef _GPMUIFBOARDOBJ_H_ -#define _GPMUIFBOARDOBJ_H_ - -#include -#include "ctrl/ctrlboardobj.h" - -/* - * Base structure describing a BOARDOBJ for communication between Kernel and - * PMU. - */ -struct nv_pmu_boardobj { - u8 type; -}; - -/* - * Base structure describing a BOARDOBJ for Query interface between Kernel and - * PMU. - */ -struct nv_pmu_boardobj_query { - u8 type; -}; - -/* - * Virtual base structure describing a BOARDOBJGRP interface between Kernel and - * PMU. - */ -struct nv_pmu_boardobjgrp_super { - u8 type; - u8 class_id; - u8 obj_slots; - u8 rsvd; -}; - -struct nv_pmu_boardobjgrp { - struct nv_pmu_boardobjgrp_super super; - u32 obj_mask; -}; - -struct nv_pmu_boardobjgrp_e32 { - struct nv_pmu_boardobjgrp_super super; - struct ctrl_boardobjgrp_mask_e32 obj_mask; -}; - -struct nv_pmu_boardobjgrp_e255 { - struct nv_pmu_boardobjgrp_super super; - struct ctrl_boardobjgrp_mask_e255 obj_mask; -}; - -struct nv_pmu_boardobj_cmd_grp_payload { - struct pmu_allocation_v3 dmem_buf; - struct flcn_mem_desc_v0 fb; - u8 hdr_size; - u8 entry_size; -}; - -struct nv_pmu_boardobj_cmd_grp { - u8 cmd_type; - u8 pad[2]; - u8 class_id; - struct nv_pmu_boardobj_cmd_grp_payload grp; -}; - -#define NV_PMU_BOARDOBJ_GRP_ALLOC_OFFSET \ - (NV_OFFSETOF(NV_PMU_BOARDOBJ_CMD_GRP, grp)) - -struct nv_pmu_boardobj_cmd { - union { - u8 cmd_type; - struct nv_pmu_boardobj_cmd_grp grp; - struct nv_pmu_boardobj_cmd_grp grp_set; - struct nv_pmu_boardobj_cmd_grp grp_get_status; - }; -}; - -struct nv_pmu_boardobj_msg_grp { - u8 msg_type; - bool b_success; - flcn_status flcn_status; - u8 class_id; -}; - -struct nv_pmu_boardobj_msg { - union { - u8 msg_type; - struct nv_pmu_boardobj_msg_grp grp; - struct nv_pmu_boardobj_msg_grp grp_set; - struct nv_pmu_boardobj_msg_grp grp_get_status; - }; -}; - -/* -* Macro generating structures describing classes which implement -* NV_PMU_BOARDOBJGRP via the NV_PMU_BOARDBOBJ_CMD_GRP SET interface. -* -* @para _eng Name of implementing engine in which this structure is -* found. -* @param _class Class ID of Objects within Board Object Group. -* @param _slots Max number of elements this group can contain. -*/ -#define NV_PMU_BOARDOBJ_GRP_SET_MAKE(_eng, _class, _slots) \ - NV_PMU_MAKE_ALIGNED_STRUCT( \ - nv_pmu_##_eng##_##_class##_boardobjgrp_set_header, one_structure); \ - NV_PMU_MAKE_ALIGNED_UNION( \ - nv_pmu_##_eng##_##_class##_boardobj_set_union, one_union); \ - struct nv_pmu_##_eng##_##_class##_boardobj_grp_set { \ - union nv_pmu_##_eng##_##_class##_boardobjgrp_set_header_aligned hdr; \ - union nv_pmu_##_eng##_##_class##_boardobj_set_union_aligned objects[(_slots)];\ - } - -/* -* Macro generating structures describing classes which implement -* NV_PMU_BOARDOBJGRP_E32 via the NV_PMU_BOARDBOBJ_CMD_GRP SET interface. -* -* @para _eng Name of implementing engine in which this structure is -* found. -* @param _class Class ID of Objects within Board Object Group. -*/ -#define NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(_eng, _class) \ - NV_PMU_BOARDOBJ_GRP_SET_MAKE(_eng, _class, \ - CTRL_BOARDOBJGRP_E32_MAX_OBJECTS) - -/* -* Macro generating structures describing classes which implement -* NV_PMU_BOARDOBJGRP_E255 via the NV_PMU_BOARDBOBJ_CMD_GRP SET interface. -* -* @para _eng Name of implementing engine in which this structure is -* found. -* @param _class Class ID of Objects within Board Object Group. -*/ -#define NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(_eng, _class) \ - NV_PMU_BOARDOBJ_GRP_SET_MAKE(_eng, _class, \ - CTRL_BOARDOBJGRP_E255_MAX_OBJECTS) - -/* -* Macro generating structures for querying dynamic state for classes which -* implement NV_PMU_BOARDOBJGRP via the NV_PMU_BOARDOBJ_CMD_GRP GET_STATUS -* interface. -* -* @para _eng Name of implementing engine in which this structure is -* found. -* @param _class Class ID of Objects within Board Object Group. -* @param _slots Max number of elements this group can contain. -*/ -#define NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE(_eng, _class, _slots) \ - NV_PMU_MAKE_ALIGNED_STRUCT( \ - nv_pmu_##_eng##_##_class##_boardobjgrp_get_status_header, struct); \ - NV_PMU_MAKE_ALIGNED_UNION( \ - nv_pmu_##_eng##_##_class##_boardobj_get_status_union, union); \ - struct nv_pmu_##_eng##_##_class##_boardobj_grp_get_status { \ - union nv_pmu_##_eng##_##_class##_boardobjgrp_get_status_header_aligned \ - hdr; \ - union nv_pmu_##_eng##_##_class##_boardobj_get_status_union_aligned \ - objects[(_slots)]; \ - } - -/* -* Macro generating structures for querying dynamic state for classes which -* implement NV_PMU_BOARDOBJGRP_E32 via the NV_PMU_BOARDOBJ_CMD_GRP GET_STATUS -* interface. -* -* @para _eng Name of implementing engine in which this structure is -* found. -* @param _class Class ID of Objects within Board Object Group. -*/ -#define NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(_eng, _class) \ - NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE(_eng, _class, \ - CTRL_BOARDOBJGRP_E32_MAX_OBJECTS) - -/* -* Macro generating structures for querying dynamic state for classes which -* implement NV_PMU_BOARDOBJGRP_E255 via the NV_PMU_BOARDOBJ_CMD_GRP GET_STATUS -* interface. -* -* @para _eng Name of implementing engine in which this structure is -* found. -* @param _class Class ID of Objects within Board Object Group. -*/ -#define NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E255(_eng, _class) \ - NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE(_eng, _class, \ - CTRL_BOARDOBJGRP_E255_MAX_OBJECTS) - - -#endif /* _GPMUIFBOARDOBJ_H_ */ diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifclk.h b/drivers/gpu/nvgpu/pmuif/gpmuifclk.h deleted file mode 100644 index 5747b0df..00000000 --- a/drivers/gpu/nvgpu/pmuif/gpmuifclk.h +++ /dev/null @@ -1,455 +0,0 @@ -/* -* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms and conditions of the GNU General Public License, -* version 2, as published by the Free Software Foundation. -* -* This program is distributed in the hope it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -*/ - -#ifndef _GPMUIFCLK_H_ -#define _GPMUIFCLK_H_ - -#include "ctrl/ctrlboardobj.h" -#include "ctrl/ctrlvolt.h" -#include "ctrl/ctrlperf.h" -#include "ctrl/ctrlclk.h" -#include "pmuif/gpmuifboardobj.h" -#include "pmuif/gpmuifvolt.h" -#include - -enum nv_pmu_clk_clkwhich { - clkwhich_mclk = 5, - clkwhich_dispclk = 7, - clkwhich_gpc2clk = 17, - clkwhich_xbar2clk = 19, - clkwhich_sys2clk = 20, - clkwhich_hub2clk = 21, - clkwhich_pwrclk = 24, - clkwhich_nvdclk = 25, - clkwhich_pciegenclk = 31, -}; - -/* - * Enumeration of BOARDOBJGRP class IDs within OBJCLK. Used as "classId" - * argument for communications between Kernel and PMU via the various generic - * BOARDOBJGRP interfaces. - */ -#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_DOMAIN 0x00 -#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_PROG 0x01 -#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_VIN_DEVICE 0x02 -#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_FLL_DEVICE 0x03 -#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_VF_POINT 0x04 -#define NV_PMU_CLK_BOARDOBJGRP_CLASS_ID_CLK_FREQ_CONTROLLER 0x05 - -/*! -* CLK_DOMAIN BOARDOBJGRP Header structure. Describes global state about the -* CLK_DOMAIN feature. -*/ -struct nv_pmu_clk_clk_domain_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e32 super; - u32 vbios_domains; - struct ctrl_boardobjgrp_mask_e32 master_domains_mask; - u16 cntr_sampling_periodms; - bool b_override_o_v_o_c; - bool b_debug_mode; - bool b_enforce_vf_monotonicity; - bool b_enforce_vf_smoothening; - u8 volt_rails_max; - struct ctrl_clk_clk_delta deltas; -}; - -struct nv_pmu_clk_clk_domain_boardobj_set { - struct nv_pmu_boardobj super; - enum nv_pmu_clk_clkwhich domain; - u32 api_domain; - u8 perf_domain_grp_idx; -}; - -struct nv_pmu_clk_clk_domain_3x_boardobj_set { - struct nv_pmu_clk_clk_domain_boardobj_set super; - bool b_noise_aware_capable; -}; - -struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set { - struct nv_pmu_clk_clk_domain_3x_boardobj_set super; - u16 freq_mhz; -}; - -struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set { - struct nv_pmu_clk_clk_domain_3x_boardobj_set super; - u8 clk_prog_idx_first; - u8 clk_prog_idx_last; - u8 noise_unaware_ordering_index; - u8 noise_aware_ordering_index; - bool b_force_noise_unaware_ordering; - int factory_offset_khz; - short freq_delta_min_mhz; - short freq_delta_max_mhz; - struct ctrl_clk_clk_delta deltas; -}; - -struct nv_pmu_clk_clk_domain_3x_master_boardobj_set { - struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; - u32 slave_idxs_mask; -}; - -struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set { - struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; - u8 master_idx; -}; - -union nv_pmu_clk_clk_domain_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_clk_clk_domain_boardobj_set super; - struct nv_pmu_clk_clk_domain_3x_boardobj_set v3x; - struct nv_pmu_clk_clk_domain_3x_fixed_boardobj_set v3x_fixed; - struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set v3x_prog; - struct nv_pmu_clk_clk_domain_3x_master_boardobj_set v3x_master; - struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set v3x_slave; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_domain); - -struct nv_pmu_clk_clk_prog_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e255 super; - u8 slave_entry_count; - u8 vf_entry_count; -}; - -struct nv_pmu_clk_clk_prog_boardobj_set { - struct nv_pmu_boardobj super; -}; - -struct nv_pmu_clk_clk_prog_1x_boardobj_set { - struct nv_pmu_clk_clk_prog_boardobj_set super; - u8 source; - u16 freq_max_mhz; - union ctrl_clk_clk_prog_1x_source_data source_data; -}; - -struct nv_pmu_clk_clk_prog_1x_master_boardobj_set { - struct nv_pmu_clk_clk_prog_1x_boardobj_set super; - bool b_o_c_o_v_enabled; - struct ctrl_clk_clk_prog_1x_master_vf_entry vf_entries[ - CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES]; - union ctrl_clk_clk_prog_1x_master_source_data source_data; - struct ctrl_clk_clk_delta deltas; -}; - -struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set { - struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super; - struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry slave_entries[ - CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES]; -}; - -struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set { - struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super; - struct ctrl_clk_clk_prog_1x_master_table_slave_entry - slave_entries[CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES]; -}; - -union nv_pmu_clk_clk_prog_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_clk_clk_prog_boardobj_set super; - struct nv_pmu_clk_clk_prog_1x_boardobj_set v1x; - struct nv_pmu_clk_clk_prog_1x_master_boardobj_set v1x_master; - struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set v1x_master_ratio; - struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set v1x_master_table; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(clk, clk_prog); - -struct nv_pmu_clk_lut_device_desc { - u8 vselect_mode; - u16 hysteresis_threshold; -}; - -struct nv_pmu_clk_regime_desc { - u8 regime_id; - u16 fixed_freq_regime_limit_mhz; -}; - -struct nv_pmu_clk_clk_fll_device_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e32 super; - struct ctrl_boardobjgrp_mask_e32 lut_prog_master_mask; - u32 lut_step_size_uv; - u32 lut_min_voltage_uv; - u8 lut_num_entries; - u16 max_min_freq_mhz; -}; - -struct nv_pmu_clk_clk_fll_device_boardobj_set { - struct nv_pmu_boardobj super; - u8 id; - u8 mdiv; - u8 vin_idx_logic; - u8 vin_idx_sram; - u8 rail_idx_for_lut; - u16 input_freq_mhz; - u32 clk_domain; - struct nv_pmu_clk_lut_device_desc lut_device; - struct nv_pmu_clk_regime_desc regime_desc; - u8 min_freq_vfe_idx; - u8 freq_ctrl_idx; - struct ctrl_boardobjgrp_mask_e32 lut_prog_broadcast_slave_mask; -}; - -union nv_pmu_clk_clk_fll_device_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_clk_clk_fll_device_boardobj_set super; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_fll_device); - -struct nv_pmu_clk_clk_vin_device_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e32 super; - bool b_vin_is_disable_allowed; -}; - -struct nv_pmu_clk_clk_vin_device_boardobj_set { - struct nv_pmu_boardobj super; - u8 id; - u8 volt_domain; - u32 slope; - u32 intercept; - u32 flls_shared_mask; -}; - -union nv_pmu_clk_clk_vin_device_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_clk_clk_vin_device_boardobj_set super; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_vin_device); - -struct nv_pmu_clk_clk_vf_point_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e255 super; -}; - -struct nv_pmu_clk_clk_vf_point_boardobj_set { - struct nv_pmu_boardobj super; - u8 vfe_equ_idx; - u8 volt_rail_idx; -}; - -struct nv_pmu_clk_clk_vf_point_freq_boardobj_set { - struct nv_pmu_clk_clk_vf_point_boardobj_set super; - u16 freq_mhz; - int volt_delta_uv; -}; - -struct nv_pmu_clk_clk_vf_point_volt_boardobj_set { - struct nv_pmu_clk_clk_vf_point_boardobj_set super; - u32 source_voltage_uv; - int freq_delta_khz; -}; - -union nv_pmu_clk_clk_vf_point_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_clk_clk_vf_point_boardobj_set super; - struct nv_pmu_clk_clk_vf_point_freq_boardobj_set freq; - struct nv_pmu_clk_clk_vf_point_volt_boardobj_set volt; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(clk, clk_vf_point); - -struct nv_pmu_clk_clk_vf_point_boardobjgrp_get_status_header { - struct nv_pmu_boardobjgrp_e255 super; -}; - -struct nv_pmu_clk_clk_vf_point_boardobj_get_status { - struct nv_pmu_boardobj super; - struct ctrl_clk_vf_pair pair; -}; - -struct nv_pmu_clk_clk_vf_point_volt_boardobj_get_status { - struct nv_pmu_clk_clk_vf_point_boardobj_get_status super; - u16 vf_gain_value; -}; - -union nv_pmu_clk_clk_vf_point_boardobj_get_status_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_clk_clk_vf_point_boardobj_get_status super; - struct nv_pmu_clk_clk_vf_point_volt_boardobj_get_status volt; -}; - -NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E255(clk, clk_vf_point); - -#define NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS (12) - -struct nv_pmu_clk_clk_domain_list { - u8 num_domains; - struct ctrl_clk_clk_domain_list_item clk_domains[ - NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS]; -}; - -struct nv_pmu_clk_vf_change_inject { - u8 flags; - struct nv_pmu_clk_clk_domain_list clk_list; - struct nv_pmu_volt_volt_rail_list volt_list; -}; - -#define NV_NV_PMU_CLK_LOAD_FEATURE_VIN (0x00000002) -#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_VIN_HW_CAL_PROGRAM_YES (0x00000001) - -struct nv_pmu_clk_load_payload_freq_controllers { - struct ctrl_boardobjgrp_mask_e32 load_mask; -}; - -struct nv_pmu_clk_load { - u8 feature; - u32 action_mask; - union { - struct nv_pmu_clk_load_payload_freq_controllers freq_controllers; - } payload; -}; -/* CLK_FREQ_CONTROLLER */ -#define NV_NV_PMU_CLK_LOAD_FEATURE_FREQ_CONTROLLER (0x00000003) - -#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_NO (0x00000000) -#define NV_NV_PMU_CLK_LOAD_ACTION_MASK_FREQ_CONTROLLER_CALLBACK_YES (0x00000002) - -struct nv_pmu_clk_clk_freq_controller_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e32 super; - u32 sampling_period_ms; - u8 volt_policy_idx; -}; - -struct nv_pmu_clk_clk_freq_controller_boardobj_set { - struct nv_pmu_boardobj super; - u8 controller_id; - u8 parts_freq_mode; - bool bdisable; - u32 clk_domain; - s16 freq_cap_noise_unaware_vmin_above; - s16 freq_cap_noise_unaware_vmin_below; - s16 freq_hyst_pos_mhz; - s16 freq_hyst_neg_mhz; -}; - -struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set { - struct nv_pmu_clk_clk_freq_controller_boardobj_set super; - s32 prop_gain; - s32 integ_gain; - s32 integ_decay; - s32 volt_delta_min; - s32 volt_delta_max; - u8 slowdown_pct_min; - bool bpoison; -}; - -union nv_pmu_clk_clk_freq_controller_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_clk_clk_freq_controller_boardobj_set super; - struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set pi; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_freq_controller); - -/* CLK CMD ID definitions. */ -#define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_SET (0x00000000) -#define NV_PMU_CLK_CMD_ID_RPC (0x00000001) -#define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) - -#define NV_PMU_CLK_RPC_ID_LOAD (0x00000002) -#define NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT (0x00000001) - -struct nv_pmu_clk_cmd_rpc { - u8 cmd_type; - u8 pad[3]; - struct nv_pmu_allocation request; -}; - -#define NV_PMU_CLK_CMD_RPC_ALLOC_OFFSET \ - (offsetof(struct nv_pmu_clk_cmd_rpc, request)) - -struct nv_pmu_clk_cmd { - union { - u8 cmd_type; - struct nv_pmu_boardobj_cmd_grp grp_set; - struct nv_pmu_clk_cmd_rpc rpc; - struct nv_pmu_boardobj_cmd_grp grp_get_status; - }; -}; - -struct nv_pmu_clk_rpc { - u8 function; - bool b_supported; - bool b_success; - flcn_status flcn_status; - union { - struct nv_pmu_clk_vf_change_inject clk_vf_change_inject; - struct nv_pmu_clk_load clk_load; - } params; -}; - -/* CLK MSG ID definitions */ -#define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_SET (0x00000000) -#define NV_PMU_CLK_MSG_ID_RPC (0x00000001) -#define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) - -struct nv_pmu_clk_msg_rpc { - u8 msg_type; - u8 rsvd[3]; - struct nv_pmu_allocation response; -}; - -#define NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET \ - offsetof(struct nv_pmu_clk_msg_rpc, response) - -struct nv_pmu_clk_msg { - union { - u8 msg_type; - struct nv_pmu_boardobj_msg_grp grp_set; - struct nv_pmu_clk_msg_rpc rpc; - struct nv_pmu_boardobj_msg_grp grp_get_status; - }; -}; - -struct nv_pmu_clk_clk_vin_device_boardobjgrp_get_status_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -struct nv_pmu_clk_clk_vin_device_boardobj_get_status { - struct nv_pmu_boardobj_query super; - u32 actual_voltage_uv; - u32 corrected_voltage_uv; - u8 sampled_code; - u8 override_code; -}; - -union nv_pmu_clk_clk_vin_device_boardobj_get_status_union { - struct nv_pmu_boardobj_query board_obj; - struct nv_pmu_clk_clk_vin_device_boardobj_get_status super; -}; - -NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(clk, clk_vin_device); - -struct nv_pmu_clk_lut_vf_entry { - u32 entry; -}; - -struct nv_pmu_clk_clk_fll_device_boardobjgrp_get_status_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -struct nv_pmu_clk_clk_fll_device_boardobj_get_status { - struct nv_pmu_boardobj_query super; - u8 current_regime_id; - u16 min_freq_mhz; - struct nv_pmu_clk_lut_vf_entry lut_vf_curve[NV_UNSIGNED_ROUNDED_DIV(CTRL_CLK_LUT_NUM_ENTRIES, 2)]; -}; - -union nv_pmu_clk_clk_fll_device_boardobj_get_status_union { - struct nv_pmu_boardobj_query board_obj; - struct nv_pmu_clk_clk_fll_device_boardobj_get_status super; -}; - -NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(clk, clk_fll_device); - -#endif /*_GPMUIFCLK_H_*/ diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifperf.h b/drivers/gpu/nvgpu/pmuif/gpmuifperf.h deleted file mode 100644 index 181a65f5..00000000 --- a/drivers/gpu/nvgpu/pmuif/gpmuifperf.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ -#ifndef _GPMUIFPERF_H_ -#define _GPMUIFPERF_H_ - -#include "gpmuifvolt.h" -#include "gpmuifperfvfe.h" - -/* -* Enumeration of BOARDOBJGRP class IDs within OBJPERF. Used as "classId" -* argument for communications between Kernel and PMU via the various generic -* BOARDOBJGRP interfaces. -*/ -#define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_VAR 0x00 -#define NV_PMU_PERF_BOARDOBJGRP_CLASS_ID_VFE_EQU 0x01 - -#define NV_PMU_PERF_CMD_ID_RPC (0x00000002) -#define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_SET (0x00000003) -#define NV_PMU_PERF_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000004) - -struct nv_pmu_perf_cmd_set_object { - u8 cmd_type; - u8 pad[2]; - u8 object_type; - struct nv_pmu_allocation object; -}; - -#define NV_PMU_PERF_SET_OBJECT_ALLOC_OFFSET \ - (offsetof(struct nv_pmu_perf_cmd_set_object, object)) - -/* RPC IDs */ -#define NV_PMU_PERF_RPC_ID_VFE_LOAD (0x00000001) - -/*! -* Command requesting execution of the perf RPC. -*/ -struct nv_pmu_perf_cmd_rpc { - u8 cmd_type; - u8 pad[3]; - struct nv_pmu_allocation request; -}; - -#define NV_PMU_PERF_CMD_RPC_ALLOC_OFFSET \ - offsetof(struct nv_pmu_perf_cmd_rpc, request) - -/*! -* Simply a union of all specific PERF commands. Forms the general packet -* exchanged between the Kernel and PMU when sending and receiving PERF commands -* (respectively). -*/ -struct nv_pmu_perf_cmd { - union { - u8 cmd_type; - struct nv_pmu_perf_cmd_set_object set_object; - struct nv_pmu_boardobj_cmd_grp grp_set; - struct nv_pmu_boardobj_cmd_grp grp_get_status; - }; -}; - -/*! -* Defines the data structure used to invoke PMU perf RPCs. Same structure is -* used to return the result of the RPC execution. -*/ -struct nv_pmu_perf_rpc { - u8 function; - bool b_supported; - bool b_success; - flcn_status flcn_status; - union { - struct nv_pmu_perf_rpc_vfe_equ_eval vfe_equ_eval; - struct nv_pmu_perf_rpc_vfe_load vfe_load; - } params; -}; - - -/* PERF Message-type Definitions */ -#define NV_PMU_PERF_MSG_ID_RPC (0x00000003) -#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_SET (0x00000004) -#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000006) -#define NV_PMU_PERF_MSG_ID_VFE_CALLBACK (0x00000005) - -/*! -* Message carrying the result of the perf RPC execution. -*/ -struct nv_pmu_perf_msg_rpc { - u8 msg_type; - u8 rsvd[3]; - struct nv_pmu_allocation response; -}; - -#define NV_PMU_PERF_MSG_RPC_ALLOC_OFFSET \ - (offsetof(struct nv_pmu_perf_msg_rpc, response)) - -/*! -* Simply a union of all specific PERF messages. Forms the general packet -* exchanged between the Kernel and PMU when sending and receiving PERF messages -* (respectively). -*/ -struct nv_pmu_perf_msg { - union { - u8 msg_type; - struct nv_pmu_perf_msg_rpc rpc; - struct nv_pmu_boardobj_msg_grp grp_set; - }; -}; - -#endif /* _GPMUIFPERF_H_*/ diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifperfvfe.h b/drivers/gpu/nvgpu/pmuif/gpmuifperfvfe.h deleted file mode 100644 index 6bad6445..00000000 --- a/drivers/gpu/nvgpu/pmuif/gpmuifperfvfe.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ -#ifndef _GPMUIFPERFVFE_H_ -#define _GPMUIFPERFVFE_H_ - -#include "gpmuifbios.h" -#include "gpmuifboardobj.h" - -#define CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT 0x03 -#define NV_PMU_PERF_RPC_VFE_EQU_EVAL_VAR_COUNT_MAX 2 -#define NV_PMU_PERF_RPC_VFE_EQU_MONITOR_COUNT_MAX 16 -#define NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX 1 - -struct nv_pmu_perf_vfe_var_value { - u8 var_type; - u8 reserved[3]; - u32 var_value; -}; - -union nv_pmu_perf_vfe_equ_result { - u32 freq_m_hz; - u32 voltu_v; - u32 vf_gain; - int volt_deltau_v; -}; - -struct nv_pmu_perf_rpc_vfe_equ_eval { - u8 equ_idx; - u8 var_count; - u8 output_type; - struct nv_pmu_perf_vfe_var_value var_values[ - NV_PMU_PERF_RPC_VFE_EQU_EVAL_VAR_COUNT_MAX]; - union nv_pmu_perf_vfe_equ_result result; -}; - -struct nv_pmu_perf_rpc_vfe_load { - bool b_load; -}; - -struct nv_pmu_perf_vfe_var_boardobjgrp_get_status_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -struct nv_pmu_perf_vfe_var_get_status_super { - struct nv_pmu_boardobj_query board_obj; -}; - -struct nv_pmu_perf_vfe_var_single_sensed_fuse_get_status { - struct nv_pmu_perf_vfe_var_get_status_super super; - u32 fuse_value_integer; - u32 fuse_value_hw_integer; - u8 fuse_version; - bool b_version_check_failed; -}; - -union nv_pmu_perf_vfe_var_boardobj_get_status_union { - struct nv_pmu_boardobj_query board_obj; - struct nv_pmu_perf_vfe_var_get_status_super super; - struct nv_pmu_perf_vfe_var_single_sensed_fuse_get_status fuse_status; -}; - -NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(perf, vfe_var); - -struct nv_pmu_vfe_var { - struct nv_pmu_boardobj super; - u32 out_range_min; - u32 out_range_max; -}; - -struct nv_pmu_vfe_var_derived { - struct nv_pmu_vfe_var super; -}; - -struct nv_pmu_vfe_var_derived_product { - struct nv_pmu_vfe_var_derived super; - u8 var_idx0; - u8 var_idx1; -}; - -struct nv_pmu_vfe_var_derived_sum { - struct nv_pmu_vfe_var_derived super; - u8 var_idx0; - u8 var_idx1; -}; - -struct nv_pmu_vfe_var_single { - struct nv_pmu_vfe_var super; - u8 override_type; - u32 override_value; -}; - -struct nv_pmu_vfe_var_single_frequency { - struct nv_pmu_vfe_var_single super; -}; - -struct nv_pmu_vfe_var_single_sensed { - struct nv_pmu_vfe_var_single super; -}; - -struct nv_pmu_vfe_var_single_sensed_fuse_info { - u8 segment_count; - union nv_pmu_bios_vfield_register_segment segments[ - NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX]; -}; - -struct nv_pmu_vfe_var_single_sensed_fuse_vfield_info { - struct nv_pmu_vfe_var_single_sensed_fuse_info fuse; - u32 fuse_val_default; - int hw_correction_scale; - int hw_correction_offset; - u8 v_field_id; -}; - -struct nv_pmu_vfe_var_single_sensed_fuse_ver_vfield_info { - struct nv_pmu_vfe_var_single_sensed_fuse_info fuse; - u8 ver_expected; - bool b_ver_check; - bool b_use_default_on_ver_check_fail; - u8 v_field_id_ver; -}; - -struct nv_pmu_vfe_var_single_sensed_fuse_override_info { - u32 fuse_val_override; - bool b_fuse_regkey_override; -}; - -struct nv_pmu_vfe_var_single_sensed_fuse { - struct nv_pmu_vfe_var_single_sensed super; - struct nv_pmu_vfe_var_single_sensed_fuse_override_info override_info; - struct nv_pmu_vfe_var_single_sensed_fuse_vfield_info vfield_info; - struct nv_pmu_vfe_var_single_sensed_fuse_ver_vfield_info vfield_ver_info; -}; - -struct nv_pmu_vfe_var_single_sensed_temp { - struct nv_pmu_vfe_var_single_sensed super; - u8 therm_channel_index; - int temp_hysteresis_positive; - int temp_hysteresis_negative; - int temp_default; -}; - -struct nv_pmu_vfe_var_single_voltage { - struct nv_pmu_vfe_var_single super; -}; - -struct nv_pmu_perf_vfe_var_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e32 super; - u8 polling_periodms; -}; - -union nv_pmu_perf_vfe_var_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_vfe_var var; - struct nv_pmu_vfe_var_derived var_derived; - struct nv_pmu_vfe_var_derived_product var_derived_product; - struct nv_pmu_vfe_var_derived_sum var_derived_sum; - struct nv_pmu_vfe_var_single var_single; - struct nv_pmu_vfe_var_single_frequency var_single_frequiency; - struct nv_pmu_vfe_var_single_sensed var_single_sensed; - struct nv_pmu_vfe_var_single_sensed_fuse var_single_sensed_fuse; - struct nv_pmu_vfe_var_single_sensed_temp var_single_sensed_temp; - struct nv_pmu_vfe_var_single_voltage var_single_voltage; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(perf, vfe_var); - -struct nv_pmu_vfe_equ { - struct nv_pmu_boardobj super; - u8 var_idx; - u8 equ_idx_next; - u8 output_type; - u32 out_range_min; - u32 out_range_max; -}; - -struct nv_pmu_vfe_equ_compare { - struct nv_pmu_vfe_equ super; - u8 func_id; - u8 equ_idx_true; - u8 equ_idx_false; - u32 criteria; -}; - -struct nv_pmu_vfe_equ_minmax { - struct nv_pmu_vfe_equ super; - bool b_max; - u8 equ_idx0; - u8 equ_idx1; -}; - -struct nv_pmu_vfe_equ_quadratic { - struct nv_pmu_vfe_equ super; - u32 coeffs[CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT]; -}; - -struct nv_pmu_perf_vfe_equ_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e255 super; -}; - -union nv_pmu_perf_vfe_equ_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_vfe_equ equ; - struct nv_pmu_vfe_equ_compare equ_comapre; - struct nv_pmu_vfe_equ_minmax equ_minmax; - struct nv_pmu_vfe_equ_quadratic equ_quadratic; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E255(perf, vfe_equ); - -#endif /* _GPMUIFPERFVFE_H_*/ diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifpmgr.h b/drivers/gpu/nvgpu/pmuif/gpmuifpmgr.h deleted file mode 100644 index b6842fb7..00000000 --- a/drivers/gpu/nvgpu/pmuif/gpmuifpmgr.h +++ /dev/null @@ -1,434 +0,0 @@ -/* -* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms and conditions of the GNU General Public License, -* version 2, as published by the Free Software Foundation. -* -* This program is distributed in the hope it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -*/ - -#ifndef _GPMUIFPMGR_H_ -#define _GPMUIFPMGR_H_ - -#include "ctrl/ctrlpmgr.h" -#include "pmuif/gpmuifboardobj.h" -#include - -struct nv_pmu_pmgr_i2c_device_desc { - struct nv_pmu_boardobj super; - u8 dcb_index; - u16 i2c_address; - u32 i2c_flags; - u8 i2c_port; -}; - -#define NV_PMU_PMGR_I2C_DEVICE_DESC_TABLE_MAX_DEVICES (32) - -struct nv_pmu_pmgr_i2c_device_desc_table { - u32 dev_mask; - struct nv_pmu_pmgr_i2c_device_desc - devices[NV_PMU_PMGR_I2C_DEVICE_DESC_TABLE_MAX_DEVICES]; -}; - -struct nv_pmu_pmgr_pwr_device_desc { - struct nv_pmu_boardobj super; - u32 power_corr_factor; -}; - -#define NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM 0x03 - -struct nv_pmu_pmgr_pwr_device_desc_ina3221 { - struct nv_pmu_pmgr_pwr_device_desc super; - u8 i2c_dev_idx; - struct ctrl_pmgr_pwr_device_info_rshunt - r_shuntm_ohm[NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM]; - u16 configuration; - u16 mask_enable; - u32 event_mask; - u16 curr_correct_m; - s16 curr_correct_b; -}; - -union nv_pmu_pmgr_pwr_device_desc_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_pmgr_pwr_device_desc pwr_dev; - struct nv_pmu_pmgr_pwr_device_desc_ina3221 ina3221; -}; - -struct nv_pmu_pmgr_pwr_device_ba_info { - bool b_initialized_and_used; -}; - -struct nv_pmu_pmgr_pwr_device_desc_table_header { - struct nv_pmu_boardobjgrp_e32 super; - struct nv_pmu_pmgr_pwr_device_ba_info ba_info; -}; - -NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_device_desc_table_header, - sizeof(struct nv_pmu_pmgr_pwr_device_desc_table_header)); -NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_device_desc_union, - sizeof(union nv_pmu_pmgr_pwr_device_desc_union)); - -struct nv_pmu_pmgr_pwr_device_desc_table { - union nv_pmu_pmgr_pwr_device_desc_table_header_aligned hdr; - union nv_pmu_pmgr_pwr_device_desc_union_aligned - devices[CTRL_PMGR_PWR_DEVICES_MAX_DEVICES]; -}; - -union nv_pmu_pmgr_pwr_device_dmem_size { - union nv_pmu_pmgr_pwr_device_desc_table_header_aligned pwr_device_hdr; - union nv_pmu_pmgr_pwr_device_desc_union_aligned pwr_device; -}; - -struct nv_pmu_pmgr_pwr_channel { - struct nv_pmu_boardobj super; - u8 pwr_rail; - u8 ch_idx; - u32 volt_fixedu_v; - u32 pwr_corr_slope; - s32 pwr_corr_offsetm_w; - u32 curr_corr_slope; - s32 curr_corr_offsetm_a; - u32 dependent_ch_mask; -}; - -#define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHANNELS 16 - -#define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHRELATIONSHIPS 16 - -struct nv_pmu_pmgr_pwr_channel_sensor { - struct nv_pmu_pmgr_pwr_channel super; - u8 pwr_dev_idx; - u8 pwr_dev_prov_idx; -}; - -struct nv_pmu_pmgr_pwr_channel_pmu_compactible { - u8 pmu_compactible_data[56]; -}; - -union nv_pmu_pmgr_pwr_channel_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_pmgr_pwr_channel pwr_channel; - struct nv_pmu_pmgr_pwr_channel_sensor sensor; - struct nv_pmu_pmgr_pwr_channel_pmu_compactible pmu_pwr_channel; -}; - -#define NV_PMU_PMGR_PWR_MONITOR_TYPE_NO_POLLING 0x02 - -struct nv_pmu_pmgr_pwr_monitor_pstate { - u32 hw_channel_mask; -}; - -union nv_pmu_pmgr_pwr_monitor_type_specific { - struct nv_pmu_pmgr_pwr_monitor_pstate pstate; -}; - -struct nv_pmu_pmgr_pwr_chrelationship_pmu_compactible { - u8 pmu_compactible_data[28]; -}; - -union nv_pmu_pmgr_pwr_chrelationship_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_pmgr_pwr_chrelationship_pmu_compactible pmu_pwr_chrelationship; -}; - -struct nv_pmu_pmgr_pwr_channel_header { - struct nv_pmu_boardobjgrp_e32 super; - u8 type; - union nv_pmu_pmgr_pwr_monitor_type_specific type_specific; - u8 sample_count; - u16 sampling_periodms; - u16 sampling_period_low_powerms; - u32 total_gpu_power_channel_mask; - u32 physical_channel_mask; -}; - -struct nv_pmu_pmgr_pwr_chrelationship_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_channel_header, - sizeof(struct nv_pmu_pmgr_pwr_channel_header)); -NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_chrelationship_header, - sizeof(struct nv_pmu_pmgr_pwr_chrelationship_header)); -NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_chrelationship_union, - sizeof(union nv_pmu_pmgr_pwr_chrelationship_union)); -NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_channel_union, - sizeof(union nv_pmu_pmgr_pwr_channel_union)); - -struct nv_pmu_pmgr_pwr_channel_desc { - union nv_pmu_pmgr_pwr_channel_header_aligned hdr; - union nv_pmu_pmgr_pwr_channel_union_aligned - channels[NV_PMU_PMGR_PWR_CHANNEL_MAX_CHANNELS]; -}; - -struct nv_pmu_pmgr_pwr_chrelationship_desc { - union nv_pmu_pmgr_pwr_chrelationship_header_aligned hdr; - union nv_pmu_pmgr_pwr_chrelationship_union_aligned - ch_rels[NV_PMU_PMGR_PWR_CHANNEL_MAX_CHRELATIONSHIPS]; -}; - -union nv_pmu_pmgr_pwr_monitor_dmem_size { - union nv_pmu_pmgr_pwr_channel_header_aligned channel_hdr; - union nv_pmu_pmgr_pwr_channel_union_aligned channel; - union nv_pmu_pmgr_pwr_chrelationship_header_aligned ch_rels_hdr; - union nv_pmu_pmgr_pwr_chrelationship_union_aligned ch_rels; -}; - -struct nv_pmu_pmgr_pwr_monitor_pack { - struct nv_pmu_pmgr_pwr_channel_desc channels; - struct nv_pmu_pmgr_pwr_chrelationship_desc ch_rels; -}; - -#define NV_PMU_PMGR_PWR_POLICY_MAX_POLICIES 32 - -#define NV_PMU_PMGR_PWR_POLICY_MAX_POLICY_RELATIONSHIPS 32 - -struct nv_pmu_pmgr_pwr_policy { - struct nv_pmu_boardobj super; - u8 ch_idx; - u8 num_limit_inputs; - u8 limit_unit; - u8 sample_mult; - u32 limit_curr; - u32 limit_min; - u32 limit_max; - struct ctrl_pmgr_pwr_policy_info_integral integral; - enum ctrl_pmgr_pwr_policy_filter_type filter_type; - union ctrl_pmgr_pwr_policy_filter_param filter_param; -}; - -struct nv_pmu_pmgr_pwr_policy_hw_threshold { - struct nv_pmu_pmgr_pwr_policy super; - u8 threshold_idx; - u8 low_threshold_idx; - bool b_use_low_threshold; - u16 low_threshold_value; -}; - -struct nv_pmu_pmgr_pwr_policy_sw_threshold { - struct nv_pmu_pmgr_pwr_policy super; - u8 threshold_idx; - u8 low_threshold_idx; - bool b_use_low_threshold; - u16 low_threshold_value; - u8 event_id; -}; - -struct nv_pmu_pmgr_pwr_policy_pmu_compactible { - u8 pmu_compactible_data[68]; -}; - -union nv_pmu_pmgr_pwr_policy_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_pmgr_pwr_policy pwr_policy; - struct nv_pmu_pmgr_pwr_policy_hw_threshold hw_threshold; - struct nv_pmu_pmgr_pwr_policy_sw_threshold sw_threshold; - struct nv_pmu_pmgr_pwr_policy_pmu_compactible pmu_pwr_policy; -}; - -struct nv_pmu_pmgr_pwr_policy_relationship_pmu_compactible { - u8 pmu_compactible_data[24]; -}; - -union nv_pmu_pmgr_pwr_policy_relationship_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_pmgr_pwr_policy_relationship_pmu_compactible pmu_pwr_relationship; -}; - -struct nv_pmu_pmgr_pwr_violation_pmu_compactible { - u8 pmu_compactible_data[16]; -}; - -union nv_pmu_pmgr_pwr_violation_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_pmgr_pwr_violation_pmu_compactible violation; -}; - -#define NV_PMU_PMGR_PWR_POLICY_DESC_TABLE_VERSION_3X 0x30 - -NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_policy_union, - sizeof(union nv_pmu_pmgr_pwr_policy_union)); -NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_policy_relationship_union, - sizeof(union nv_pmu_pmgr_pwr_policy_relationship_union)); - -#define NV_PMU_PERF_DOMAIN_GROUP_MAX_GROUPS 2 - -struct nv_pmu_perf_domain_group_limits -{ - u32 values[NV_PMU_PERF_DOMAIN_GROUP_MAX_GROUPS]; -} ; - -#define NV_PMU_PMGR_RESERVED_PWR_POLICY_MASK_COUNT 0x6 - -struct nv_pmu_pmgr_pwr_policy_desc_header { - struct nv_pmu_boardobjgrp_e32 super; - u8 version; - bool b_enabled; - u8 low_sampling_mult; - u8 semantic_policy_tbl[CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES]; - u16 base_sample_period; - u16 min_client_sample_period; - u32 reserved_pmu_policy_mask[NV_PMU_PMGR_RESERVED_PWR_POLICY_MASK_COUNT]; - struct nv_pmu_perf_domain_group_limits global_ceiling; -}; - -NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_policy_desc_header , - sizeof(struct nv_pmu_pmgr_pwr_policy_desc_header )); - -struct nv_pmu_pmgr_pwr_policyrel_desc_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_policyrel_desc_header, - sizeof(struct nv_pmu_pmgr_pwr_policyrel_desc_header)); - -struct nv_pmu_pmgr_pwr_violation_desc_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_violation_desc_header, - sizeof(struct nv_pmu_pmgr_pwr_violation_desc_header)); -NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_violation_union, - sizeof(union nv_pmu_pmgr_pwr_violation_union)); - -struct nv_pmu_pmgr_pwr_policy_desc { - union nv_pmu_pmgr_pwr_policy_desc_header_aligned hdr; - union nv_pmu_pmgr_pwr_policy_union_aligned - policies[NV_PMU_PMGR_PWR_POLICY_MAX_POLICIES]; -}; - -struct nv_pmu_pmgr_pwr_policyrel_desc { - union nv_pmu_pmgr_pwr_policyrel_desc_header_aligned hdr; - union nv_pmu_pmgr_pwr_policy_relationship_union_aligned - policy_rels[NV_PMU_PMGR_PWR_POLICY_MAX_POLICY_RELATIONSHIPS]; -}; - -struct nv_pmu_pmgr_pwr_violation_desc { - union nv_pmu_pmgr_pwr_violation_desc_header_aligned hdr; - union nv_pmu_pmgr_pwr_violation_union_aligned - violations[CTRL_PMGR_PWR_VIOLATION_MAX]; -}; - -union nv_pmu_pmgr_pwr_policy_dmem_size { - union nv_pmu_pmgr_pwr_policy_desc_header_aligned policy_hdr; - union nv_pmu_pmgr_pwr_policy_union_aligned policy; - union nv_pmu_pmgr_pwr_policyrel_desc_header_aligned policy_rels_hdr; - union nv_pmu_pmgr_pwr_policy_relationship_union_aligned policy_rels; - union nv_pmu_pmgr_pwr_violation_desc_header_aligned violation_hdr; - union nv_pmu_pmgr_pwr_violation_union_aligned violation; -}; - -struct nv_pmu_pmgr_pwr_policy_pack { - struct nv_pmu_pmgr_pwr_policy_desc policies; - struct nv_pmu_pmgr_pwr_policyrel_desc policy_rels; - struct nv_pmu_pmgr_pwr_violation_desc violations; -}; - -#define NV_PMU_PMGR_CMD_ID_SET_OBJECT (0x00000000) - -#define NV_PMU_PMGR_MSG_ID_QUERY (0x00000002) - -#define NV_PMU_PMGR_CMD_ID_PWR_DEVICES_QUERY (0x00000001) - -#define NV_PMU_PMGR_CMD_ID_LOAD (0x00000006) - -#define NV_PMU_PMGR_CMD_ID_UNLOAD (0x00000007) - -struct nv_pmu_pmgr_cmd_set_object { - u8 cmd_type; - u8 pad[2]; - u8 object_type; - struct nv_pmu_allocation object; -}; - -#define NV_PMU_PMGR_SET_OBJECT_ALLOC_OFFSET (0x04) - -#define NV_PMU_PMGR_OBJECT_I2C_DEVICE_DESC_TABLE (0x00000000) - -#define NV_PMU_PMGR_OBJECT_PWR_DEVICE_DESC_TABLE (0x00000001) - -#define NV_PMU_PMGR_OBJECT_PWR_MONITOR (0x00000002) - -#define NV_PMU_PMGR_OBJECT_PWR_POLICY (0x00000005) - -struct nv_pmu_pmgr_pwr_devices_query_payload { - struct { - u32 powerm_w; - u32 voltageu_v; - u32 currentm_a; - } devices[CTRL_PMGR_PWR_DEVICES_MAX_DEVICES]; -}; - -struct nv_pmu_pmgr_cmd_pwr_devices_query { - u8 cmd_type; - u8 pad[3]; - u32 dev_mask; - struct nv_pmu_allocation payload; -}; - -#define NV_PMU_PMGR_PWR_DEVICES_QUERY_ALLOC_OFFSET (0x08) - -struct nv_pmu_pmgr_cmd_load { - u8 cmd_type; -}; - -struct nv_pmu_pmgr_cmd_unload { - u8 cmd_type; -}; - -struct nv_pmu_pmgr_cmd { - union { - u8 cmd_type; - struct nv_pmu_pmgr_cmd_set_object set_object; - struct nv_pmu_pmgr_cmd_pwr_devices_query pwr_dev_query; - struct nv_pmu_pmgr_cmd_load load; - struct nv_pmu_pmgr_cmd_unload unload; - }; -}; - -#define NV_PMU_PMGR_MSG_ID_SET_OBJECT (0x00000000) - -#define NV_PMU_PMGR_MSG_ID_LOAD (0x00000004) - -#define NV_PMU_PMGR_MSG_ID_UNLOAD (0x00000005) - -struct nv_pmu_pmgr_msg_set_object { - u8 msg_type; - bool b_success; - flcn_status flcnstatus; - u8 object_type; -}; - -struct nv_pmu_pmgr_msg_query { - u8 msg_type; - bool b_success; - flcn_status flcnstatus; - u8 cmd_type; -}; - -struct nv_pmu_pmgr_msg_load { - u8 msg_type; - bool b_success; - flcn_status flcnstatus; -}; - -struct nv_pmu_pmgr_msg_unload { - u8 msg_type; -}; - -struct nv_pmu_pmgr_msg { - union { - u8 msg_type; - struct nv_pmu_pmgr_msg_set_object set_object; - struct nv_pmu_pmgr_msg_query query; - struct nv_pmu_pmgr_msg_load load; - struct nv_pmu_pmgr_msg_unload unload; - }; -}; - -#endif diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifseq.h b/drivers/gpu/nvgpu/pmuif/gpmuifseq.h deleted file mode 100644 index 2927206f..00000000 --- a/drivers/gpu/nvgpu/pmuif/gpmuifseq.h +++ /dev/null @@ -1,73 +0,0 @@ -/* -* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms and conditions of the GNU General Public License, -* version 2, as published by the Free Software Foundation. -* -* This program is distributed in the hope it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -*/ -#ifndef _GPMUIFSEQ_H_ -#define _GPMUIFSEQ_H_ - -#include - -#define PMU_UNIT_SEQ (0x02) - -/*! -* @file gpmuifseq.h -* @brief PMU Command/Message Interfaces - Sequencer -*/ - -/*! -* Defines the identifiers various high-level types of sequencer commands. -* -* _RUN_SCRIPT @ref NV_PMU_SEQ_CMD_RUN_SCRIPT -*/ -enum { - NV_PMU_SEQ_CMD_ID_RUN_SCRIPT = 0, -}; - -struct nv_pmu_seq_cmd_run_script { - u8 cmd_type; - u8 pad[3]; - struct pmu_allocation_v3 script_alloc; - struct pmu_allocation_v3 reg_alloc; -}; - -#define NV_PMU_SEQ_CMD_ALLOC_OFFSET 4 - -#define NV_PMU_SEQ_MSG_ALLOC_OFFSET \ - (NV_PMU_SEQ_CMD_ALLOC_OFFSET + NV_PMU_CMD_ALLOC_SIZE) - -struct nv_pmu_seq_cmd { - struct pmu_hdr hdr; - union { - u8 cmd_type; - struct nv_pmu_seq_cmd_run_script run_script; - }; -}; - -enum { - NV_PMU_SEQ_MSG_ID_RUN_SCRIPT = 0, -}; - -struct nv_pmu_seq_msg_run_script { - u8 msg_type; - u8 error_code; - u16 error_pc; - u32 timeout_stat; -}; - -struct nv_pmu_seq_msg { - struct pmu_hdr hdr; - union { - u8 msg_type; - struct nv_pmu_seq_msg_run_script run_script; - }; -}; - -#endif diff --git a/drivers/gpu/nvgpu/pmuif/gpmuiftherm.h b/drivers/gpu/nvgpu/pmuif/gpmuiftherm.h deleted file mode 100644 index 27e811ff..00000000 --- a/drivers/gpu/nvgpu/pmuif/gpmuiftherm.h +++ /dev/null @@ -1,93 +0,0 @@ -/* -* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms and conditions of the GNU General Public License, -* version 2, as published by the Free Software Foundation. -* -* This program is distributed in the hope it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -*/ - -#ifndef _GPMUIFTHERM_H_ -#define _GPMUIFTHERM_H_ - -#include - -#define NV_PMU_THERM_CMD_ID_RPC 0x00000002 -#define NV_PMU_THERM_MSG_ID_RPC 0x00000002 -#define NV_PMU_THERM_RPC_ID_SLCT 0x00000000 -#define NV_PMU_THERM_RPC_ID_SLCT_EVENT_TEMP_TH_SET 0x00000006 -#define NV_PMU_THERM_EVENT_THERMAL_1 0x00000004 -#define NV_PMU_THERM_CMD_ID_HW_SLOWDOWN_NOTIFICATION 0x00000001 -#define NV_RM_PMU_THERM_HW_SLOWDOWN_NOTIFICATION_REQUEST_ENABLE 0x00000001 -#define NV_PMU_THERM_MSG_ID_EVENT_HW_SLOWDOWN_NOTIFICATION 0x00000001 - -struct nv_pmu_therm_rpc_slct_event_temp_th_set { - s32 temp_threshold; - u8 event_id; - flcn_status flcn_stat; -}; - -struct nv_pmu_therm_rpc_slct { - u32 mask_enabled; - flcn_status flcn_stat; -}; - -struct nv_pmu_therm_rpc { - u8 function; - bool b_supported; - union { - struct nv_pmu_therm_rpc_slct slct; - struct nv_pmu_therm_rpc_slct_event_temp_th_set slct_event_temp_th_set; - } params; -}; - -struct nv_pmu_therm_cmd_rpc { - u8 cmd_type; - u8 pad[3]; - struct nv_pmu_allocation request; -}; - -struct nv_pmu_therm_cmd_hw_slowdown_notification { - u8 cmd_type; - u8 request; -}; - -#define NV_PMU_THERM_CMD_RPC_ALLOC_OFFSET \ - offsetof(struct nv_pmu_therm_cmd_rpc, request) - -struct nv_pmu_therm_cmd { - union { - u8 cmd_type; - struct nv_pmu_therm_cmd_rpc rpc; - struct nv_pmu_therm_cmd_hw_slowdown_notification hw_slct_notification; - }; -}; - -struct nv_pmu_therm_msg_rpc { - u8 msg_type; - u8 rsvd[3]; - struct nv_pmu_allocation response; -}; - -struct nv_pmu_therm_msg_event_hw_slowdown_notification { - u8 msg_type; - u32 mask; -}; - -#define NV_PMU_THERM_MSG_RPC_ALLOC_OFFSET \ - offsetof(struct nv_pmu_therm_msg_rpc, response) - -struct nv_pmu_therm_msg { - union { - u8 msg_type; - struct nv_pmu_therm_msg_rpc rpc; - struct nv_pmu_therm_msg_event_hw_slowdown_notification hw_slct_msg; - }; -}; - -#endif - diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifthermsensor.h b/drivers/gpu/nvgpu/pmuif/gpmuifthermsensor.h deleted file mode 100644 index bc2b4f52..00000000 --- a/drivers/gpu/nvgpu/pmuif/gpmuifthermsensor.h +++ /dev/null @@ -1,74 +0,0 @@ -/* -* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms and conditions of the GNU General Public License, -* version 2, as published by the Free Software Foundation. -* -* This program is distributed in the hope it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -*/ - -#ifndef _GPMUIFTHERMSENSOR_H_ -#define _GPMUIFTHERMSENSOR_H_ - -#include "ctrl/ctrltherm.h" -#include "pmuif/gpmuifboardobj.h" -#include - -#define NV_PMU_THERM_BOARDOBJGRP_CLASS_ID_THERM_DEVICE 0x00 -#define NV_PMU_THERM_BOARDOBJGRP_CLASS_ID_THERM_CHANNEL 0x01 - -#define NV_PMU_THERM_CMD_ID_BOARDOBJ_GRP_SET 0x0000000B -#define NV_PMU_THERM_MSG_ID_BOARDOBJ_GRP_SET 0x00000008 - -struct nv_pmu_therm_therm_device_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -struct nv_pmu_therm_therm_device_boardobj_set { - struct nv_pmu_boardobj super; -}; - -struct nv_pmu_therm_therm_device_i2c_boardobj_set { - struct nv_pmu_therm_therm_device_boardobj_set super; - u8 i2c_dev_idx; -}; - -union nv_pmu_therm_therm_device_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_therm_therm_device_boardobj_set therm_device; - struct nv_pmu_therm_therm_device_i2c_boardobj_set i2c; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(therm, therm_device); - -struct nv_pmu_therm_therm_channel_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -struct nv_pmu_therm_therm_channel_boardobj_set { - struct nv_pmu_boardobj super; - s16 scaling; - s16 offset; - s32 temp_min; - s32 temp_max; -}; - -struct nv_pmu_therm_therm_channel_device_boardobj_set { - struct nv_pmu_therm_therm_channel_boardobj_set super; - u8 therm_dev_idx; - u8 therm_dev_prov_idx; -}; - -union nv_pmu_therm_therm_channel_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_therm_therm_channel_boardobj_set therm_channel; - struct nv_pmu_therm_therm_channel_device_boardobj_set device; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(therm, therm_channel); - -#endif diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifvolt.h b/drivers/gpu/nvgpu/pmuif/gpmuifvolt.h deleted file mode 100644 index b4dea724..00000000 --- a/drivers/gpu/nvgpu/pmuif/gpmuifvolt.h +++ /dev/null @@ -1,326 +0,0 @@ -/* -* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify it -* under the terms and conditions of the GNU General Public License, -* version 2, as published by the Free Software Foundation. -* -* This program is distributed in the hope it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -*/ -#ifndef _GPMUIFVOLT_H_ -#define _GPMUIFVOLT_H_ - -#include "pmuif/gpmuifboardobj.h" -#include -#include "ctrl/ctrlvolt.h" - -#define NV_PMU_VOLT_VALUE_0V_IN_UV (0) - -/* ------------- VOLT_RAIL's GRP_SET defines and structures ------------- */ - -#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_RAIL 0x00 -#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_DEVICE 0x01 -#define NV_PMU_VOLT_BOARDOBJGRP_CLASS_ID_VOLT_POLICY 0x02 - - -struct nv_pmu_volt_volt_rail_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -struct nv_pmu_volt_volt_rail_boardobj_set { - - struct nv_pmu_boardobj super; - u8 rel_limit_vfe_equ_idx; - u8 alt_rel_limit_vfe_equ_idx; - u8 ov_limit_vfe_equ_idx; - u8 vmin_limit_vfe_equ_idx; - u8 volt_margin_limit_vfe_equ_idx; - u8 pwr_equ_idx; - u8 volt_dev_idx_default; - struct ctrl_boardobjgrp_mask_e32 volt_dev_mask; - s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES]; -}; - -union nv_pmu_volt_volt_rail_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_volt_volt_rail_boardobj_set super; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_rail); - -/* ------------ VOLT_DEVICE's GRP_SET defines and structures ------------ */ - -struct nv_pmu_volt_volt_device_boardobjgrp_set_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -struct nv_pmu_volt_volt_device_boardobj_set { - struct nv_pmu_boardobj super; - u32 switch_delay_us; - u32 voltage_min_uv; - u32 voltage_max_uv; - u32 volt_step_uv; -}; - -struct nv_pmu_volt_volt_device_vid_boardobj_set { - struct nv_pmu_volt_volt_device_boardobj_set super; - s32 voltage_base_uv; - s32 voltage_offset_scale_uv; - u8 gpio_pin[CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES]; - u8 vsel_mask; -}; - -struct nv_pmu_volt_volt_device_pwm_boardobj_set { - struct nv_pmu_volt_volt_device_boardobj_set super; - u32 raw_period; - s32 voltage_base_uv; - s32 voltage_offset_scale_uv; - enum nv_pmu_pmgr_pwm_source pwm_source; -}; - -union nv_pmu_volt_volt_device_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_volt_volt_device_boardobj_set super; - struct nv_pmu_volt_volt_device_vid_boardobj_set vid; - struct nv_pmu_volt_volt_device_pwm_boardobj_set pwm; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_device); - -/* ------------ VOLT_POLICY's GRP_SET defines and structures ------------ */ -struct nv_pmu_volt_volt_policy_boardobjgrp_set_header { - - struct nv_pmu_boardobjgrp_e32 super; -}; - -struct nv_pmu_volt_volt_policy_boardobj_set { - struct nv_pmu_boardobj super; -}; -struct nv_pmu_volt_volt_policy_sr_boardobj_set { - struct nv_pmu_volt_volt_policy_boardobj_set super; - u8 rail_idx; -}; - -struct nv_pmu_volt_volt_policy_splt_r_boardobj_set { - struct nv_pmu_volt_volt_policy_boardobj_set super; - u8 rail_idx_master; - u8 rail_idx_slave; - u8 delta_min_vfe_equ_idx; - u8 delta_max_vfe_equ_idx; - s32 offset_delta_min_uv; - s32 offset_delta_max_uv; -}; - -struct nv_pmu_volt_volt_policy_srms_boardobj_set { - struct nv_pmu_volt_volt_policy_splt_r_boardobj_set super; - u16 inter_switch_delayus; -}; - -/* sr - > single_rail */ -struct nv_pmu_volt_volt_policy_srss_boardobj_set { - struct nv_pmu_volt_volt_policy_splt_r_boardobj_set super; -}; - -union nv_pmu_volt_volt_policy_boardobj_set_union { - struct nv_pmu_boardobj board_obj; - struct nv_pmu_volt_volt_policy_boardobj_set super; - struct nv_pmu_volt_volt_policy_sr_boardobj_set single_rail; - struct nv_pmu_volt_volt_policy_splt_r_boardobj_set split_rail; - struct nv_pmu_volt_volt_policy_srms_boardobj_set - split_rail_m_s; - struct nv_pmu_volt_volt_policy_srss_boardobj_set - split_rail_s_s; -}; - -NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(volt, volt_policy); - -/* ----------- VOLT_RAIL's GRP_GET_STATUS defines and structures ----------- */ -struct nv_pmu_volt_volt_rail_boardobjgrp_get_status_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -struct nv_pmu_volt_volt_rail_boardobj_get_status { - struct nv_pmu_boardobj_query super; - u32 curr_volt_defaultu_v; - u32 rel_limitu_v; - u32 alt_rel_limitu_v; - u32 ov_limitu_v; - u32 max_limitu_v; - u32 vmin_limitu_v; - s32 volt_margin_limitu_v; - u32 rsvd; -}; - -union nv_pmu_volt_volt_rail_boardobj_get_status_union { - struct nv_pmu_boardobj_query board_obj; - struct nv_pmu_volt_volt_rail_boardobj_get_status super; -}; - -NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_rail); - -/* ---------- VOLT_DEVICE's GRP_GET_STATUS defines and structures ---------- */ -struct nv_pmu_volt_volt_device_boardobjgrp_get_status_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -struct nv_pmu_volt_volt_device_boardobj_get_status { - struct nv_pmu_boardobj_query super; -}; - -union nv_pmu_volt_volt_device_boardobj_get_status_union { - struct nv_pmu_boardobj_query board_obj; - struct nv_pmu_volt_volt_device_boardobj_get_status super; -}; - -NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_device); - -/* ---------- VOLT_POLICY's GRP_GET_STATUS defines and structures ---------- */ -struct nv_pmu_volt_volt_policy_boardobjgrp_get_status_header { - struct nv_pmu_boardobjgrp_e32 super; -}; - -struct nv_pmu_volt_volt_policy_boardobj_get_status { - struct nv_pmu_boardobj_query super; - u32 offset_volt_requ_v; - u32 offset_volt_curru_v; -}; - -struct nv_pmu_volt_volt_policy_sr_boardobj_get_status { - struct nv_pmu_volt_volt_policy_boardobj_get_status super; - u32 curr_voltu_v; -}; - -struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status { - struct nv_pmu_volt_volt_policy_boardobj_get_status super; - s32 delta_minu_v; - s32 delta_maxu_v; - s32 orig_delta_minu_v; - s32 orig_delta_maxu_v; - u32 curr_volt_masteru_v; - u32 curr_volt_slaveu_v; - bool b_violation; -}; - -/* srms -> split_rail_multi_step */ -struct nv_pmu_volt_volt_policy_srms_boardobj_get_status { - struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status super; -}; - -/* srss -> split_rail_single_step */ -struct nv_pmu_volt_volt_policy_srss_boardobj_get_status { - struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status super; -}; - -union nv_pmu_volt_volt_policy_boardobj_get_status_union { - struct nv_pmu_boardobj_query board_obj; - struct nv_pmu_volt_volt_policy_boardobj_get_status super; - struct nv_pmu_volt_volt_policy_sr_boardobj_get_status single_rail; - struct nv_pmu_volt_volt_policy_splt_r_boardobj_get_status split_rail; - struct nv_pmu_volt_volt_policy_srms_boardobj_get_status - split_rail_m_s; - struct nv_pmu_volt_volt_policy_srss_boardobj_get_status - split_rail_s_s; -}; - -NV_PMU_BOARDOBJ_GRP_GET_STATUS_MAKE_E32(volt, volt_policy); - -struct nv_pmu_volt_policy_voltage_data { - u8 policy_idx; - struct ctrl_perf_volt_rail_list - rail_list; -}; - -struct nv_pmu_volt_rail_get_voltage { - u8 rail_idx; - u32 voltage_uv; -}; - -struct nv_pmu_volt_volt_rail_set_noise_unaware_vmin { - u8 num_rails; - struct ctrl_volt_volt_rail_list - rail_list; -}; - -#define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_SET (0x00000000) -#define NV_PMU_VOLT_CMD_ID_RPC (0x00000001) -#define NV_PMU_VOLT_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) -#define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_SET_NOISE_UNAWARE_VMIN (0x00000004) - -/*! -* PMU VOLT RPC calls. -*/ -#define NV_PMU_VOLT_RPC_ID_LOAD (0x00000000) -#define NV_PMU_VOLT_RPC_ID_VOLT_POLICY_SET_VOLTAGE (0x00000002) -#define NV_PMU_VOLT_RPC_ID_VOLT_RAIL_GET_VOLTAGE (0x00000003) - -struct nv_pmu_volt_cmd_rpc { - u8 cmd_type; - u8 pad[3]; - struct nv_pmu_allocation request; -}; - -#define NV_PMU_VOLT_CMD_RPC_ALLOC_OFFSET \ - offsetof(struct nv_pmu_volt_cmd_rpc, request) - -struct nv_pmu_volt_cmd { - union { - u8 cmd_type; - struct nv_pmu_boardobj_cmd_grp grp_set; - struct nv_pmu_volt_cmd_rpc rpc; - struct nv_pmu_boardobj_cmd_grp grp_get_status; - }; -}; - -struct nv_pmu_volt_rpc { - u8 function; - bool b_supported; - bool b_success; - flcn_status flcn_status; - union { - struct nv_pmu_volt_policy_voltage_data volt_policy_voltage_data; - struct nv_pmu_volt_rail_get_voltage volt_rail_get_voltage; - struct nv_pmu_volt_volt_rail_set_noise_unaware_vmin - volt_rail_set_noise_unaware_vmin; - } params; -}; - -/*! -* VOLT MSG ID definitions -*/ -#define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_SET (0x00000000) -#define NV_PMU_VOLT_MSG_ID_RPC (0x00000001) -#define NV_PMU_VOLT_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) - -/*! -* Message carrying the result of the VOLT RPC execution. -*/ -struct nv_pmu_volt_msg_rpc { - u8 msg_type; - u8 rsvd[3]; - struct nv_pmu_allocation response; -}; - -#define NV_PMU_VOLT_MSG_RPC_ALLOC_OFFSET \ - offsetof(struct nv_pmu_volt_msg_rpc, response) - -struct nv_pmu_volt_msg { - union { - u8 msg_type; - struct nv_pmu_boardobj_msg_grp grp_set; - struct nv_pmu_volt_msg_rpc rpc; - struct nv_pmu_boardobj_msg_grp grp_get_status; - }; -}; - -#define NV_PMU_VF_INJECT_MAX_VOLT_RAILS (2) - -struct nv_pmu_volt_volt_rail_list { - u8 num_rails; - struct ctrl_perf_volt_rail_list_item - rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS]; -}; - -#endif /* _GPMUIFVOLT_H_*/ diff --git a/drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h b/drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h deleted file mode 100644 index 91175c69..00000000 --- a/drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ -#ifndef _NVGPUGPMUCMDIF_H_ -#define _NVGPUGPMUCMDIF_H_ - -#include -#include "gpmuif_cmn.h" -#include "gpmuif_pmu.h" -#include "gpmuif_ap.h" -#include "gpmuif_pg.h" -#include "gpmuif_perfmon.h" -#include "gpmuif_acr.h" -#include "gpmuifboardobj.h" -#include "gpmuifclk.h" -#include "gpmuifperf.h" -#include "gpmuifpmgr.h" -#include "gpmuifvolt.h" -#include "gpmuiftherm.h" - -struct pmu_cmd { - struct pmu_hdr hdr; - union { - struct pmu_perfmon_cmd perfmon; - struct pmu_pg_cmd pg; - struct pmu_zbc_cmd zbc; - struct pmu_acr_cmd acr; - struct nv_pmu_boardobj_cmd boardobj; - struct nv_pmu_perf_cmd perf; - struct nv_pmu_volt_cmd volt; - struct nv_pmu_clk_cmd clk; - struct nv_pmu_pmgr_cmd pmgr; - struct nv_pmu_therm_cmd therm; - } cmd; -}; - -struct pmu_msg { - struct pmu_hdr hdr; - union { - struct pmu_init_msg init; - struct pmu_perfmon_msg perfmon; - struct pmu_pg_msg pg; - struct pmu_rc_msg rc; - struct pmu_acr_msg acr; - struct nv_pmu_boardobj_msg boardobj; - struct nv_pmu_perf_msg perf; - struct nv_pmu_volt_msg volt; - struct nv_pmu_clk_msg clk; - struct nv_pmu_pmgr_msg pmgr; - struct nv_pmu_therm_msg therm; - } msg; -}; - -#define PMU_UNIT_REWIND (0x00) -#define PMU_UNIT_PG (0x03) -#define PMU_UNIT_INIT (0x07) -#define PMU_UNIT_ACR (0x0A) -#define PMU_UNIT_PERFMON_T18X (0x11) -#define PMU_UNIT_PERFMON (0x12) -#define PMU_UNIT_PERF (0x13) -#define PMU_UNIT_RC (0x1F) -#define PMU_UNIT_FECS_MEM_OVERRIDE (0x1E) -#define PMU_UNIT_CLK (0x0D) -#define PMU_UNIT_THERM (0x14) -#define PMU_UNIT_PMGR (0x18) -#define PMU_UNIT_VOLT (0x0E) - -#define PMU_UNIT_END (0x23) - -#define PMU_UNIT_TEST_START (0xFE) -#define PMU_UNIT_END_SIM (0xFF) -#define PMU_UNIT_TEST_END (0xFF) - -#define PMU_UNIT_ID_IS_VALID(id) \ - (((id) < PMU_UNIT_END) || ((id) >= PMU_UNIT_TEST_START)) - -#endif /* _NVGPUGPMUCMDIF_H_*/ diff --git a/drivers/gpu/nvgpu/therm/thrmchannel.c b/drivers/gpu/nvgpu/therm/thrmchannel.c index aa40dac8..f253a196 100644 --- a/drivers/gpu/nvgpu/therm/thrmchannel.c +++ b/drivers/gpu/nvgpu/therm/thrmchannel.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,8 +16,7 @@ #include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" -#include "pmuif/gpmuifboardobj.h" -#include "pmuif/gpmuifthermsensor.h" +#include #include "gm206/bios_gm206.h" #include "gk20a/pmu_gk20a.h" diff --git a/drivers/gpu/nvgpu/therm/thrmdev.c b/drivers/gpu/nvgpu/therm/thrmdev.c index 9bb77537..3ff199e7 100644 --- a/drivers/gpu/nvgpu/therm/thrmdev.c +++ b/drivers/gpu/nvgpu/therm/thrmdev.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,8 +16,7 @@ #include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" -#include "pmuif/gpmuifboardobj.h" -#include "pmuif/gpmuifthermsensor.h" +#include #include "gm206/bios_gm206.h" #include "gk20a/pmu_gk20a.h" #include "ctrl/ctrltherm.h" diff --git a/drivers/gpu/nvgpu/therm/thrmpmu.c b/drivers/gpu/nvgpu/therm/thrmpmu.c index 0f780730..a06d3b92 100644 --- a/drivers/gpu/nvgpu/therm/thrmpmu.c +++ b/drivers/gpu/nvgpu/therm/thrmpmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,9 +15,8 @@ #include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" -#include "pmuif/gpmuifboardobj.h" #include "thrmpmu.h" -#include "pmuif/gpmuiftherm.h" +#include struct therm_pmucmdhandler_params { struct nv_pmu_therm_rpc *prpccall; diff --git a/drivers/gpu/nvgpu/volt/volt_dev.c b/drivers/gpu/nvgpu/volt/volt_dev.c index 3a7ed1b5..ebc140ef 100644 --- a/drivers/gpu/nvgpu/volt/volt_dev.c +++ b/drivers/gpu/nvgpu/volt/volt_dev.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,14 +17,13 @@ #include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" -#include "pmuif/gpmuifboardobj.h" #include "gm206/bios_gm206.h" #include "ctrl/ctrlvolt.h" #include "gk20a/pmu_gk20a.h" -#include "pmuif/gpmuifperfvfe.h" #include "include/bios.h" #include "volt.h" +#include #define VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID 0 #define VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT 1 diff --git a/drivers/gpu/nvgpu/volt/volt_pmu.c b/drivers/gpu/nvgpu/volt/volt_pmu.c index 4e7f73c9..488e67a3 100644 --- a/drivers/gpu/nvgpu/volt/volt_pmu.c +++ b/drivers/gpu/nvgpu/volt/volt_pmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,16 +15,14 @@ #include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" -#include "pmuif/gpmuifboardobj.h" #include "gm206/bios_gm206.h" #include "ctrl/ctrlvolt.h" #include "ctrl/ctrlperf.h" #include "gk20a/pmu_gk20a.h" -#include "pmuif/gpmuifperfvfe.h" -#include "pmuif/gpmuifvolt.h" #include "include/bios.h" #include "volt.h" +#include #define RAIL_COUNT 2 diff --git a/drivers/gpu/nvgpu/volt/volt_policy.c b/drivers/gpu/nvgpu/volt/volt_policy.c index ee3e74b8..e943e771 100644 --- a/drivers/gpu/nvgpu/volt/volt_policy.c +++ b/drivers/gpu/nvgpu/volt/volt_policy.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,12 +15,11 @@ #include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" -#include "pmuif/gpmuifboardobj.h" #include "gm206/bios_gm206.h" #include "ctrl/ctrlvolt.h" #include "gk20a/pmu_gk20a.h" -#include "pmuif/gpmuifperfvfe.h" +#include #include "include/bios.h" #include "volt.h" diff --git a/drivers/gpu/nvgpu/volt/volt_rail.c b/drivers/gpu/nvgpu/volt/volt_rail.c index 87b85160..6d606228 100644 --- a/drivers/gpu/nvgpu/volt/volt_rail.c +++ b/drivers/gpu/nvgpu/volt/volt_rail.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,12 +15,11 @@ #include "include/bios.h" #include "boardobj/boardobjgrp.h" #include "boardobj/boardobjgrp_e32.h" -#include "pmuif/gpmuifboardobj.h" #include "gm206/bios_gm206.h" #include "ctrl/ctrlvolt.h" #include "gk20a/pmu_gk20a.h" -#include "pmuif/gpmuifperfvfe.h" +#include #include "include/bios.h" #include "volt.h" -- cgit v1.2.2