From 312f6c2c5f8b2ad6ab95300896ec4e7be9d5f833 Mon Sep 17 00:00:00 2001 From: Debarshi Dutta Date: Wed, 22 Nov 2017 13:20:19 +0530 Subject: gpu: nvgpu: remove dependency on linux header for sim_gk20a* This patch removes linux dependencies from sim_gk20a.h under gk20a/sim_gk20a.h. The following changes are made in this patch. 1) Created a linux based structure sim_gk20a_linux that contains a common sim_gk20a struct inside it. The common struct sim_gk20a doesn't contain any linux specific structs. 2) The common struct sim_gk20a contains an added function pointer which is used to invoke gk20a_sim_esc_readl() method. 3) sim_gk20a.c is moved to nvgpu/common/linux along with a new header sim_gk20a.h that contains the definition of struct sim_gk20a_linux. 4) struct gk20a now contains a pointer of sim_gk20a instead of the entire object. The memory for this struct is allocated and initialized during gk20a_init_support() and freed during invocation of gk20_remove_support(). 5) We first obtain the pointer for struct sim_gk20a_linux from the pointer of sim_gk20a using the container_of method in order to work on the struct. JIRA NVGPU-386 Change-Id: Ic82b8702642377f82694577a53c3ca0b9c1bb2ab Signed-off-by: Debarshi Dutta Reviewed-on: https://git-master.nvidia.com/r/1603073 GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 2 +- drivers/gpu/nvgpu/common/linux/module.c | 23 +- drivers/gpu/nvgpu/common/linux/sim_gk20a.c | 365 +++++++++++++++++++++++++++++ drivers/gpu/nvgpu/common/linux/sim_gk20a.h | 39 +++ drivers/gpu/nvgpu/gk20a/gk20a.h | 2 +- drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c | 131 ++++++----- drivers/gpu/nvgpu/gk20a/sim_gk20a.c | 343 --------------------------- drivers/gpu/nvgpu/gk20a/sim_gk20a.h | 15 +- 8 files changed, 492 insertions(+), 428 deletions(-) create mode 100644 drivers/gpu/nvgpu/common/linux/sim_gk20a.c create mode 100644 drivers/gpu/nvgpu/common/linux/sim_gk20a.h delete mode 100644 drivers/gpu/nvgpu/gk20a/sim_gk20a.c (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 29966d84..ef8237f3 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -48,6 +48,7 @@ nvgpu-y := \ common/linux/sched.o \ common/linux/channel.o \ common/linux/ce2.o \ + common/linux/sim_gk20a.o \ common/mm/nvgpu_allocator.o \ common/mm/bitmap_allocator.o \ common/mm/buddy_allocator.o \ @@ -99,7 +100,6 @@ nvgpu-y := \ gk20a/tsg_gk20a.o \ gk20a/fecs_trace_gk20a.o \ gk20a/mc_gk20a.o \ - gk20a/sim_gk20a.o \ gm20b/hal_gm20b.o \ gm20b/bus_gm20b.o \ gm20b/ltc_gm20b.o \ diff --git a/drivers/gpu/nvgpu/common/linux/module.c b/drivers/gpu/nvgpu/common/linux/module.c index 4af62d5f..950b1581 100644 --- a/drivers/gpu/nvgpu/common/linux/module.c +++ b/drivers/gpu/nvgpu/common/linux/module.c @@ -47,6 +47,7 @@ #include "intr.h" #include "cde.h" #include "ioctl.h" +#include "sim_gk20a.h" #ifdef CONFIG_TEGRA_19x_GPU #include "nvgpu_gpuid_t19x.h" #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION @@ -637,11 +638,10 @@ void gk20a_remove_support(struct gk20a *g) if (g->mm.remove_support) g->mm.remove_support(&g->mm); - if (g->sim.remove_support) - g->sim.remove_support(&g->sim); + if (g->sim->remove_support) + g->sim->remove_support(g->sim); /* free mappings to registers, etc */ - if (l->regs) { iounmap(l->regs); l->regs = NULL; @@ -661,6 +661,11 @@ static int gk20a_init_support(struct platform_device *dev) int err = 0; struct gk20a *g = get_gk20a(&dev->dev); struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); + struct sim_gk20a_linux *sim_linux = nvgpu_kzalloc(g, sizeof(*sim_linux)); + if (!sim_linux) + goto fail; + + g->sim = &sim_linux->sim; tegra_register_idle_unidle(gk20a_do_idle, gk20a_do_unidle, g); @@ -681,13 +686,13 @@ static int gk20a_init_support(struct platform_device *dev) } if (nvgpu_platform_is_simulation(g)) { - g->sim.g = g; - g->sim.regs = gk20a_ioremap_resource(dev, + g->sim->g = g; + sim_linux->regs = gk20a_ioremap_resource(dev, GK20A_SIM_IORESOURCE_MEM, - &g->sim.reg_mem); - if (IS_ERR(g->sim.regs)) { + &sim_linux->reg_mem); + if (IS_ERR(sim_linux->regs)) { nvgpu_err(g, "failed to remap gk20a sim regs"); - err = PTR_ERR(g->sim.regs); + err = PTR_ERR(sim_linux->regs); goto fail; } @@ -703,6 +708,8 @@ static int gk20a_init_support(struct platform_device *dev) return 0; fail: + nvgpu_kfree(g, sim_linux); + g->sim = NULL; return err; } diff --git a/drivers/gpu/nvgpu/common/linux/sim_gk20a.c b/drivers/gpu/nvgpu/common/linux/sim_gk20a.c new file mode 100644 index 00000000..6b148df6 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/sim_gk20a.c @@ -0,0 +1,365 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include + +#include +#include + +#include "gk20a/gk20a.h" +#include "sim_gk20a.h" + +#include + +static inline void sim_writel(struct sim_gk20a_linux *sim_linux, u32 r, u32 v) +{ + writel(v, sim_linux->regs + r); +} + +static inline u32 sim_readl(struct sim_gk20a_linux *sim_linux, u32 r) +{ + return readl(sim_linux->regs + r); +} + +static void kunmap_and_free_iopage(void **kvaddr, struct page **page) +{ + if (*kvaddr) { + kunmap(*kvaddr); + *kvaddr = NULL; + } + if (*page) { + __free_page(*page); + *page = NULL; + } +} + +static void gk20a_free_sim_support(struct gk20a *g) +{ + struct sim_gk20a_linux *sim_linux = + container_of(g->sim, struct sim_gk20a_linux, sim); + /* free sim mappings, bfrs */ + kunmap_and_free_iopage(&sim_linux->send_bfr.kvaddr, + &sim_linux->send_bfr.page); + + kunmap_and_free_iopage(&sim_linux->recv_bfr.kvaddr, + &sim_linux->recv_bfr.page); + + kunmap_and_free_iopage(&sim_linux->msg_bfr.kvaddr, + &sim_linux->msg_bfr.page); +} + +static void gk20a_remove_sim_support(struct sim_gk20a *s) +{ + struct gk20a *g = s->g; + struct sim_gk20a_linux *sim_linux = + container_of(g->sim, struct sim_gk20a_linux, sim); + + if (sim_linux->regs) + sim_writel(sim_linux, sim_config_r(), sim_config_mode_disabled_v()); + gk20a_free_sim_support(g); + + if (sim_linux->regs) { + iounmap(sim_linux->regs); + sim_linux->regs = NULL; + } + + nvgpu_kfree(g, sim_linux); + g->sim = NULL; +} + +static int alloc_and_kmap_iopage(struct gk20a *g, + void **kvaddr, + u64 *phys, + struct page **page) +{ + int err = 0; + *page = alloc_page(GFP_KERNEL); + + if (!*page) { + err = -ENOMEM; + nvgpu_err(g, "couldn't allocate io page"); + goto fail; + } + + *kvaddr = kmap(*page); + if (!*kvaddr) { + err = -ENOMEM; + nvgpu_err(g, "couldn't kmap io page"); + goto fail; + } + *phys = page_to_phys(*page); + return 0; + + fail: + kunmap_and_free_iopage(kvaddr, page); + return err; + +} + +static inline u32 sim_msg_header_size(void) +{ + return 24;/*TBD: fix the header to gt this from NV_VGPU_MSG_HEADER*/ +} + +static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset) +{ + struct sim_gk20a_linux *sim_linux = + container_of(g->sim, struct sim_gk20a_linux, sim); + return (u32 *)(sim_linux->msg_bfr.kvaddr + byte_offset); +} + +static inline u32 *sim_msg_hdr(struct gk20a *g, u32 byte_offset) +{ + return sim_msg_bfr(g, byte_offset); /*starts at 0*/ +} + +static inline u32 *sim_msg_param(struct gk20a *g, u32 byte_offset) +{ + /*starts after msg header/cmn*/ + return sim_msg_bfr(g, byte_offset + sim_msg_header_size()); +} + +static inline void sim_write_hdr(struct gk20a *g, u32 func, u32 size) +{ + /*memset(g->sim->msg_bfr.kvaddr,0,min(PAGE_SIZE,size));*/ + *sim_msg_hdr(g, sim_msg_signature_r()) = sim_msg_signature_valid_v(); + *sim_msg_hdr(g, sim_msg_result_r()) = sim_msg_result_rpc_pending_v(); + *sim_msg_hdr(g, sim_msg_spare_r()) = sim_msg_spare__init_v(); + *sim_msg_hdr(g, sim_msg_function_r()) = func; + *sim_msg_hdr(g, sim_msg_length_r()) = size + sim_msg_header_size(); +} + +static inline u32 sim_escape_read_hdr_size(void) +{ + return 12; /*TBD: fix NV_VGPU_SIM_ESCAPE_READ_HEADER*/ +} + +static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset) +{ + struct sim_gk20a_linux *sim_linux = + container_of(g->sim, struct sim_gk20a_linux, sim); + return (u32 *)(sim_linux->send_bfr.kvaddr + byte_offset); +} + +static int rpc_send_message(struct gk20a *g) +{ + /* calculations done in units of u32s */ + u32 send_base = sim_send_put_pointer_v(g->sim->send_ring_put) * 2; + u32 dma_offset = send_base + sim_dma_r()/sizeof(u32); + u32 dma_hi_offset = send_base + sim_dma_hi_r()/sizeof(u32); + struct sim_gk20a_linux *sim_linux = + container_of(g->sim, struct sim_gk20a_linux, sim); + + *sim_send_ring_bfr(g, dma_offset*sizeof(u32)) = + sim_dma_target_phys_pci_coherent_f() | + sim_dma_status_valid_f() | + sim_dma_size_4kb_f() | + sim_dma_addr_lo_f(sim_linux->msg_bfr.phys >> PAGE_SHIFT); + + *sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) = + u64_hi32(sim_linux->msg_bfr.phys); + + *sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim->sequence_base++; + + g->sim->send_ring_put = (g->sim->send_ring_put + 2 * sizeof(u32)) % + PAGE_SIZE; + + __cpuc_flush_dcache_area(sim_linux->msg_bfr.kvaddr, PAGE_SIZE); + __cpuc_flush_dcache_area(sim_linux->send_bfr.kvaddr, PAGE_SIZE); + __cpuc_flush_dcache_area(sim_linux->recv_bfr.kvaddr, PAGE_SIZE); + + /* Update the put pointer. This will trap into the host. */ + sim_writel(sim_linux, sim_send_put_r(), g->sim->send_ring_put); + + return 0; +} + +static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset) +{ + struct sim_gk20a_linux *sim_linux = + container_of(g->sim, struct sim_gk20a_linux, sim); + return (u32 *)(sim_linux->recv_bfr.kvaddr + byte_offset); +} + +static int rpc_recv_poll(struct gk20a *g) +{ + u64 recv_phys_addr; + struct sim_gk20a_linux *sim_linux = + container_of(g->sim, struct sim_gk20a_linux, sim); + + /* XXX This read is not required (?) */ + /*pVGpu->recv_ring_get = VGPU_REG_RD32(pGpu, NV_VGPU_RECV_GET);*/ + + /* Poll the recv ring get pointer in an infinite loop*/ + do { + g->sim->recv_ring_put = sim_readl(sim_linux, sim_recv_put_r()); + } while (g->sim->recv_ring_put == g->sim->recv_ring_get); + + /* process all replies */ + while (g->sim->recv_ring_put != g->sim->recv_ring_get) { + /* these are in u32 offsets*/ + u32 dma_lo_offset = + sim_recv_put_pointer_v(g->sim->recv_ring_get)*2 + 0; + u32 dma_hi_offset = dma_lo_offset + 1; + u32 recv_phys_addr_lo = sim_dma_addr_lo_v( + *sim_recv_ring_bfr(g, dma_lo_offset*4)); + u32 recv_phys_addr_hi = sim_dma_hi_addr_v( + *sim_recv_ring_bfr(g, dma_hi_offset*4)); + + recv_phys_addr = (u64)recv_phys_addr_hi << 32 | + (u64)recv_phys_addr_lo << PAGE_SHIFT; + + if (recv_phys_addr != sim_linux->msg_bfr.phys) { + nvgpu_err(g, "%s Error in RPC reply", + __func__); + return -1; + } + + /* Update GET pointer */ + g->sim->recv_ring_get = (g->sim->recv_ring_get + 2*sizeof(u32)) % + PAGE_SIZE; + + __cpuc_flush_dcache_area(sim_linux->msg_bfr.kvaddr, PAGE_SIZE); + __cpuc_flush_dcache_area(sim_linux->send_bfr.kvaddr, PAGE_SIZE); + __cpuc_flush_dcache_area(sim_linux->recv_bfr.kvaddr, PAGE_SIZE); + + sim_writel(sim_linux, sim_recv_get_r(), g->sim->recv_ring_get); + + g->sim->recv_ring_put = sim_readl(sim_linux, sim_recv_put_r()); + } + + return 0; +} + +static int issue_rpc_and_wait(struct gk20a *g) +{ + int err; + + err = rpc_send_message(g); + if (err) { + nvgpu_err(g, "%s failed rpc_send_message", + __func__); + return err; + } + + err = rpc_recv_poll(g); + if (err) { + nvgpu_err(g, "%s failed rpc_recv_poll", + __func__); + return err; + } + + /* Now check if RPC really succeeded */ + if (*sim_msg_hdr(g, sim_msg_result_r()) != sim_msg_result_success_v()) { + nvgpu_err(g, "%s received failed status!", + __func__); + return -(*sim_msg_hdr(g, sim_msg_result_r())); + } + return 0; +} + +static int gk20a_sim_esc_readl(struct gk20a *g, char *path, u32 index, u32 *data) +{ + int err; + size_t pathlen = strlen(path); + u32 data_offset; + + sim_write_hdr(g, sim_msg_function_sim_escape_read_v(), + sim_escape_read_hdr_size()); + *sim_msg_param(g, 0) = index; + *sim_msg_param(g, 4) = sizeof(u32); + data_offset = roundup(0xc + pathlen + 1, sizeof(u32)); + *sim_msg_param(g, 8) = data_offset; + strcpy((char *)sim_msg_param(g, 0xc), path); + + err = issue_rpc_and_wait(g); + + if (!err) + memcpy(data, sim_msg_param(g, data_offset), sizeof(u32)); + return err; +} + + +int gk20a_init_sim_support(struct gk20a *g) +{ + int err = 0; + u64 phys; + struct sim_gk20a_linux *sim_linux = + container_of(g->sim, struct sim_gk20a_linux, sim); + + /* allocate sim event/msg buffers */ + err = alloc_and_kmap_iopage(g, &sim_linux->send_bfr.kvaddr, + &sim_linux->send_bfr.phys, + &sim_linux->send_bfr.page); + + err = err || alloc_and_kmap_iopage(g, &sim_linux->recv_bfr.kvaddr, + &sim_linux->recv_bfr.phys, + &sim_linux->recv_bfr.page); + + err = err || alloc_and_kmap_iopage(g, &sim_linux->msg_bfr.kvaddr, + &sim_linux->msg_bfr.phys, + &sim_linux->msg_bfr.page); + + if (!(sim_linux->send_bfr.kvaddr && sim_linux->recv_bfr.kvaddr && + sim_linux->msg_bfr.kvaddr)) { + nvgpu_err(g, "couldn't allocate all sim buffers"); + goto fail; + } + + /*mark send ring invalid*/ + sim_writel(sim_linux, sim_send_ring_r(), sim_send_ring_status_invalid_f()); + + /*read get pointer and make equal to put*/ + g->sim->send_ring_put = sim_readl(sim_linux, sim_send_get_r()); + sim_writel(sim_linux, sim_send_put_r(), g->sim->send_ring_put); + + /*write send ring address and make it valid*/ + phys = sim_linux->send_bfr.phys; + sim_writel(sim_linux, sim_send_ring_hi_r(), + sim_send_ring_hi_addr_f(u64_hi32(phys))); + sim_writel(sim_linux, sim_send_ring_r(), + sim_send_ring_status_valid_f() | + sim_send_ring_target_phys_pci_coherent_f() | + sim_send_ring_size_4kb_f() | + sim_send_ring_addr_lo_f(phys >> PAGE_SHIFT)); + + /*repeat for recv ring (but swap put,get as roles are opposite) */ + sim_writel(sim_linux, sim_recv_ring_r(), sim_recv_ring_status_invalid_f()); + + /*read put pointer and make equal to get*/ + g->sim->recv_ring_get = sim_readl(sim_linux, sim_recv_put_r()); + sim_writel(sim_linux, sim_recv_get_r(), g->sim->recv_ring_get); + + /*write send ring address and make it valid*/ + phys = sim_linux->recv_bfr.phys; + sim_writel(sim_linux, sim_recv_ring_hi_r(), + sim_recv_ring_hi_addr_f(u64_hi32(phys))); + sim_writel(sim_linux, sim_recv_ring_r(), + sim_recv_ring_status_valid_f() | + sim_recv_ring_target_phys_pci_coherent_f() | + sim_recv_ring_size_4kb_f() | + sim_recv_ring_addr_lo_f(phys >> PAGE_SHIFT)); + + g->sim->remove_support = gk20a_remove_sim_support; + g->sim->esc_readl = gk20a_sim_esc_readl; + return 0; + + fail: + gk20a_free_sim_support(g); + return err; +} \ No newline at end of file diff --git a/drivers/gpu/nvgpu/common/linux/sim_gk20a.h b/drivers/gpu/nvgpu/common/linux/sim_gk20a.h new file mode 100644 index 00000000..c2d975b1 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/sim_gk20a.h @@ -0,0 +1,39 @@ +/* + * drivers/video/tegra/host/gk20a/sim_gk20a.h + * + * GK20A sim support + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __SIM_GK20A_LINUX_H__ +#define __SIM_GK20A_LINUX_H__ + +#include "gk20a/sim_gk20a.h" + +struct sim_gk20a_linux { + struct sim_gk20a sim; + struct resource *reg_mem; + void __iomem *regs; + struct { + struct page *page; + void *kvaddr; + u64 phys; + } send_bfr, recv_bfr, msg_bfr; +}; + +int gk20a_init_sim_support(struct gk20a *g); + +#endif diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index e586913e..8f3900a1 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -1127,7 +1127,7 @@ struct gk20a { struct clk_gk20a clk; struct fifo_gk20a fifo; struct gr_gk20a gr; - struct sim_gk20a sim; + struct sim_gk20a *sim; struct mm_gk20a mm; struct nvgpu_pmu pmu; struct acr_desc acr; diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c index d496b7b9..146b0e22 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c +++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c @@ -41,47 +41,52 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr) g->gr.ctx_vars.dynamic = true; g->gr.netlist = GR_NETLIST_DYNAMIC; + if(!g->sim->esc_readl) { + nvgpu_err(g, "Invalid pointer to query function."); + goto fail; + } + /* query sizes and counts */ - gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_FECS_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_UCODE_INST_FECS_COUNT", 0, &g->gr.ctx_vars.ucode.fecs.inst.count); - gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_FECS_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_UCODE_DATA_FECS_COUNT", 0, &g->gr.ctx_vars.ucode.fecs.data.count); - gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_GPCCS_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_UCODE_INST_GPCCS_COUNT", 0, &g->gr.ctx_vars.ucode.gpccs.inst.count); - gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_GPCCS_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_UCODE_DATA_GPCCS_COUNT", 0, &g->gr.ctx_vars.ucode.gpccs.data.count); - gk20a_sim_esc_readl(g, "GRCTX_ALL_CTX_TOTAL_WORDS", 0, &temp); + g->sim->esc_readl(g, "GRCTX_ALL_CTX_TOTAL_WORDS", 0, &temp); g->gr.ctx_vars.buffer_size = temp << 2; - gk20a_sim_esc_readl(g, "GRCTX_SW_BUNDLE_INIT_SIZE", 0, + g->sim->esc_readl(g, "GRCTX_SW_BUNDLE_INIT_SIZE", 0, &g->gr.ctx_vars.sw_bundle_init.count); - gk20a_sim_esc_readl(g, "GRCTX_SW_METHOD_INIT_SIZE", 0, + g->sim->esc_readl(g, "GRCTX_SW_METHOD_INIT_SIZE", 0, &g->gr.ctx_vars.sw_method_init.count); - gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD_SIZE", 0, + g->sim->esc_readl(g, "GRCTX_SW_CTX_LOAD_SIZE", 0, &g->gr.ctx_vars.sw_ctx_load.count); - gk20a_sim_esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT_SIZE", 0, + g->sim->esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT_SIZE", 0, &g->gr.ctx_vars.sw_veid_bundle_init.count); - gk20a_sim_esc_readl(g, "GRCTX_NONCTXSW_REG_SIZE", 0, + g->sim->esc_readl(g, "GRCTX_NONCTXSW_REG_SIZE", 0, &g->gr.ctx_vars.sw_non_ctx_load.count); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS_COUNT", 0, &g->gr.ctx_vars.ctxsw_regs.sys.count); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC_COUNT", 0, &g->gr.ctx_vars.ctxsw_regs.gpc.count); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC_COUNT", 0, &g->gr.ctx_vars.ctxsw_regs.tpc.count); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC_COUNT", 0, &g->gr.ctx_vars.ctxsw_regs.zcull_gpc.count); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_SYS_COUNT", 0, &g->gr.ctx_vars.ctxsw_regs.pm_sys.count); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_GPC_COUNT", 0, &g->gr.ctx_vars.ctxsw_regs.pm_gpc.count); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_TPC_COUNT", 0, &g->gr.ctx_vars.ctxsw_regs.pm_tpc.count); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COUNT", 0, &g->gr.ctx_vars.ctxsw_regs.ppc.count); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC_COUNT", 0, &g->gr.ctx_vars.ctxsw_regs.etpc.count); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC_COUNT", 0, + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC_COUNT", 0, &g->gr.ctx_vars.ctxsw_regs.ppc.count); err |= !alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.fecs.inst); @@ -107,152 +112,152 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr) goto fail; for (i = 0; i < g->gr.ctx_vars.ucode.fecs.inst.count; i++) - gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_FECS", + g->sim->esc_readl(g, "GRCTX_UCODE_INST_FECS", i, &g->gr.ctx_vars.ucode.fecs.inst.l[i]); for (i = 0; i < g->gr.ctx_vars.ucode.fecs.data.count; i++) - gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_FECS", + g->sim->esc_readl(g, "GRCTX_UCODE_DATA_FECS", i, &g->gr.ctx_vars.ucode.fecs.data.l[i]); for (i = 0; i < g->gr.ctx_vars.ucode.gpccs.inst.count; i++) - gk20a_sim_esc_readl(g, "GRCTX_UCODE_INST_GPCCS", + g->sim->esc_readl(g, "GRCTX_UCODE_INST_GPCCS", i, &g->gr.ctx_vars.ucode.gpccs.inst.l[i]); for (i = 0; i < g->gr.ctx_vars.ucode.gpccs.data.count; i++) - gk20a_sim_esc_readl(g, "GRCTX_UCODE_DATA_GPCCS", + g->sim->esc_readl(g, "GRCTX_UCODE_DATA_GPCCS", i, &g->gr.ctx_vars.ucode.gpccs.data.l[i]); for (i = 0; i < g->gr.ctx_vars.sw_bundle_init.count; i++) { struct av_gk20a *l = g->gr.ctx_vars.sw_bundle_init.l; - gk20a_sim_esc_readl(g, "GRCTX_SW_BUNDLE_INIT:ADDR", + g->sim->esc_readl(g, "GRCTX_SW_BUNDLE_INIT:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_SW_BUNDLE_INIT:VALUE", + g->sim->esc_readl(g, "GRCTX_SW_BUNDLE_INIT:VALUE", i, &l[i].value); } for (i = 0; i < g->gr.ctx_vars.sw_method_init.count; i++) { struct av_gk20a *l = g->gr.ctx_vars.sw_method_init.l; - gk20a_sim_esc_readl(g, "GRCTX_SW_METHOD_INIT:ADDR", + g->sim->esc_readl(g, "GRCTX_SW_METHOD_INIT:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_SW_METHOD_INIT:VALUE", + g->sim->esc_readl(g, "GRCTX_SW_METHOD_INIT:VALUE", i, &l[i].value); } for (i = 0; i < g->gr.ctx_vars.sw_ctx_load.count; i++) { struct aiv_gk20a *l = g->gr.ctx_vars.sw_ctx_load.l; - gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD:ADDR", + g->sim->esc_readl(g, "GRCTX_SW_CTX_LOAD:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD:INDEX", + g->sim->esc_readl(g, "GRCTX_SW_CTX_LOAD:INDEX", i, &l[i].index); - gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD:VALUE", + g->sim->esc_readl(g, "GRCTX_SW_CTX_LOAD:VALUE", i, &l[i].value); } for (i = 0; i < g->gr.ctx_vars.sw_non_ctx_load.count; i++) { struct av_gk20a *l = g->gr.ctx_vars.sw_non_ctx_load.l; - gk20a_sim_esc_readl(g, "GRCTX_NONCTXSW_REG:REG", + g->sim->esc_readl(g, "GRCTX_NONCTXSW_REG:REG", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_NONCTXSW_REG:VALUE", + g->sim->esc_readl(g, "GRCTX_NONCTXSW_REG:VALUE", i, &l[i].value); } for (i = 0; i < g->gr.ctx_vars.sw_veid_bundle_init.count; i++) { struct av_gk20a *l = g->gr.ctx_vars.sw_veid_bundle_init.l; - gk20a_sim_esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:ADDR", + g->sim->esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:VALUE", + g->sim->esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:VALUE", i, &l[i].value); } for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.sys.count; i++) { struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.sys.l; - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS:ADDR", + g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS:INDEX", + g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS:INDEX", i, &l[i].index); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS:VALUE", + g->sim->esc_readl(g, "GRCTX_REG_LIST_SYS:VALUE", i, &l[i].value); } for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.gpc.count; i++) { struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.gpc.l; - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC:ADDR", + g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC:INDEX", + g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC:INDEX", i, &l[i].index); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_GPC:VALUE", + g->sim->esc_readl(g, "GRCTX_REG_LIST_GPC:VALUE", i, &l[i].value); } for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.tpc.count; i++) { struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.tpc.l; - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC:ADDR", + g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC:INDEX", + g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC:INDEX", i, &l[i].index); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_TPC:VALUE", + g->sim->esc_readl(g, "GRCTX_REG_LIST_TPC:VALUE", i, &l[i].value); } for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.ppc.count; i++) { struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.ppc.l; - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC:ADDR", + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC:INDEX", + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC:INDEX", i, &l[i].index); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PPC:VALUE", + g->sim->esc_readl(g, "GRCTX_REG_LIST_PPC:VALUE", i, &l[i].value); } for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.zcull_gpc.count; i++) { struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.zcull_gpc.l; - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:ADDR", + g->sim->esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:INDEX", + g->sim->esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:INDEX", i, &l[i].index); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:VALUE", + g->sim->esc_readl(g, "GRCTX_REG_LIST_ZCULL_GPC:VALUE", i, &l[i].value); } for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_sys.count; i++) { struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_sys.l; - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS:ADDR", + g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_SYS:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS:INDEX", + g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_SYS:INDEX", i, &l[i].index); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_SYS:VALUE", + g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_SYS:VALUE", i, &l[i].value); } for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_gpc.count; i++) { struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_gpc.l; - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC:ADDR", + g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_GPC:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC:INDEX", + g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_GPC:INDEX", i, &l[i].index); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_GPC:VALUE", + g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_GPC:VALUE", i, &l[i].value); } for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.pm_tpc.count; i++) { struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.pm_tpc.l; - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC:ADDR", + g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_TPC:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC:INDEX", + g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_TPC:INDEX", i, &l[i].index); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC:VALUE", + g->sim->esc_readl(g, "GRCTX_REG_LIST_PM_TPC:VALUE", i, &l[i].value); } gk20a_dbg(gpu_dbg_info | gpu_dbg_fn, "query GRCTX_REG_LIST_ETPC"); for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.etpc.count; i++) { struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.etpc.l; - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC:ADDR", + g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC:ADDR", i, &l[i].addr); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC:INDEX", + g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC:INDEX", i, &l[i].index); - gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC:VALUE", + g->sim->esc_readl(g, "GRCTX_REG_LIST_ETPC:VALUE", i, &l[i].value); gk20a_dbg(gpu_dbg_info | gpu_dbg_fn, "addr:0x%#08x index:0x%08x value:0x%08x", @@ -261,7 +266,7 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr) g->gr.ctx_vars.valid = true; - gk20a_sim_esc_readl(g, "GRCTX_GEN_CTX_REGS_BASE_INDEX", 0, + g->sim->esc_readl(g, "GRCTX_GEN_CTX_REGS_BASE_INDEX", 0, &g->gr.ctx_vars.regs_base_index); gk20a_dbg(gpu_dbg_info | gpu_dbg_fn, "finished querying grctx info from chiplib"); diff --git a/drivers/gpu/nvgpu/gk20a/sim_gk20a.c b/drivers/gpu/nvgpu/gk20a/sim_gk20a.c deleted file mode 100644 index ab064710..00000000 --- a/drivers/gpu/nvgpu/gk20a/sim_gk20a.c +++ /dev/null @@ -1,343 +0,0 @@ -/* - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#include -#include -#include - -#include -#include - -#include "gk20a.h" - -#include - -static inline void sim_writel(struct gk20a *g, u32 r, u32 v) -{ - writel(v, g->sim.regs + r); -} - -static inline u32 sim_readl(struct gk20a *g, u32 r) -{ - return readl(g->sim.regs + r); -} - -static void kunmap_and_free_iopage(void **kvaddr, struct page **page) -{ - if (*kvaddr) { - kunmap(*kvaddr); - *kvaddr = NULL; - } - if (*page) { - __free_page(*page); - *page = NULL; - } -} - -static void gk20a_free_sim_support(struct gk20a *g) -{ - /* free sim mappings, bfrs */ - kunmap_and_free_iopage(&g->sim.send_bfr.kvaddr, - &g->sim.send_bfr.page); - - kunmap_and_free_iopage(&g->sim.recv_bfr.kvaddr, - &g->sim.recv_bfr.page); - - kunmap_and_free_iopage(&g->sim.msg_bfr.kvaddr, - &g->sim.msg_bfr.page); -} - -static void gk20a_remove_sim_support(struct sim_gk20a *s) -{ - struct gk20a *g = s->g; - if (g->sim.regs) - sim_writel(g, sim_config_r(), sim_config_mode_disabled_v()); - gk20a_free_sim_support(g); -} - -static int alloc_and_kmap_iopage(struct gk20a *g, - void **kvaddr, - u64 *phys, - struct page **page) -{ - int err = 0; - *page = alloc_page(GFP_KERNEL); - - if (!*page) { - err = -ENOMEM; - nvgpu_err(g, "couldn't allocate io page"); - goto fail; - } - - *kvaddr = kmap(*page); - if (!*kvaddr) { - err = -ENOMEM; - nvgpu_err(g, "couldn't kmap io page"); - goto fail; - } - *phys = page_to_phys(*page); - return 0; - - fail: - kunmap_and_free_iopage(kvaddr, page); - return err; - -} - -int gk20a_init_sim_support(struct gk20a *g) -{ - int err = 0; - u64 phys; - - /* allocate sim event/msg buffers */ - err = alloc_and_kmap_iopage(g, &g->sim.send_bfr.kvaddr, - &g->sim.send_bfr.phys, - &g->sim.send_bfr.page); - - err = err || alloc_and_kmap_iopage(g, &g->sim.recv_bfr.kvaddr, - &g->sim.recv_bfr.phys, - &g->sim.recv_bfr.page); - - err = err || alloc_and_kmap_iopage(g, &g->sim.msg_bfr.kvaddr, - &g->sim.msg_bfr.phys, - &g->sim.msg_bfr.page); - - if (!(g->sim.send_bfr.kvaddr && g->sim.recv_bfr.kvaddr && - g->sim.msg_bfr.kvaddr)) { - nvgpu_err(g, "couldn't allocate all sim buffers"); - goto fail; - } - - /*mark send ring invalid*/ - sim_writel(g, sim_send_ring_r(), sim_send_ring_status_invalid_f()); - - /*read get pointer and make equal to put*/ - g->sim.send_ring_put = sim_readl(g, sim_send_get_r()); - sim_writel(g, sim_send_put_r(), g->sim.send_ring_put); - - /*write send ring address and make it valid*/ - phys = g->sim.send_bfr.phys; - sim_writel(g, sim_send_ring_hi_r(), - sim_send_ring_hi_addr_f(u64_hi32(phys))); - sim_writel(g, sim_send_ring_r(), - sim_send_ring_status_valid_f() | - sim_send_ring_target_phys_pci_coherent_f() | - sim_send_ring_size_4kb_f() | - sim_send_ring_addr_lo_f(phys >> PAGE_SHIFT)); - - /*repeat for recv ring (but swap put,get as roles are opposite) */ - sim_writel(g, sim_recv_ring_r(), sim_recv_ring_status_invalid_f()); - - /*read put pointer and make equal to get*/ - g->sim.recv_ring_get = sim_readl(g, sim_recv_put_r()); - sim_writel(g, sim_recv_get_r(), g->sim.recv_ring_get); - - /*write send ring address and make it valid*/ - phys = g->sim.recv_bfr.phys; - sim_writel(g, sim_recv_ring_hi_r(), - sim_recv_ring_hi_addr_f(u64_hi32(phys))); - sim_writel(g, sim_recv_ring_r(), - sim_recv_ring_status_valid_f() | - sim_recv_ring_target_phys_pci_coherent_f() | - sim_recv_ring_size_4kb_f() | - sim_recv_ring_addr_lo_f(phys >> PAGE_SHIFT)); - - g->sim.remove_support = gk20a_remove_sim_support; - return 0; - - fail: - gk20a_free_sim_support(g); - return err; -} - -static inline u32 sim_msg_header_size(void) -{ - return 24;/*TBD: fix the header to gt this from NV_VGPU_MSG_HEADER*/ -} - -static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset) -{ - return (u32 *)(g->sim.msg_bfr.kvaddr + byte_offset); -} - -static inline u32 *sim_msg_hdr(struct gk20a *g, u32 byte_offset) -{ - return sim_msg_bfr(g, byte_offset); /*starts at 0*/ -} - -static inline u32 *sim_msg_param(struct gk20a *g, u32 byte_offset) -{ - /*starts after msg header/cmn*/ - return sim_msg_bfr(g, byte_offset + sim_msg_header_size()); -} - -static inline void sim_write_hdr(struct gk20a *g, u32 func, u32 size) -{ - /*memset(g->sim.msg_bfr.kvaddr,0,min(PAGE_SIZE,size));*/ - *sim_msg_hdr(g, sim_msg_signature_r()) = sim_msg_signature_valid_v(); - *sim_msg_hdr(g, sim_msg_result_r()) = sim_msg_result_rpc_pending_v(); - *sim_msg_hdr(g, sim_msg_spare_r()) = sim_msg_spare__init_v(); - *sim_msg_hdr(g, sim_msg_function_r()) = func; - *sim_msg_hdr(g, sim_msg_length_r()) = size + sim_msg_header_size(); -} - -static inline u32 sim_escape_read_hdr_size(void) -{ - return 12; /*TBD: fix NV_VGPU_SIM_ESCAPE_READ_HEADER*/ -} - -static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset) -{ - return (u32 *)(g->sim.send_bfr.kvaddr + byte_offset); -} - -static int rpc_send_message(struct gk20a *g) -{ - /* calculations done in units of u32s */ - u32 send_base = sim_send_put_pointer_v(g->sim.send_ring_put) * 2; - u32 dma_offset = send_base + sim_dma_r()/sizeof(u32); - u32 dma_hi_offset = send_base + sim_dma_hi_r()/sizeof(u32); - - *sim_send_ring_bfr(g, dma_offset*sizeof(u32)) = - sim_dma_target_phys_pci_coherent_f() | - sim_dma_status_valid_f() | - sim_dma_size_4kb_f() | - sim_dma_addr_lo_f(g->sim.msg_bfr.phys >> PAGE_SHIFT); - - *sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) = - u64_hi32(g->sim.msg_bfr.phys); - - *sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim.sequence_base++; - - g->sim.send_ring_put = (g->sim.send_ring_put + 2 * sizeof(u32)) % - PAGE_SIZE; - - __cpuc_flush_dcache_area(g->sim.msg_bfr.kvaddr, PAGE_SIZE); - __cpuc_flush_dcache_area(g->sim.send_bfr.kvaddr, PAGE_SIZE); - __cpuc_flush_dcache_area(g->sim.recv_bfr.kvaddr, PAGE_SIZE); - - /* Update the put pointer. This will trap into the host. */ - sim_writel(g, sim_send_put_r(), g->sim.send_ring_put); - - return 0; -} - -static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset) -{ - return (u32 *)(g->sim.recv_bfr.kvaddr + byte_offset); -} - -static int rpc_recv_poll(struct gk20a *g) -{ - u64 recv_phys_addr; - - /* XXX This read is not required (?) */ - /*pVGpu->recv_ring_get = VGPU_REG_RD32(pGpu, NV_VGPU_RECV_GET);*/ - - /* Poll the recv ring get pointer in an infinite loop*/ - do { - g->sim.recv_ring_put = sim_readl(g, sim_recv_put_r()); - } while (g->sim.recv_ring_put == g->sim.recv_ring_get); - - /* process all replies */ - while (g->sim.recv_ring_put != g->sim.recv_ring_get) { - /* these are in u32 offsets*/ - u32 dma_lo_offset = - sim_recv_put_pointer_v(g->sim.recv_ring_get)*2 + 0; - u32 dma_hi_offset = dma_lo_offset + 1; - u32 recv_phys_addr_lo = sim_dma_addr_lo_v( - *sim_recv_ring_bfr(g, dma_lo_offset*4)); - u32 recv_phys_addr_hi = sim_dma_hi_addr_v( - *sim_recv_ring_bfr(g, dma_hi_offset*4)); - - recv_phys_addr = (u64)recv_phys_addr_hi << 32 | - (u64)recv_phys_addr_lo << PAGE_SHIFT; - - if (recv_phys_addr != g->sim.msg_bfr.phys) { - nvgpu_err(g, "%s Error in RPC reply", - __func__); - return -1; - } - - /* Update GET pointer */ - g->sim.recv_ring_get = (g->sim.recv_ring_get + 2*sizeof(u32)) % - PAGE_SIZE; - - __cpuc_flush_dcache_area(g->sim.msg_bfr.kvaddr, PAGE_SIZE); - __cpuc_flush_dcache_area(g->sim.send_bfr.kvaddr, PAGE_SIZE); - __cpuc_flush_dcache_area(g->sim.recv_bfr.kvaddr, PAGE_SIZE); - - sim_writel(g, sim_recv_get_r(), g->sim.recv_ring_get); - - g->sim.recv_ring_put = sim_readl(g, sim_recv_put_r()); - } - - return 0; -} - -static int issue_rpc_and_wait(struct gk20a *g) -{ - int err; - - err = rpc_send_message(g); - if (err) { - nvgpu_err(g, "%s failed rpc_send_message", - __func__); - return err; - } - - err = rpc_recv_poll(g); - if (err) { - nvgpu_err(g, "%s failed rpc_recv_poll", - __func__); - return err; - } - - /* Now check if RPC really succeeded */ - if (*sim_msg_hdr(g, sim_msg_result_r()) != sim_msg_result_success_v()) { - nvgpu_err(g, "%s received failed status!", - __func__); - return -(*sim_msg_hdr(g, sim_msg_result_r())); - } - return 0; -} - -int gk20a_sim_esc_readl(struct gk20a *g, char *path, u32 index, u32 *data) -{ - int err; - size_t pathlen = strlen(path); - u32 data_offset; - - sim_write_hdr(g, sim_msg_function_sim_escape_read_v(), - sim_escape_read_hdr_size()); - *sim_msg_param(g, 0) = index; - *sim_msg_param(g, 4) = sizeof(u32); - data_offset = roundup(0xc + pathlen + 1, sizeof(u32)); - *sim_msg_param(g, 8) = data_offset; - strcpy((char *)sim_msg_param(g, 0xc), path); - - err = issue_rpc_and_wait(g); - - if (!err) - memcpy(data, sim_msg_param(g, data_offset), sizeof(u32)); - return err; -} diff --git a/drivers/gpu/nvgpu/gk20a/sim_gk20a.h b/drivers/gpu/nvgpu/gk20a/sim_gk20a.h index 44378e7a..8f23abd8 100644 --- a/drivers/gpu/nvgpu/gk20a/sim_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/sim_gk20a.h @@ -3,7 +3,7 @@ * * GK20A sim support * - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2013-2017, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -27,25 +27,16 @@ #define __SIM_GK20A_H__ struct gk20a; -struct platform_device; struct sim_gk20a { struct gk20a *g; - struct resource *reg_mem; - void __iomem *regs; - struct { - struct page *page; - void *kvaddr; - u64 phys; - } send_bfr, recv_bfr, msg_bfr; u32 send_ring_put; u32 recv_ring_get; u32 recv_ring_put; u32 sequence_base; void (*remove_support)(struct sim_gk20a *); + int (*esc_readl)( + struct gk20a *g, char *path, u32 index, u32 *data); }; -int gk20a_init_sim_support(struct gk20a *g); -int gk20a_sim_esc_readl(struct gk20a *g, char *path, u32 index, u32 *data); - #endif /*__SIM_GK20A_H__*/ -- cgit v1.2.2