From 2d23236ae26ec6dcbbc934bb372fe56ef839bb80 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 11 Nov 2014 11:13:11 +0200 Subject: gpu: nvgpu: Use queried interrupt ids Change-Id: I258b54447d09b32adc076de50997d792f0567af5 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/601019 Reviewed-by: Automatic_Commit_Validation_User --- drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h | 8 ++++++++ drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 20 ++++++++++++-------- 2 files changed, 20 insertions(+), 8 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h index ca6457c7..0982bc09 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h @@ -102,6 +102,14 @@ static inline u32 top_device_info_runlist_enum_v(u32 r) { return (r >> 21) & 0xf; } +static inline u32 top_device_info_intr_enum_v(u32 r) +{ + return (r >> 15) & 0x1f; +} +static inline u32 top_device_info_reset_enum_v(u32 r) +{ + return (r >> 9) & 0x1f; +} static inline u32 top_device_info_type_enum_v(u32 r) { return (r >> 2) & 0x1fffffff; diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 4f7ab698..3fae4ea3 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c @@ -21,17 +21,19 @@ void mc_gp10b_intr_enable(struct gk20a *g) { + u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); + gk20a_writel(g, mc_intr_en_clear_r(0), 0xffffffff); gk20a_writel(g, mc_intr_en_set_r(0), mc_intr_pfifo_pending_f() - | mc_intr_pgraph_pending_f()); + | eng_intr_mask); gk20a_writel(g, mc_intr_en_clear_r(1), 0xffffffff); gk20a_writel(g, mc_intr_en_set_r(1), mc_intr_pfifo_pending_f() - | mc_intr_pgraph_pending_f() | mc_intr_priv_ring_pending_f() | mc_intr_ltc_pending_f() - | mc_intr_pbus_pending_f()); + | mc_intr_pbus_pending_f() + | eng_intr_mask); } irqreturn_t mc_gp10b_isr_stall(struct gk20a *g) @@ -71,6 +73,7 @@ irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g) irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) { u32 mc_intr_0; + u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); @@ -78,7 +81,7 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); - if (mc_intr_0 & mc_intr_pgraph_pending_f()) + if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); if (mc_intr_0 & mc_intr_pfifo_pending_f()) gk20a_fifo_isr(g); @@ -93,7 +96,7 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) gk20a_writel(g, mc_intr_en_set_r(0), mc_intr_pfifo_pending_f() - | mc_intr_pgraph_pending_f()); + | eng_intr_mask); return IRQ_HANDLED; } @@ -101,6 +104,7 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) { u32 mc_intr_1; + u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); @@ -110,15 +114,15 @@ irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) if (mc_intr_1 & mc_intr_pfifo_pending_f()) gk20a_fifo_nonstall_isr(g); - if (mc_intr_1 & mc_intr_pgraph_pending_f()) + if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) gk20a_gr_nonstall_isr(g); gk20a_writel(g, mc_intr_en_set_r(1), mc_intr_pfifo_pending_f() - | mc_intr_pgraph_pending_f() | mc_intr_priv_ring_pending_f() | mc_intr_ltc_pending_f() - | mc_intr_pbus_pending_f()); + | mc_intr_pbus_pending_f() + | eng_intr_mask); return IRQ_HANDLED; } -- cgit v1.2.2