From 24f47f0de8bd5f10bdcd505237ff33baf6fe80eb Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Mon, 17 Sep 2018 14:29:41 +0530 Subject: gpu: nvgpu: SEC2 RTOS support s/w init -Created struct nvgpu_sec2 to hold members related to SEC2-RTOS ucode support in header file sec2.h -Created nvgpu_sec2 variable under struct gk20a. -Created NVGPU_SUPPORT_SEC2_RTOS enable flag to enable SEC2 RTOS support. -Defined method nvgpu_init_sec2_support() to init SEC2 RTOS support by performing s/w setup like mutex-init, sequence-init & add support for remove_support. -Defined method nvgpu_sec2_destroy() to deinit SEC2 RTOS support. -Added nvgpu_init_sec2_support()/nvgpu_sec2_destroy() as part gk20a_finalize_poweron()/gk20a_prepare_poweroff() sequence based on NVGPU_SUPPORT_SEC2_RTOS enable flag -Assigned g->sec2->flcn to point to g->sec2_flcn to access falcon. -Made Makefile changes to include sec2.c to build JIRA NVGPUT-80 Change-Id: Icdc8c25994e305427ad465a5a20e9ce533759a9e Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1791955 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/Makefile.sources | 1 + drivers/gpu/nvgpu/common/falcon/falcon.c | 2 + drivers/gpu/nvgpu/common/sec2/sec2.c | 131 ++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gk20a/gk20a.c | 12 +++ drivers/gpu/nvgpu/include/nvgpu/enabled.h | 5 +- drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 2 + drivers/gpu/nvgpu/include/nvgpu/sec2.h | 97 ++++++++++++++++++++++ 8 files changed, 250 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/nvgpu/common/sec2/sec2.c create mode 100644 drivers/gpu/nvgpu/include/nvgpu/sec2.h (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index d704de83..e0fd70e6 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -215,6 +215,7 @@ nvgpu-y += \ common/ltc/ltc_gm20b.o \ common/ltc/ltc_gp10b.o \ common/ltc/ltc_gv11b.o \ + common/sec2/sec2.o \ common/io_common.o \ common/clock_gating/gm20b_gating_reglist.o \ common/clock_gating/gp106_gating_reglist.o \ diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index cc612e07..8f7cdcf9 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources @@ -100,6 +100,7 @@ srcs := os/posix/nvgpu.c \ common/pmu/pmu_pg.c \ common/pmu/pmu_perfmon.c \ common/pmu/pmu_debug.c \ + common/sec2/sec2.c \ common/ptimer/ptimer.c \ common/sync/channel_sync.c \ common/clock_gating/gm20b_gating_reglist.c \ diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c index b1d6558a..451b8450 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon.c @@ -440,6 +440,8 @@ int nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id) case FALCON_ID_SEC2: flcn = &g->sec2_flcn; flcn->flcn_id = flcn_id; + g->sec2.flcn = &g->sec2_flcn; + g->sec2.g = g; break; case FALCON_ID_FECS: flcn = &g->fecs_flcn; diff --git a/drivers/gpu/nvgpu/common/sec2/sec2.c b/drivers/gpu/nvgpu/common/sec2/sec2.c new file mode 100644 index 00000000..842d39f9 --- /dev/null +++ b/drivers/gpu/nvgpu/common/sec2/sec2.c @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include + +static void sec2_seq_init(struct nvgpu_sec2 *sec2) +{ + u32 i = 0; + + nvgpu_log_fn(sec2->g, " "); + + memset(sec2->seq, 0, + sizeof(struct sec2_sequence) * SEC2_MAX_NUM_SEQUENCES); + + memset(sec2->sec2_seq_tbl, 0, sizeof(sec2->sec2_seq_tbl)); + + for (i = 0; i < SEC2_MAX_NUM_SEQUENCES; i++) { + sec2->seq[i].id = (u8)i; + } +} + +static void nvgpu_remove_sec2_support(struct nvgpu_sec2 *sec2) +{ + struct gk20a *g = sec2->g; + + nvgpu_log_fn(g, " "); + + nvgpu_kfree(g, sec2->seq); + nvgpu_mutex_destroy(&sec2->sec2_seq_lock); + nvgpu_mutex_destroy(&sec2->isr_mutex); +} + +static int nvgpu_init_sec2_setup_sw(struct gk20a *g, struct nvgpu_sec2 *sec2) +{ + int err = 0; + + nvgpu_log_fn(g, " "); + + sec2->seq = nvgpu_kzalloc(g, SEC2_MAX_NUM_SEQUENCES * + sizeof(struct sec2_sequence)); + if (sec2->seq == NULL) { + err = -ENOMEM; + goto exit; + } + + err = nvgpu_mutex_init(&sec2->sec2_seq_lock); + if (err != 0) { + goto free_seq_alloc; + } + + sec2_seq_init(sec2); + + err = nvgpu_mutex_init(&sec2->isr_mutex); + if (err != 0) { + goto free_seq_mutex; + } + + sec2->remove_support = nvgpu_remove_sec2_support; + + goto exit; + +free_seq_mutex: + nvgpu_mutex_destroy(&sec2->sec2_seq_lock); +free_seq_alloc: + nvgpu_kfree(g, sec2->seq); + +exit: + return err; +} + +int nvgpu_init_sec2_support(struct gk20a *g) +{ + struct nvgpu_sec2 *sec2 = &g->sec2; + int err = 0; + + nvgpu_log_fn(g, " "); + + err = nvgpu_init_sec2_setup_sw(g, sec2); + if (err != 0) { + goto exit; + } + + /* TBD - call SEC2 in secure mode to boot RTOS */ + +exit: + return err; +} + +int nvgpu_sec2_destroy(struct gk20a *g) +{ + struct nvgpu_sec2 *sec2 = &g->sec2; + u32 i = 0; + + nvgpu_log_fn(g, " "); + + nvgpu_mutex_acquire(&sec2->isr_mutex); + sec2->isr_enabled = false; + nvgpu_mutex_release(&sec2->isr_mutex); + + for (i = 0; i < SEC2_QUEUE_NUM; i++) { + nvgpu_flcn_queue_free(sec2->flcn, &sec2->queue[i]); + } + + sec2->sec2_ready = false; + + return 0; +} diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index 39318f66..7855493d 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c @@ -93,6 +93,10 @@ int gk20a_prepare_poweroff(struct gk20a *g) ret |= nvgpu_pmu_destroy(g); } + if (nvgpu_is_enabled(g, NVGPU_SUPPORT_SEC2_RTOS)) { + ret |= nvgpu_sec2_destroy(g); + } + ret |= gk20a_gr_suspend(g); ret |= nvgpu_mm_suspend(g); ret |= gk20a_fifo_suspend(g); @@ -313,6 +317,14 @@ int gk20a_finalize_poweron(struct gk20a *g) } } + if (nvgpu_is_enabled(g, NVGPU_SUPPORT_SEC2_RTOS)) { + err = nvgpu_init_sec2_support(g); + if (err != 0) { + nvgpu_err(g, "failed to init sec2"); + goto done; + } + } + if (g->ops.pmu.is_pmu_supported(g)) { err = nvgpu_init_pmu_support(g); if (err) { diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h index ccf60546..074be0c3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h @@ -170,10 +170,13 @@ struct gk20a; /* Multiple WPR support */ #define NVGPU_SUPPORT_MULTIPLE_WPR 68 +/* SEC2 RTOS support*/ +#define NVGPU_SUPPORT_SEC2_RTOS 69 + /* * Must be greater than the largest bit offset in the above list. */ -#define NVGPU_MAX_ENABLED_BITS 69 +#define NVGPU_MAX_ENABLED_BITS 70 /** * nvgpu_is_enabled - Check if the passed flag is enabled. diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 104d463b..bb46d85c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -67,6 +67,7 @@ struct nvgpu_gpfifo_args; #include #include #include +#include #include "gk20a/clk_gk20a.h" #include "gk20a/ce2_gk20a.h" @@ -1450,6 +1451,7 @@ struct gk20a { struct perf_pmupstate perf_pmu; struct pmgr_pmupstate pmgr_pmu; struct therm_pmupstate therm_pmu; + struct nvgpu_sec2 sec2; #ifdef CONFIG_DEBUG_FS struct railgate_stats pstats; diff --git a/drivers/gpu/nvgpu/include/nvgpu/sec2.h b/drivers/gpu/nvgpu/include/nvgpu/sec2.h new file mode 100644 index 00000000..7c755841 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/sec2.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef NVGPU_SEC2_H +#define NVGPU_SEC2_H + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define NVGPU_SEC2_TRACE_BUFSIZE (32U*1024U) + +#define SEC2_MAX_NUM_SEQUENCES (256U) +#define SEC2_SEQ_BIT_SHIFT (5U) +#define SEC2_SEQ_TBL_SIZE \ + (SEC2_MAX_NUM_SEQUENCES >> SEC2_SEQ_BIT_SHIFT) + +#define SEC2_INVALID_SEQ_DESC (~0U) + +enum { + SEC2_SEQ_STATE_FREE = 0U, + SEC2_SEQ_STATE_PENDING, + SEC2_SEQ_STATE_USED, + SEC2_SEQ_STATE_CANCELLED +}; + +typedef void (*sec2_callback)(struct gk20a *, struct nv_flcn_msg_sec2 *, + void *, u32, u32); + +struct sec2_sequence { + u8 id; + u32 state; + u32 desc; + struct nv_flcn_msg_sec2 *msg; + u8 *out_payload; + sec2_callback callback; + void *cb_params; +}; + +struct nvgpu_sec2 { + struct gk20a *g; + struct nvgpu_falcon *flcn; + u32 falcon_id; + + struct nvgpu_falcon_queue queue[SEC2_QUEUE_NUM]; + + struct sec2_sequence *seq; + unsigned long sec2_seq_tbl[SEC2_SEQ_TBL_SIZE]; + u32 next_seq_desc; + struct nvgpu_mutex sec2_seq_lock; + + bool isr_enabled; + struct nvgpu_mutex isr_mutex; + + struct nvgpu_allocator dmem; + + /* set to true once init received */ + bool sec2_ready; + + struct nvgpu_mem trace_buf; + + void (*remove_support)(struct nvgpu_sec2 *sec2); + + u32 command_ack; +}; + +/* sec2 init */ +int nvgpu_init_sec2_support(struct gk20a *g); +int nvgpu_sec2_destroy(struct gk20a *g); + +#endif /* NVGPU_SEC2_H */ -- cgit v1.2.2