From 2328d305b7c9437aa467922086b9fcfc0a4169ba Mon Sep 17 00:00:00 2001 From: Amulya Date: Mon, 6 Aug 2018 10:37:32 +0530 Subject: gpu: nvgpu: MISRA 10.4 enum fixes MISRA rule-10.4 only allows arithmetic conversions on operands of the same essential type category. Fix violations where an arithmetic conversion is performed on enum and non-enum types. JIRA NVGPU-993 Change-Id: I5391bb670d68982e0b5af6600995f70fe0cb2ad3 Signed-off-by: Amulya Reviewed-on: https://git-master.nvidia.com/r/1792852 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/falcon/falcon.c | 2 +- drivers/gpu/nvgpu/gk20a/flcn_gk20a.c | 5 +++-- drivers/gpu/nvgpu/gk20a/gk20a.h | 9 +++++---- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 10 +++++----- drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 6 ++++-- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 9 +++++---- drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 7 ++++--- 7 files changed, 27 insertions(+), 21 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c index 048bb760..41dca0cd 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon.c @@ -255,7 +255,7 @@ int nvgpu_flcn_copy_to_imem(struct nvgpu_falcon *flcn, } static void nvgpu_flcn_print_mem(struct nvgpu_falcon *flcn, u32 src, - u32 size, u32 mem_type) + u32 size, enum flcn_mem_type mem_type) { u32 buff[64] = {0}; u32 total_block_read = 0; diff --git a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c index 98fdb8c2..92f88333 100644 --- a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c @@ -139,7 +139,8 @@ static bool gk20a_is_falcon_scrubbing_done(struct nvgpu_falcon *flcn) return status; } -static u32 gk20a_falcon_get_mem_size(struct nvgpu_falcon *flcn, u32 mem_type) +static u32 gk20a_falcon_get_mem_size(struct nvgpu_falcon *flcn, + enum flcn_mem_type mem_type) { struct gk20a *g = flcn->g; u32 mem_size = 0; @@ -157,7 +158,7 @@ static u32 gk20a_falcon_get_mem_size(struct nvgpu_falcon *flcn, u32 mem_type) } static int flcn_mem_overflow_check(struct nvgpu_falcon *flcn, - u32 offset, u32 size, u32 mem_type) + u32 offset, u32 size, enum flcn_mem_type mem_type) { struct gk20a *g = flcn->g; u32 mem_size = 0; diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index c29c03f0..204fd371 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -250,7 +250,7 @@ struct gpu_ops { int (*get_zcull_info)(struct gk20a *g, struct gr_gk20a *gr, struct gr_zcull_info *zcull_params); int (*decode_egpc_addr)(struct gk20a *g, - u32 addr, int *addr_type, + u32 addr, enum ctxsw_addr_type *addr_type, u32 *gpc_num, u32 *tpc_num, u32 *broadcast_flags); void (*egpc_etpc_priv_addr_table)(struct gk20a *g, u32 addr, u32 gpc, u32 tpc, u32 broadcast_flags, @@ -473,7 +473,7 @@ struct gpu_ops { u32 *count, u32 *offset, u32 max_cnt, u32 base, u32 mask); int (*decode_priv_addr)(struct gk20a *g, u32 addr, - int *addr_type, + enum ctxsw_addr_type *addr_type, u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num, u32 *broadcast_flags); @@ -495,8 +495,9 @@ struct gpu_ops { struct channel_gk20a *c, bool patch); u32 (*get_nonpes_aware_tpc)(struct gk20a *g, u32 gpc, u32 tpc); int (*get_offset_in_gpccs_segment)(struct gk20a *g, - int addr_type, u32 num_tpcs, u32 num_ppcs, - u32 reg_list_ppc_count, u32 *__offset_in_segment); + enum ctxsw_addr_type addr_type, u32 num_tpcs, + u32 num_ppcs, u32 reg_list_ppc_count, + u32 *__offset_in_segment); } gr; struct { void (*init_hw)(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index bedd39eb..5539b801 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -6274,7 +6274,7 @@ static int gr_gk20a_find_priv_offset_in_pm_buffer(struct gk20a *g, /* This function will decode a priv address and return the partition type and numbers. */ int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr, - int *addr_type, /* enum ctxsw_addr_type */ + enum ctxsw_addr_type *addr_type, u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num, u32 *broadcast_flags) { @@ -6391,7 +6391,7 @@ int gr_gk20a_create_priv_addr_table(struct gk20a *g, u32 *priv_addr_table, u32 *num_registers) { - int addr_type; /*enum ctxsw_addr_type */ + enum ctxsw_addr_type addr_type; u32 gpc_num, tpc_num, ppc_num, be_num; u32 priv_addr, gpc_addr; u32 broadcast_flags; @@ -7036,7 +7036,7 @@ static int gr_gk20a_find_priv_offset_in_ext_buffer(struct gk20a *g, static int gr_gk20a_process_context_buffer_priv_segment(struct gk20a *g, - int addr_type,/* enum ctxsw_addr_type */ + enum ctxsw_addr_type addr_type, u32 pri_addr, u32 gpc_num, u32 num_tpcs, u32 num_ppcs, u32 ppc_mask, @@ -7214,7 +7214,7 @@ static int gr_gk20a_determine_ppc_configuration(struct gk20a *g, } int gr_gk20a_get_offset_in_gpccs_segment(struct gk20a *g, - int addr_type, + enum ctxsw_addr_type addr_type, u32 num_tpcs, u32 num_ppcs, u32 reg_list_ppc_count, @@ -7289,7 +7289,7 @@ static int gr_gk20a_find_priv_offset_in_buffer(struct gk20a *g, { u32 i, data32; int err; - int addr_type; /*enum ctxsw_addr_type */ + enum ctxsw_addr_type addr_type; u32 broadcast_flags; u32 gpc_num, tpc_num, ppc_num, be_num; u32 num_gpcs, num_tpcs, num_ppcs; diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 804e0e25..2b31b6b6 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h @@ -70,6 +70,8 @@ struct tsg_gk20a; struct channel_gk20a; struct nvgpu_warpstate; +enum ctxsw_addr_type; + enum /* global_ctx_buffer */ { CIRCULAR = 0, PAGEPOOL = 1, @@ -842,7 +844,7 @@ int gr_gk20a_add_ctxsw_reg_perf_pma(struct ctxsw_buf_offset_map_entry *map, u32 *count, u32 *offset, u32 max_cnt, u32 base, u32 mask); int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr, - int *addr_type, + enum ctxsw_addr_type *addr_type, u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num, u32 *broadcast_flags); int gr_gk20a_split_ppc_broadcast_addr(struct gk20a *g, u32 addr, @@ -856,7 +858,7 @@ void gr_gk20a_split_fbpa_broadcast_addr(struct gk20a *g, u32 addr, u32 num_fbpas, u32 *priv_addr_table, u32 *t); int gr_gk20a_get_offset_in_gpccs_segment(struct gk20a *g, - int addr_type, u32 num_tpcs, u32 num_ppcs, + enum ctxsw_addr_type addr_type, u32 num_tpcs, u32 num_ppcs, u32 reg_list_ppc_count, u32 *__offset_in_segment); void gk20a_gr_destroy_ctx_buffer(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 4327e087..058a21e5 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -4138,8 +4138,9 @@ void gv11b_gr_get_egpc_etpc_num(struct gk20a *g, u32 addr, "egpc_num = %d etpc_num = %d", *egpc_num, *etpc_num); } -int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, int *addr_type, - u32 *gpc_num, u32 *tpc_num, u32 *broadcast_flags) +int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, + enum ctxsw_addr_type *addr_type, u32 *gpc_num, u32 *tpc_num, + u32 *broadcast_flags) { u32 gpc_addr; u32 tpc_addr; @@ -4702,7 +4703,7 @@ int gr_gv11b_handle_ssync_hww(struct gk20a *g) * type and numbers */ int gr_gv11b_decode_priv_addr(struct gk20a *g, u32 addr, - int *addr_type, /* enum ctxsw_addr_type */ + enum ctxsw_addr_type *addr_type, u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num, u32 *broadcast_flags) { @@ -4849,7 +4850,7 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g, u32 *priv_addr_table, u32 *num_registers) { - int addr_type; /*enum ctxsw_addr_type */ + enum ctxsw_addr_type addr_type; u32 gpc_num, tpc_num, ppc_num, be_num; u32 priv_addr, gpc_addr; u32 broadcast_flags; diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 9c680827..0a8a536c 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -217,8 +217,9 @@ bool gv11b_gr_pri_is_egpc_addr(struct gk20a *g, u32 addr); bool gv11b_gr_pri_is_etpc_addr(struct gk20a *g, u32 addr); void gv11b_gr_get_egpc_etpc_num(struct gk20a *g, u32 addr, u32 *egpc_num, u32 *etpc_num); -int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, int *addr_type, - u32 *gpc_num, u32 *tpc_num, u32 *broadcast_flags); +int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, + enum ctxsw_addr_type *addr_type, u32 *gpc_num, u32 *tpc_num, + u32 *broadcast_flags); void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr, u32 gpc, u32 tpc, u32 broadcast_flags, u32 *priv_addr_table, u32 *t); u32 gv11b_gr_get_egpc_base(struct gk20a *g); @@ -242,7 +243,7 @@ u32 gv11b_gr_sm_offset(struct gk20a *g, u32 sm); u32 gr_gv11b_get_pmm_per_chiplet_offset(void); int gr_gv11b_decode_priv_addr(struct gk20a *g, u32 addr, - int *addr_type, + enum ctxsw_addr_type *addr_type, u32 *gpc_num, u32 *tpc_num, u32 *ppc_num, u32 *be_num, u32 *broadcast_flags); int gr_gv11b_create_priv_addr_table(struct gk20a *g, -- cgit v1.2.2