From 20a1ab078546c7206bb65ab007882195953df1dd Mon Sep 17 00:00:00 2001 From: Sam Payne Date: Thu, 5 Feb 2015 10:46:35 -0800 Subject: gpu: nvgpu: gp10b: add ce interrupt support ce interrupts use different register mapping and format from gk20a and gm20b. Change-Id: Icfe33bad940b2b829b6f57d07a3300adaf53d43c Signed-off-by: Sam Payne Reviewed-on: http://git-master/r/681646 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/Makefile | 1 + drivers/gpu/nvgpu/gp10b/ce2_gp10b.c | 83 ++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/ce2_gp10b.h | 29 ++++++++++++ drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 6 ++- drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h | 81 +++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 8 ++++ 6 files changed, 206 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/nvgpu/gp10b/ce2_gp10b.c create mode 100644 drivers/gpu/nvgpu/gp10b/ce2_gp10b.h create mode 100644 drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile index e14cd0ee..421e50f6 100644 --- a/drivers/gpu/nvgpu/gp10b/Makefile +++ b/drivers/gpu/nvgpu/gp10b/Makefile @@ -12,6 +12,7 @@ ccflags-y += -Werror obj-$(CONFIG_GK20A) += \ gr_gp10b.o \ gr_ctx_gp10b.o \ + ce2_gp10b.o \ mc_gp10b.o \ ltc_gp10b.o \ mm_gp10b.o \ diff --git a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c new file mode 100644 index 00000000..d76b97a5 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c @@ -0,0 +1,83 @@ +/* + * GK20A Graphics Copy Engine (gr host) + * + * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */ +#include "hw_ce2_gp10b.h" +#include "ce2_gp10b.h" + +static u32 ce2_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr) +{ + gk20a_dbg(gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n"); + + /* wake theads waiting in this channel */ + gk20a_channel_semaphore_wakeup(g); + return ce2_intr_status_nonblockpipe_pending_f(); +} + +static u32 ce2_blockpipe_isr(struct gk20a *g, u32 fifo_intr) +{ + gk20a_dbg(gpu_dbg_intr, "ce2 blocking pipe interrupt\n"); + + return ce2_intr_status_blockpipe_pending_f(); +} + +static u32 ce2_launcherr_isr(struct gk20a *g, u32 fifo_intr) +{ + gk20a_dbg(gpu_dbg_intr, "ce2 launch error interrupt\n"); + + return ce2_intr_status_launcherr_pending_f(); +} + +void gp10b_ce2_isr(struct gk20a *g) +{ + u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r(0)); + u32 clear_intr = 0; + + gk20a_dbg(gpu_dbg_intr, "ce2 isr %08x\n", ce2_intr); + + /* clear blocking interrupts: they exibit broken behavior */ + if (ce2_intr & ce2_intr_status_blockpipe_pending_f()) + clear_intr |= ce2_blockpipe_isr(g, ce2_intr); + + if (ce2_intr & ce2_intr_status_launcherr_pending_f()) + clear_intr |= ce2_launcherr_isr(g, ce2_intr); + + gk20a_writel(g, ce2_intr_status_r(0), clear_intr); + return; +} + +void gp10b_ce2_nonstall_isr(struct gk20a *g) +{ + u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r(0)); + u32 clear_intr = 0; + + gk20a_dbg(gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr); + + if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) + clear_intr |= ce2_nonblockpipe_isr(g, ce2_intr); + + gk20a_writel(g, ce2_intr_status_r(0), clear_intr); + + return; +} +void gp10b_init_ce2(struct gpu_ops *gops) +{ + gops->ce2.isr_stall = gp10b_ce2_isr; + gops->ce2.isr_nonstall = gp10b_ce2_nonstall_isr; +} diff --git a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.h b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.h new file mode 100644 index 00000000..d432d1e0 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.h @@ -0,0 +1,29 @@ +/* + * drivers/video/tegra/host/gk20a/fifo_gk20a.h + * + * GK20A graphics copy engine (gr host) + * + * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef __CE2_GP10B_H__ +#define __CE2_GP10B_H__ + +#include "gk20a/channel_gk20a.h" +#include "gk20a/tsg_gk20a.h" + +void gp10b_init_ce2(struct gpu_ops *gops); + +#endif /*__CE2_GP10B_H__*/ diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 30b56a5c..c23c0f17 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -1,7 +1,7 @@ /* * GP10B Tegra HAL interface * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -24,6 +24,7 @@ #include "gp10b/mc_gp10b.h" #include "gp10b/ltc_gp10b.h" #include "gp10b/mm_gp10b.h" +#include "gp10b/ce2_gp10b.h" #include "gp10b/fb_gp10b.h" #include "gp10b/pmu_gp10b.h" #include "gp10b/gr_ctx_gp10b.h" @@ -94,7 +95,8 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_gr(gops); gp10b_init_ltc(gops); gp10b_init_fb(gops); - gp10b_init_fifo(gops); + gm20b_init_fifo(gops); + gp10b_init_ce2(gops); gp10b_init_gr_ctx(gops); gp10b_init_mm(gops); gp10b_init_pmu_ops(gops); diff --git a/drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h new file mode 100644 index 00000000..b0c35a30 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ce2_gp10b_h_ +#define _hw_ce2_gp10b_h_ + +static inline u32 ce2_intr_status_r(u32 i) +{ + return 0x00104410 + i*128; +} +static inline u32 ce2_intr_status_blockpipe_pending_f(void) +{ + return 0x1; +} +static inline u32 ce2_intr_status_blockpipe_reset_f(void) +{ + return 0x1; +} +static inline u32 ce2_intr_status_nonblockpipe_pending_f(void) +{ + return 0x2; +} +static inline u32 ce2_intr_status_nonblockpipe_reset_f(void) +{ + return 0x2; +} +static inline u32 ce2_intr_status_launcherr_pending_f(void) +{ + return 0x4; +} +static inline u32 ce2_intr_status_launcherr_reset_f(void) +{ + return 0x4; +} +#endif diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 1760b6ad..47c8fcc6 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c @@ -110,6 +110,9 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); + if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id) + && g->ops.ce2.isr_stall) + g->ops.ce2.isr_stall(g); if (mc_intr_0 & mc_intr_pfifo_pending_f()) gk20a_fifo_isr(g); if (mc_intr_0 & mc_intr_pmu_pending_f()) @@ -141,6 +144,11 @@ irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) gk20a_fifo_nonstall_isr(g); if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) gk20a_gr_nonstall_isr(g); + if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id) + && g->ops.ce2.isr_nonstall) + g->ops.ce2.isr_nonstall(g); + + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); -- cgit v1.2.2