From 1f225fa73167ec31c9332e4031c156d8b04a41f6 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 13 May 2016 12:22:21 -0700 Subject: gpu: nvgpu: Implement engine_enum_from_type Implement a helper function engine_enum_from_type. This allows parsing device_info entries for LCE engine type. Pascal has logical copy engine instead of CE2, so so add definition of that. Change-Id: I71f59c308641d84ac59fd57fc37d9b627bb07a43 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1147747 Reviewed-by: Konsta Holtta --- drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | 17 +++++++++++++++ drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h | 38 +++++++++++++++++++++++++++++----- drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 8 +++---- 3 files changed, 54 insertions(+), 9 deletions(-) (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c index 4766e0e4..45de221e 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c @@ -23,6 +23,7 @@ #include "hw_ccsr_gp10b.h" #include "hw_fifo_gp10b.h" #include "hw_ram_gp10b.h" +#include "hw_top_gp10b.h" static void gp10b_set_pdb_fault_replay_flags(struct gk20a *g, struct mem_desc *mem) @@ -181,10 +182,26 @@ static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c) return 0; } +static int gp10b_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type) +{ + int ret = ENGINE_INVAL_GK20A; + + gk20a_dbg_info("engine type %d", engine_type); + if (engine_type == top_device_info_type_enum_graphics_v()) + ret = ENGINE_GR_GK20A; + else if (engine_type == top_device_info_type_enum_lce_v()) + ret = ENGINE_CE2_GK20A; + else + gk20a_err(g->dev, "unknown engine %d", engine_type); + + return ret; +} + void gp10b_init_fifo(struct gpu_ops *gops) { gm20b_init_fifo(gops); gops->fifo.setup_ramfc = channel_gp10b_setup_ramfc; gops->fifo.get_pbdma_signature = gp10b_fifo_get_pbdma_signature; gops->fifo.resetup_ramfc = gp10b_fifo_resetup_ramfc; + gops->fifo.engine_enum_from_type = gp10b_fifo_engine_enum_from_type; } diff --git a/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h index ab6f6373..5376717f 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -138,13 +138,37 @@ static inline u32 top_device_info_type_enum_graphics_f(void) { return 0x0; } -static inline u32 top_device_info_type_enum_copy0_v(void) +static inline u32 top_device_info_type_enum_copy2_v(void) { - return 0x00000001; + return 0x00000003; +} +static inline u32 top_device_info_type_enum_copy2_f(void) +{ + return 0xc; +} +static inline u32 top_device_info_type_enum_lce_v(void) +{ + return 0x00000013; +} +static inline u32 top_device_info_type_enum_lce_f(void) +{ + return 0x4c; +} +static inline u32 top_device_info_engine_v(u32 r) +{ + return (r >> 5) & 0x1; +} +static inline u32 top_device_info_runlist_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 top_device_info_intr_v(u32 r) +{ + return (r >> 3) & 0x1; } -static inline u32 top_device_info_type_enum_copy0_f(void) +static inline u32 top_device_info_reset_v(u32 r) { - return 0x4; + return (r >> 2) & 0x1; } static inline u32 top_device_info_entry_v(u32 r) { @@ -158,4 +182,8 @@ static inline u32 top_device_info_entry_enum_v(void) { return 0x00000002; } +static inline u32 top_device_info_entry_engine_type_v(void) +{ + return 0x00000002; +} #endif diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 47c8fcc6..4d9573d1 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c @@ -108,9 +108,9 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); - if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) + if (mc_intr_0 & g->fifo.engine_info[ENGINE_GR_GK20A].intr_mask) gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); - if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id) + if (mc_intr_0 & g->fifo.engine_info[ENGINE_CE2_GK20A].intr_mask && g->ops.ce2.isr_stall) g->ops.ce2.isr_stall(g); if (mc_intr_0 & mc_intr_pfifo_pending_f()) @@ -142,9 +142,9 @@ irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) if (mc_intr_1 & mc_intr_pfifo_pending_f()) gk20a_fifo_nonstall_isr(g); - if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) + if (mc_intr_1 & g->fifo.engine_info[ENGINE_GR_GK20A].intr_mask) gk20a_gr_nonstall_isr(g); - if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id) + if (mc_intr_1 & g->fifo.engine_info[ENGINE_CE2_GK20A].intr_mask && g->ops.ce2.isr_nonstall) g->ops.ce2.isr_nonstall(g); -- cgit v1.2.2