From 07b7a534fa8d5e93420521fcb5e745acad386f00 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 27 Oct 2014 09:47:25 +0200 Subject: gpu: nvgpu: Synchronize gp10b headers with gm20b Added all registers added to gk20a and gm20b to gp10b. Remove gp10b trim registers, because they will not be accessed by CPU. Bug 1567274 Change-Id: Ib6be34ce3d55901bd7e1f30eea8e43725719a912 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/590312 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h | 68 +++++- drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h | 32 ++- drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h | 20 ++ drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h | 44 ++++ drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h | 2 +- drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 228 ++++++++++++-------- drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h | 250 +++++++++++++++++++--- drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h | 50 ++++- drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h | 20 ++ drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h | 12 ++ drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h | 62 +++++- drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h | 72 ++----- drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h | 289 -------------------------- 13 files changed, 662 insertions(+), 487 deletions(-) delete mode 100644 drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h (limited to 'drivers') diff --git a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h index 6339cf5b..79890f3c 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h @@ -90,13 +90,25 @@ static inline u32 ctxsw_prog_main_image_pm_o(void) { return 0x00000028; } -static inline u32 ctxsw_prog_main_image_pm_mode_v(u32 r) +static inline u32 ctxsw_prog_main_image_pm_mode_m(void) { - return (r >> 0) & 0x7; + return 0x7 << 0; } -static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_v(void) +static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) { - return 0x00000000; + return 0x0; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) +{ + return 0x7 << 3; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) +{ + return 0x8; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) +{ + return 0x0; } static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) { @@ -178,4 +190,52 @@ static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_strid { return 0x00000002; } +static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) +{ + return 0x000000a0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) +{ + return 2; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) +{ + return 0x3 << 0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) +{ + return 0x2; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) +{ + return 0x000000a4; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) +{ + return 0x000000a8; +} +static inline u32 ctxsw_prog_main_image_misc_options_o(void) +{ + return 0x0000003c; +} +static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) +{ + return 0x1 << 3; +} +static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) +{ + return 0x0; +} #endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h index 9dacabce..d2ecdce1 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h @@ -66,6 +66,10 @@ static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void) { return 0x0; } +static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void) +{ + return 0x1; +} static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) { return (r >> 15) & 0x1; @@ -78,6 +82,22 @@ static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) { return (r >> 16) & 0xff; } +static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r) +{ + return (r >> 11) & 0x1; +} +static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void) +{ + return 0x800; +} +static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void) +{ + return 0x0; +} +static inline u32 fb_priv_mmu_phy_secure_r(void) +{ + return 0x00100ce4; +} static inline u32 fb_mmu_invalidate_pdb_r(void) { return 0x00100cb8; @@ -158,9 +178,9 @@ static inline u32 fb_mmu_debug_wr_vol_true_f(void) { return 0x4; } -static inline u32 fb_mmu_debug_wr_addr_v(u32 r) +static inline u32 fb_mmu_debug_wr_addr_f(u32 v) { - return (r >> 4) & 0xfffffff; + return (v & 0xfffffff) << 4; } static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) { @@ -178,9 +198,9 @@ static inline u32 fb_mmu_debug_rd_vol_false_f(void) { return 0x0; } -static inline u32 fb_mmu_debug_rd_addr_v(u32 r) +static inline u32 fb_mmu_debug_rd_addr_f(u32 v) { - return (r >> 4) & 0xfffffff; + return (v & 0xfffffff) << 4; } static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) { @@ -202,10 +222,6 @@ static inline u32 fb_mmu_vpr_info_r(void) { return 0x00100cd0; } -static inline u32 fb_mmu_vpr_info_fetch_f(u32 v) -{ - return (v & 0x1) << 2; -} static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) { return (r >> 2) & 0x1; diff --git a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h index 764c1b6c..b79758d2 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h @@ -206,6 +206,10 @@ static inline u32 fifo_intr_en_0_r(void) { return 0x00002140; } +static inline u32 fifo_intr_en_0_sched_error_m(void) +{ + return 0x1 << 8; +} static inline u32 fifo_intr_en_1_r(void) { return 0x00002528; @@ -346,10 +350,18 @@ static inline u32 fifo_preempt_type_channel_f(void) { return 0x0; } +static inline u32 fifo_preempt_type_tsg_f(void) +{ + return 0x1000000; +} static inline u32 fifo_preempt_chid_f(u32 v) { return (v & 0xfff) << 0; } +static inline u32 fifo_preempt_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} static inline u32 fifo_trigger_mmu_fault_r(u32 i) { return 0x00002a30 + i*4; @@ -382,6 +394,10 @@ static inline u32 fifo_engine_status_id_type_chid_v(void) { return 0x00000000; } +static inline u32 fifo_engine_status_id_type_tsgid_v(void) +{ + return 0x00000001; +} static inline u32 fifo_engine_status_ctx_status_v(u32 r) { return (r >> 13) & 0x7; @@ -466,6 +482,10 @@ static inline u32 fifo_pbdma_status_id_type_chid_v(void) { return 0x00000000; } +static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) +{ + return 0x00000001; +} static inline u32 fifo_pbdma_status_chan_status_v(u32 r) { return (r >> 13) & 0x7; diff --git a/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h index 00291d30..272f7fb3 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h @@ -54,4 +54,48 @@ static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) { return 0x00021c38 + i*4; } +static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) +{ + return 0x00021838 + i*4; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) +{ + return 0x00021944; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) +{ + return 0x3 << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) +{ + return 0x00021948; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) +{ + return 0x1 << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) +{ + return 0x1; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) +{ + return 0x0; +} #endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h index f6020434..161c1ce0 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h @@ -200,7 +200,7 @@ static inline u32 gmmu_pte_read_disable_true_f(void) } static inline u32 gmmu_pte_comptagline_f(u32 v) { - return (v & 0x3ffff) << 12; + return (v & 0x1ffff) << 12; } static inline u32 gmmu_pte_comptagline_w(void) { diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index 03164957..f8607618 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -78,6 +78,26 @@ static inline u32 gr_intr_illegal_method_reset_f(void) { return 0x10; } +static inline u32 gr_intr_illegal_notify_pending_f(void) +{ + return 0x40; +} +static inline u32 gr_intr_illegal_notify_reset_f(void) +{ + return 0x40; +} +static inline u32 gr_intr_firmware_method_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 gr_intr_firmware_method_pending_f(void) +{ + return 0x100; +} +static inline u32 gr_intr_firmware_method_reset_f(void) +{ + return 0x100; +} static inline u32 gr_intr_illegal_class_pending_f(void) { return 0x20; @@ -86,6 +106,14 @@ static inline u32 gr_intr_illegal_class_reset_f(void) { return 0x20; } +static inline u32 gr_intr_fecs_error_pending_f(void) +{ + return 0x80000; +} +static inline u32 gr_intr_fecs_error_reset_f(void) +{ + return 0x80000; +} static inline u32 gr_intr_class_error_pending_f(void) { return 0x100000; @@ -102,6 +130,26 @@ static inline u32 gr_intr_exception_reset_f(void) { return 0x200000; } +static inline u32 gr_fecs_intr_r(void) +{ + return 0x00400144; +} +static inline u32 gr_class_error_r(void) +{ + return 0x00400110; +} +static inline u32 gr_class_error_code_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_intr_nonstall_r(void) +{ + return 0x00400120; +} +static inline u32 gr_intr_nonstall_trap_pending_f(void) +{ + return 0x2; +} static inline u32 gr_intr_en_r(void) { return 0x0040013c; @@ -198,6 +246,10 @@ static inline u32 gr_status_r(void) { return 0x00400700; } +static inline u32 gr_status_fe_method_upper_v(u32 r) +{ + return (r >> 1) & 0x1; +} static inline u32 gr_status_fe_method_lower_v(u32 r) { return (r >> 2) & 0x1; @@ -206,6 +258,10 @@ static inline u32 gr_status_fe_method_lower_idle_v(void) { return 0x00000000; } +static inline u32 gr_status_fe_gi_v(u32 r) +{ + return (r >> 21) & 0x1; +} static inline u32 gr_status_mask_r(void) { return 0x00400610; @@ -662,6 +718,22 @@ static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) { return 0x21; } +static inline u32 gr_fecs_host_int_status_r(void) +{ + return 0x00409c18; +} +static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) +{ + return (v & 0x1) << 17; +} +static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) +{ + return (v & 0x1) << 18; +} +static inline u32 gr_fecs_host_int_clear_r(void) +{ + return 0x00409c20; +} static inline u32 gr_fecs_host_int_enable_r(void) { return 0x00409c24; @@ -1292,15 +1364,19 @@ static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) } static inline u32 gr_ds_tga_constraintlogic_r(void) { - return 0xffffffff; + return 0x00405830; } static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) { - return (v & 0x1) << -1; + return (v & 0x3fffff) << 0; +} +static inline u32 gr_ds_tga_constraintlogic_r(void) +{ + return 0x0040585c; } static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) { - return (v & 0x1) << -1; + return (v & 0xffff) << 0; } static inline u32 gr_ds_hww_esr_r(void) { @@ -1674,6 +1750,34 @@ static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) { return (r >> 0) & 0x3f; } +static inline u32 gr_gpccs_rc_lane_size_r(void) +{ + return 0x00502910; +} +static inline u32 gr_gpccs_rc_lane_size_v_s(void) +{ + return 24; +} +static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 gr_gpccs_rc_lane_size_v_m(void) +{ + return 0xffffff << 0; +} +static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) +{ + return (r >> 0) & 0xffffff; +} +static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) +{ + return 0x0; +} static inline u32 gr_gpc0_zcull_fs_r(void) { return 0x00500910; @@ -2068,19 +2172,11 @@ static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) } static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) { - return (v & 0xffffffff) << -1; + return (v & 0x3fffff) << 0; } static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) { - return 0xffffffff << -1; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_f(u32 v) -{ - return (v & 0xffffffff) << -1; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_m(void) -{ - return 0xffffffff << -1; + return 0x3fffff << 0; } static inline u32 gr_gpcs_swdx_rm_pagepool_r(void) { @@ -2526,26 +2622,6 @@ static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) { return 0x10000000; } -static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_r(void) -{ - return 0x00419e00; -} -static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_core_enable_m(void) -{ - return 0x1 << 7; -} -static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_core_enable_enable_f(void) -{ - return 0x80; -} -static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_m(void) -{ - return 0x1 << 15; -} -static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_enable_f(void) -{ - return 0x8000; -} static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) { return 0x00419e44; @@ -2670,51 +2746,51 @@ static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complet { return 0x40; } -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) { - return 0x0050450c; + return 0x00419d0c; } -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) { return 0x2; } -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_disabled_f(void) +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) { - return 0x0; + return 0x0050450c; } -static inline u32 gr_gpc0_gpccs_gpc_exception_en_r(void) +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) { - return 0x00502c94; + return 0x2; } -static inline u32 gr_gpc0_gpccs_gpc_exception_en_tpc_0_enabled_f(void) +static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) { - return 0x10000; + return 0x0041ac94; } -static inline u32 gr_gpc0_gpccs_gpc_exception_en_tpc_0_disabled_f(void) +static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) { - return 0x0; + return (v & 0xff) << 16; } -static inline u32 gr_gpcs_gpccs_gpc_exception_r(void) +static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) { - return 0x0041ac90; + return 0x00502c90; } -static inline u32 gr_gpcs_gpccs_gpc_exception_tpc_v(u32 r) +static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) { return (r >> 16) & 0xff; } -static inline u32 gr_gpcs_gpccs_gpc_exception_tpc_0_pending_v(void) +static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) { return 0x00000001; } -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_r(void) +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) { - return 0x00419d08; + return 0x00504508; } -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_sm_v(u32 r) +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) { return (r >> 1) & 0x1; } -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_sm_pending_v(void) +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) { return 0x00000001; } @@ -2810,10 +2886,6 @@ static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) { return (v & 0x1) << 0; } -static inline u32 gr_gpcs_tpcs_sm_power_throttle_r(void) -{ - return 0x00419ed8; -} static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) { return 0x0041be08; @@ -3078,42 +3150,6 @@ static inline u32 gr_fe_pwr_mode_req_done_v(void) { return 0x00000000; } -static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_r(void) -{ - return 0x00419f88; -} -static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_blkactivity_enable_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_blkactivity_enable_m(void) -{ - return 0x1 << 31; -} -static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_r(void) -{ - return 0x00419f80; -} -static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_blkactivity_enable_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_blkactivity_enable_m(void) -{ - return 0x1 << 31; -} -static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_r(void) -{ - return 0x00419ccc; -} -static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_blkactivity_enable_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_blkactivity_enable_m(void) -{ - return 0x1 << 31; -} static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) { return 0x00418880; @@ -3166,6 +3202,14 @@ static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) { return 0x004188b0; } +static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) +{ + return 0x00000001; +} static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) { return 0x004188b4; diff --git a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h index 2b20199e..a38cfe8d 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h @@ -50,30 +50,6 @@ #ifndef _hw_ltc_gp10b_h_ #define _hw_ltc_gp10b_h_ -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) -{ - return 0xffffffff; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) -{ - return 0xffffffff; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) -{ - return 0xffffffff; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) -{ - return 0xffffffff; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) -{ - return 0xffffffff; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) -{ - return 0xffffffff; -} static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) { return 0x0014046c; @@ -140,7 +116,7 @@ static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) } static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) { - return 0x0017e26c; + return 0x0014046c; } static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) { @@ -148,7 +124,7 @@ static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) } static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) { - return (v & 0x3ffff) << 0; + return (v & 0x1ffff) << 0; } static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) { @@ -156,7 +132,7 @@ static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) } static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) { - return (v & 0x3ffff) << 0; + return (v & 0x1ffff) << 0; } static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) { @@ -298,8 +274,224 @@ static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) { return 0x1; } -static inline u32 ltc_ltc0_ltss_intr_r(void) +static inline u32 ltc_ltcs_ltss_intr_r(void) { - return 0x0014020c; + return 0x0017e20c; +} +static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) +{ + return 0x1 << 20; +} +static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) +{ + return 0x1 << 30; +} +static inline u32 ltc_ltc0_lts0_intr_r(void) +{ + return 0x0014040c; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) +{ + return 0x0017e2a0; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) +{ + return (r >> 8) & 0xf; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) +{ + return 0x00000003; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) +{ + return 0x300; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) +{ + return 0x10000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) +{ + return 0x20000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) +{ + return 0x40000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) +{ + return 0x0017e2a4; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) +{ + return (r >> 8) & 0xf; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) +{ + return 0x00000003; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) +{ + return 0x300; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) +{ + return 0x10000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) +{ + return 0x10000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) +{ + return 0x20000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) +{ + return 0x40000000; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) +{ + return 0x001402a0; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) +{ + return 0x001402a4; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) +{ + return 0x001422a0; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) +{ + return 0x001422a4; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) +{ + return 0x1; } #endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h index 83e06e8e..ba0af497 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h @@ -50,38 +50,62 @@ #ifndef _hw_mc_gp10b_h_ #define _hw_mc_gp10b_h_ -static inline u32 mc_intr_0_r(u32 i) +static inline u32 mc_boot_0_r(void) { - return 0x00000100 + i*4; + return 0x00000000; } -static inline u32 mc_intr_0_pfifo_pending_f(void) +static inline u32 mc_boot_0_architecture_v(u32 r) { - return 0x100; + return (r >> 24) & 0x1f; } -static inline u32 mc_intr_0_pgraph_pending_f(void) +static inline u32 mc_boot_0_implementation_v(u32 r) { - return 0x1000; + return (r >> 20) & 0xf; +} +static inline u32 mc_boot_0_major_revision_v(u32 r) +{ + return (r >> 4) & 0xf; +} +static inline u32 mc_boot_0_minor_revision_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 mc_intr_r(u32 i) +{ + return 0x00000100 + i*4; } -static inline u32 mc_intr_0_pmu_pending_f(void) +static inline u32 mc_intr_pfifo_pending_f(void) +{ + return 0x100; +} +static inline u32 mc_intr_pmu_pending_f(void) { return 0x1000000; } -static inline u32 mc_intr_0_ltc_pending_f(void) +static inline u32 mc_intr_ltc_pending_f(void) { return 0x2000000; } -static inline u32 mc_intr_0_priv_ring_pending_f(void) +static inline u32 mc_intr_priv_ring_pending_f(void) { return 0x40000000; } -static inline u32 mc_intr_0_pbus_pending_f(void) +static inline u32 mc_intr_pbus_pending_f(void) { return 0x10000000; } -static inline u32 mc_intr_en_0_r(u32 i) +static inline u32 mc_intr_en_r(u32 i) { return 0x00000140 + i*4; } +static inline u32 mc_intr_en_set_r(u32 i) +{ + return 0x00000160 + i*4; +} +static inline u32 mc_intr_en_clear_r(u32 i) +{ + return 0x00000180 + i*4; +} static inline u32 mc_enable_r(void) { return 0x00000200; @@ -162,6 +186,10 @@ static inline u32 mc_enable_hub_enabled_f(void) { return 0x20000000; } +static inline u32 mc_intr_ltc_r(void) +{ + return 0x000001c0; +} static inline u32 mc_enable_pb_r(void) { return 0x00000204; diff --git a/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h index 5720cde1..91429b47 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h @@ -174,6 +174,10 @@ static inline u32 pbdma_pb_header_type_inc_f(void) { return 0x20000000; } +static inline u32 pbdma_hdr_shadow_r(u32 i) +{ + return 0x00040118 + i*8192; +} static inline u32 pbdma_subdevice_r(u32 i) { return 0x00040094 + i*8192; @@ -466,4 +470,20 @@ static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r) { return (r >> 8) & 0xfff; } +static inline u32 pbdma_runlist_timeslice_r(u32 i) +{ + return 0x000400f8 + i*8192; +} +static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) +{ + return 0x80; +} +static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) +{ + return 0x3000; +} +static inline u32 pbdma_runlist_timeslice_enable_true_f(void) +{ + return 0x10000000; +} #endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h index d76095ac..0de70b96 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h @@ -378,6 +378,18 @@ static inline u32 pwr_falcon_bootvec_vec_f(u32 v) { return (v & 0xffffffff) << 0; } +static inline u32 pwr_falcon_dmactl_r(void) +{ + return 0x0010a10c; +} +static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) +{ + return 0x1 << 1; +} +static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) +{ + return 0x1 << 2; +} static inline u32 pwr_falcon_hwcfg_r(void) { return 0x0010a108; diff --git a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h index ef53882b..509031e5 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h @@ -78,6 +78,26 @@ static inline u32 ram_in_page_dir_base_vol_true_f(void) { return 0x4; } +static inline u32 ram_in_big_page_size_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 ram_in_big_page_size_m(void) +{ + return 0x1 << 11; +} +static inline u32 ram_in_big_page_size_w(void) +{ + return 128; +} +static inline u32 ram_in_big_page_size_128kb_f(void) +{ + return 0x0; +} +static inline u32 ram_in_big_page_size_64kb_f(void) +{ + return 0x800; +} static inline u32 ram_in_page_dir_base_lo_f(u32 v) { return (v & 0xfffff) << 12; @@ -318,7 +338,7 @@ static inline u32 ram_fc_chid_id_w(void) { return 0; } -static inline u32 ram_fc_pb_timeslice_w(void) +static inline u32 ram_fc_runlist_timeslice_w(void) { return 62; } @@ -382,4 +402,44 @@ static inline u32 ram_rl_entry_size_v(void) { return 0x00000008; } +static inline u32 ram_rl_entry_chid_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_rl_entry_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_rl_entry_type_f(u32 v) +{ + return (v & 0x1) << 13; +} +static inline u32 ram_rl_entry_type_chid_f(void) +{ + return 0x0; +} +static inline u32 ram_rl_entry_type_tsg_f(void) +{ + return 0x2000; +} +static inline u32 ram_rl_entry_timeslice_scale_f(u32 v) +{ + return (v & 0xf) << 14; +} +static inline u32 ram_rl_entry_timeslice_scale_3_f(void) +{ + return 0xc000; +} +static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v) +{ + return (v & 0xff) << 18; +} +static inline u32 ram_rl_entry_timeslice_timeout_128_f(void) +{ + return 0x2000000; +} +static inline u32 ram_rl_entry_tsg_length_f(u32 v) +{ + return (v & 0x3f) << 26; +} #endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h index 16bbb3ca..25eecb70 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h @@ -70,58 +70,6 @@ static inline u32 therm_weight_1_r(void) { return 0x00020024; } -static inline u32 therm_peakpower_config1_r(u32 i) -{ - return 0x00020154 + i*4; -} -static inline u32 therm_peakpower_config1_window_period_2m_v(void) -{ - return 0x00000015; -} -static inline u32 therm_peakpower_config1_window_period_2m_f(void) -{ - return 0x15; -} -static inline u32 therm_peakpower_config1_window_en_enabled_f(void) -{ - return 0x80000000; -} -static inline u32 therm_peakpower_config1_r(u32 i) -{ - return 0x000202e8 + i*4; -} -static inline u32 therm_peakpower_config1_ba_sum_shift_s(void) -{ - return 5; -} -static inline u32 therm_peakpower_config1_ba_sum_shift_f(u32 v) -{ - return (v & 0x1f) << 8; -} -static inline u32 therm_peakpower_config1_ba_sum_shift_m(void) -{ - return 0x1f << 8; -} -static inline u32 therm_peakpower_config1_ba_sum_shift_v(u32 r) -{ - return (r >> 8) & 0x1f; -} -static inline u32 therm_peakpower_config2_r(u32 i) -{ - return 0x00020170 + i*4; -} -static inline u32 therm_peakpower_config4_r(u32 i) -{ - return 0x000201c0 + i*4; -} -static inline u32 therm_peakpower_config8_r(u32 i) -{ - return 0x000202e8 + i*4; -} -static inline u32 therm_peakpower_config9_r(u32 i) -{ - return 0x000202f4 + i*4; -} static inline u32 therm_config1_r(void) { return 0x00020050; @@ -214,4 +162,24 @@ static inline u32 therm_hubmmu_idle_filter_value_m(void) { return 0xffffffff << 0; } +static inline u32 therm_clk_slowdown_r(u32 i) +{ + return 0x00020160 + i*4; +} +static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) +{ + return (v & 0x3f) << 16; +} +static inline u32 therm_clk_slowdown_idle_factor_m(void) +{ + return 0x3f << 16; +} +static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) +{ + return (r >> 16) & 0x3f; +} +static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) +{ + return 0x0; +} #endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h deleted file mode 100644 index 94da91b0..00000000 --- a/drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_trim_gp10b_h_ -#define _hw_trim_gp10b_h_ - -static inline u32 trim_sys_gpcpll_cfg_r(void) -{ - return 0x00137000; -} -static inline u32 trim_sys_gpcpll_cfg_enable_m(void) -{ - return 0x1 << 0; -} -static inline u32 trim_sys_gpcpll_cfg_enable_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 trim_sys_gpcpll_cfg_enable_no_f(void) -{ - return 0x0; -} -static inline u32 trim_sys_gpcpll_cfg_enable_yes_f(void) -{ - return 0x1; -} -static inline u32 trim_sys_gpcpll_cfg_iddq_m(void) -{ - return 0x1 << 1; -} -static inline u32 trim_sys_gpcpll_cfg_iddq_v(u32 r) -{ - return (r >> 1) & 0x1; -} -static inline u32 trim_sys_gpcpll_cfg_iddq_power_on_v(void) -{ - return 0x00000000; -} -static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void) -{ - return 0x1 << 4; -} -static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_on_f(void) -{ - return 0x0; -} -static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_off_f(void) -{ - return 0x10; -} -static inline u32 trim_sys_gpcpll_cfg_pll_lock_v(u32 r) -{ - return (r >> 17) & 0x1; -} -static inline u32 trim_sys_gpcpll_cfg_pll_lock_true_f(void) -{ - return 0x20000; -} -static inline u32 trim_sys_gpcpll_coeff_r(void) -{ - return 0x00137004; -} -static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r) -{ - return (r >> 0) & 0xff; -} -static inline u32 trim_sys_gpcpll_coeff_ndiv_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 trim_sys_gpcpll_coeff_ndiv_m(void) -{ - return 0xff << 8; -} -static inline u32 trim_sys_gpcpll_coeff_ndiv_v(u32 r) -{ - return (r >> 8) & 0xff; -} -static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v) -{ - return (v & 0x3f) << 16; -} -static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r) -{ - return (r >> 16) & 0x3f; -} -static inline u32 trim_sys_sel_vco_r(void) -{ - return 0x00137100; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_m(void) -{ - return 0x1 << 0; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_init_v(void) -{ - return 0x00000000; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_init_f(void) -{ - return 0x0; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_bypass_f(void) -{ - return 0x0; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_vco_f(void) -{ - return 0x1; -} -static inline u32 trim_sys_gpc2clk_out_r(void) -{ - return 0x00137250; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_s(void) -{ - return 6; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_f(u32 v) -{ - return (v & 0x3f) << 0; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_m(void) -{ - return 0x3f << 0; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_v(u32 r) -{ - return (r >> 0) & 0x3f; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_by31_f(void) -{ - return 0x3c; -} -static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void) -{ - return 0x3f << 8; -} -static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void) -{ - return 0x0; -} -static inline u32 trim_sys_gpc2clk_out_sdiv14_m(void) -{ - return 0x1 << 31; -} -static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void) -{ - return 0x80000000; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i) -{ - return 0x001e0124 + i*1024; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void) -{ - return 0x10000; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void) -{ - return 0x100000; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void) -{ - return 0x1000000; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i) -{ - return 0x001e0128 + i*1024; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r) -{ - return (r >> 0) & 0xfffffff; -} -static inline u32 trim_sys_gpcpll_cfg2_r(void) -{ - return 0x0013700c; -} -static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_f(u32 v) -{ - return (v & 0xff) << 24; -} -static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_m(void) -{ - return 0xff << 24; -} -static inline u32 trim_sys_gpcpll_cfg3_r(void) -{ - return 0x00137018; -} -static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_f(u32 v) -{ - return (v & 0xff) << 16; -} -static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void) -{ - return 0xff << 16; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_r(void) -{ - return 0x0013701c; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(void) -{ - return 0x1 << 22; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f(void) -{ - return 0x400000; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f(void) -{ - return 0x0; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(void) -{ - return 0x1 << 31; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f(void) -{ - return 0x80000000; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f(void) -{ - return 0x0; -} -static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r(void) -{ - return 0x001328a0; -} -static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(u32 r) -{ - return (r >> 24) & 0x1; -} -#endif -- cgit v1.2.2