From d59271c7b79080388371877fc2d10574ca42206a Mon Sep 17 00:00:00 2001 From: Sunny He Date: Mon, 24 Jul 2017 12:18:38 -0700 Subject: gpu: nvgpu: Remove privsecurity flag from gpu_ops Replace privsecurity boolean flag in gpu_ops with entry in common flag system. The new common flag is NVGPU_SEC_PRIVSECURITY Jira NVGPU-74 Change-Id: I4b258f5ffbe30a6344ffba0ece51c6f5d47ebec1 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1525713 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gk20a/gk20a.h | 1 - drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 10 ++++++---- drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 2 +- drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 16 ++++++++-------- drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 7 +++++-- drivers/gpu/nvgpu/gm20b/pmu_gm20b.h | 6 ++++-- drivers/gpu/nvgpu/gp106/gr_gp106.c | 6 ++++-- drivers/gpu/nvgpu/gp106/gr_gp106.h | 6 ++++-- drivers/gpu/nvgpu/gp106/hal_gp106.c | 6 +++--- drivers/gpu/nvgpu/gp106/pmu_gp106.c | 7 ++++--- drivers/gpu/nvgpu/gp106/pmu_gp106.h | 4 +++- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 6 ++++-- drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 4 ++-- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 18 +++++++++--------- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 6 ++++-- drivers/gpu/nvgpu/gp10b/pmu_gp10b.h | 4 +++- drivers/gpu/nvgpu/include/nvgpu/enabled.h | 1 + 17 files changed, 65 insertions(+), 45 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 8728c9a7..8135f05e 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -992,7 +992,6 @@ struct gpu_ops { struct { void (*isr)(struct gk20a *g); } priv_ring; - bool privsecurity; }; struct nvgpu_bios_ucode { diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 5d9cc32c..f60d880d 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -42,7 +42,7 @@ static void gr_gm20b_init_gpc_mmu(struct gk20a *g) gk20a_dbg_info("initialize gpc mmu"); - if (!g->ops.privsecurity) { + if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { /* Bypass MMU check for non-secure boot. For * secure-boot,this register write has no-effect */ gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffff); @@ -680,7 +680,7 @@ static int gr_gm20b_load_ctxsw_ucode_segments(struct gk20a *g, u64 addr_base, gr_gk20a_load_ctxsw_ucode_boot(g, addr_base, segments, reg_offset); /* start the falcon immediately if PRIV security is disabled*/ - if (!g->ops.privsecurity) { + if (!nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { gk20a_writel(g, reg_offset + gr_fecs_cpuctl_r(), gr_fecs_cpuctl_startcpu_f(0x01)); } @@ -1542,8 +1542,10 @@ static void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, gk20a_writel(g, gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset, 0); } -void gm20b_init_gr(struct gpu_ops *gops) +void gm20b_init_gr(struct gk20a *g) { + struct gpu_ops *gops = &g->ops; + gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu; gops->gr.bundle_cb_defaults = gr_gm20b_bundle_cb_defaults; gops->gr.cb_size_default = gr_gm20b_cb_size_default; @@ -1565,7 +1567,7 @@ void gm20b_init_gr(struct gpu_ops *gops) gops->gr.init_fs_state = gr_gm20b_init_fs_state; gops->gr.set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask; gops->gr.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments; - if (gops->privsecurity) + if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; else gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index e7dd091a..d3adacd8 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h @@ -36,7 +36,7 @@ enum { #define NVB1C0_SET_RD_COALESCE 0x0228 #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 -void gm20b_init_gr(struct gpu_ops *gops); +void gm20b_init_gr(struct gk20a *g); void gr_gm20b_commit_global_attrib_cb(struct gk20a *g, struct channel_ctx_gk20a *ch_ctx, u64 addr, bool patch); diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 01e277ce..228e1a97 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -356,38 +356,38 @@ int gm20b_init_hal(struct gk20a *g) #ifdef CONFIG_TEGRA_ACR if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { - gops->privsecurity = 1; + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); } else { val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); if (!val) { gk20a_dbg_info("priv security is disabled in HW"); - gops->privsecurity = 0; + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); } else { - gops->privsecurity = 1; + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); } } #else if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { gk20a_dbg_info("running ASIM with PRIV security disabled"); - gops->privsecurity = 0; + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); } else { val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); if (!val) { - gops->privsecurity = 0; + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); } else { gk20a_dbg_info("priv security is not supported but enabled"); - gops->privsecurity = 1; + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); return -EPERM; } } #endif g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; - gm20b_init_gr(gops); + gm20b_init_gr(g); gm20b_init_fb(gops); gm20b_init_ce2(gops); gm20b_init_gr_ctx(gops); gm20b_init_mm(gops); - gm20b_init_pmu_ops(gops); + gm20b_init_pmu_ops(g); gm20b_init_clk_ops(gops); gm20b_init_regops(gops); gm20b_init_therm_ops(gops); diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 0f99c67e..98cd3906 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/pmu_gk20a.h" @@ -273,9 +274,11 @@ static void pmu_dump_security_fuses_gm20b(struct gk20a *g) val); } -void gm20b_init_pmu_ops(struct gpu_ops *gops) +void gm20b_init_pmu_ops(struct gk20a *g) { - if (gops->privsecurity) { + struct gpu_ops *gops = &g->ops; + + if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { gm20b_init_secure_pmu(gops); gops->pmu.init_wpr_region = gm20b_pmu_init_acr; gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode; diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h index e3deb6ef..424fab35 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h @@ -1,7 +1,7 @@ /* * GM20B PMU * - * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,7 +16,9 @@ #ifndef __PMU_GM20B_H_ #define __PMU_GM20B_H_ -void gm20b_init_pmu_ops(struct gpu_ops *gops); +struct gk20a; + +void gm20b_init_pmu_ops(struct gk20a *g); void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags); int gm20b_pmu_init_acr(struct gk20a *g); void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr); diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.c b/drivers/gpu/nvgpu/gp106/gr_gp106.c index bf266b66..76e5cf89 100644 --- a/drivers/gpu/nvgpu/gp106/gr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/gr_gp106.c @@ -234,9 +234,11 @@ fail: return err; } -void gp106_init_gr(struct gpu_ops *gops) +void gp106_init_gr(struct gk20a *g) { - gp10b_init_gr(gops); + struct gpu_ops *gops = &g->ops; + + gp10b_init_gr(g); gops->gr.is_valid_class = gr_gp106_is_valid_class; gops->gr.pagepool_default_size = gr_gp106_pagepool_default_size; gops->gr.handle_sw_method = gr_gp106_handle_sw_method; diff --git a/drivers/gpu/nvgpu/gp106/gr_gp106.h b/drivers/gpu/nvgpu/gp106/gr_gp106.h index 4fe22ee9..3f49aac6 100644 --- a/drivers/gpu/nvgpu/gp106/gr_gp106.h +++ b/drivers/gpu/nvgpu/gp106/gr_gp106.h @@ -1,7 +1,7 @@ /* * GP106 GPU GR * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,11 +16,13 @@ #ifndef _NVGPU_GR_GP106_H_ #define _NVGPU_GR_GP106_H_ +struct gk20a; + enum { PASCAL_B = 0xC197, PASCAL_COMPUTE_B = 0xC1C0, }; -void gp106_init_gr(struct gpu_ops *gops); +void gp106_init_gr(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 80117ede..49c4b358 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -416,18 +416,18 @@ int gp106_init_hal(struct gk20a *g) gp106_ops.chip_init_gpu_characteristics; gops->bios_init = gp106_ops.bios_init; - gops->privsecurity = 1; + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); g->bootstrap_owner = LSF_FALCON_ID_SEC2; - gp106_init_gr(gops); + gp106_init_gr(g); gp10b_init_fecs_trace_ops(gops); gp106_init_fb(gops); gp10b_init_ce(gops); gp106_init_gr_ctx(gops); gp106_init_mm(gops); - gp106_init_pmu_ops(gops); + gp106_init_pmu_ops(g); gp106_init_clk_ops(gops); gp106_init_clk_arb_ops(gops); gp106_init_regops(gops); diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c index a09aa30b..a9fb794d 100644 --- a/drivers/gpu/nvgpu/gp106/pmu_gp106.c +++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c @@ -12,6 +12,7 @@ */ #include +#include #include "gk20a/gk20a.h" #include "gk20a/pmu_gk20a.h" @@ -289,11 +290,11 @@ static int gp106_load_falcon_ucode(struct gk20a *g, u32 falconidmask) return 0; } -void gp106_init_pmu_ops(struct gpu_ops *gops) +void gp106_init_pmu_ops(struct gk20a *g) { + struct gpu_ops *gops = &g->ops; gk20a_dbg_fn(""); - - if (gops->privsecurity) { + if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { gp106_init_secure_pmu(gops); gops->pmu.init_wpr_region = gm20b_pmu_init_acr; gops->pmu.load_lsfalcon_ucode = gp106_load_falcon_ucode; diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.h b/drivers/gpu/nvgpu/gp106/pmu_gp106.h index 5f399b89..68a00bb5 100644 --- a/drivers/gpu/nvgpu/gp106/pmu_gp106.h +++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.h @@ -17,7 +17,9 @@ #define gp106_dbg_pmu(fmt, arg...) \ gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) -void gp106_init_pmu_ops(struct gpu_ops *gops); +struct gk20a; + +void gp106_init_pmu_ops(struct gk20a *g); void gp106_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, struct pmu_pg_stats_data *pg_stat_data); bool gp106_pmu_is_engine_in_reset(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 67a38e6e..d2b86e51 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -2368,9 +2368,11 @@ int gr_gp10b_set_czf_bypass(struct gk20a *g, struct channel_gk20a *ch) return __gr_gk20a_exec_ctx_ops(ch, &ops, 1, 1, 0, false); } -void gp10b_init_gr(struct gpu_ops *gops) +void gp10b_init_gr(struct gk20a *g) { - gm20b_init_gr(gops); + struct gpu_ops *gops = &g->ops; + + gm20b_init_gr(g); gops->gr.init_fs_state = gr_gp10b_init_fs_state; gops->gr.init_preemption_state = gr_gp10b_init_preemption_state; gops->gr.is_valid_class = gr_gp10b_is_valid_class; diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index aac9eb65..161fec87 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h @@ -20,7 +20,7 @@ #include "gk20a/mm_gk20a.h" -struct gpu_ops; +struct gk20a; struct gr_gk20a_isr_data; enum { @@ -41,7 +41,7 @@ enum { #define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528 #define NVC0C0_SET_RD_COALESCE 0x0228 -void gp10b_init_gr(struct gpu_ops *ops); +void gp10b_init_gr(struct gk20a *g); int gr_gp10b_init_fs_state(struct gk20a *g); int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size, struct nvgpu_mem *mem); diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 818949f0..6b4fbf40 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -368,49 +368,49 @@ int gp10b_init_hal(struct gk20a *g) #ifdef CONFIG_TEGRA_ACR if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { - gops->privsecurity = 0; + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); } else if (g->is_virtual) { - gops->privsecurity = 1; + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); } else { val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); if (val) { - gops->privsecurity = 1; + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); } else { gk20a_dbg_info("priv security is disabled in HW"); - gops->privsecurity = 0; + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); } } #else if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { gk20a_dbg_info("running simulator with PRIV security disabled"); - gops->privsecurity = 0; + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); } else { val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); if (val) { gk20a_dbg_info("priv security is not supported but enabled"); - gops->privsecurity = 1; + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); return -EPERM; } else { - gops->privsecurity = 0; + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); } } #endif g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; - gp10b_init_gr(gops); + gp10b_init_gr(g); gp10b_init_fecs_trace_ops(gops); gp10b_init_fb(gops); gp10b_init_ce(gops); gp10b_init_gr_ctx(gops); gp10b_init_mm(gops); - gp10b_init_pmu_ops(gops); + gp10b_init_pmu_ops(g); gp10b_init_regops(gops); gp10b_init_therm_ops(gops); gk20a_init_pramin_ops(gops); diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index dbaf3ebf..e9a9b922 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -16,6 +16,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/pmu_gk20a.h" @@ -391,10 +392,11 @@ static bool gp10b_is_pmu_supported(struct gk20a *g) return true; } -void gp10b_init_pmu_ops(struct gpu_ops *gops) +void gp10b_init_pmu_ops(struct gk20a *g) { + struct gpu_ops *gops = &g->ops; gops->pmu.is_pmu_supported = gp10b_is_pmu_supported; - if (gops->privsecurity) { + if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { gm20b_init_secure_pmu(gops); gops->pmu.init_wpr_region = gm20b_pmu_init_acr; gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h index 9fc6228d..5ba7bb9b 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h @@ -16,7 +16,9 @@ #ifndef __PMU_GP10B_H_ #define __PMU_GP10B_H_ -void gp10b_init_pmu_ops(struct gpu_ops *gops); +struct gk20a; + +void gp10b_init_pmu_ops(struct gk20a *g); int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask); int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id); void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr); diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h index 7d495f48..7aac4be9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h @@ -42,6 +42,7 @@ struct gk20a; */ #define NVGPU_SEC_SECUREGPCCS 32 +#define NVGPU_SEC_PRIVSECURITY 33 /* * PMU flags. -- cgit v1.2.2