From d4c51a7321a506a73ad6c9c64b3a443ce98c1700 Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Thu, 7 Dec 2017 02:03:08 +0530 Subject: gpu: nvgpu: gv11b: Update elpg init seq for gv11b. This updates register address/value pairs for ELPG init sequence in GV11B. Bug 200365505. Change-Id: I62517c378c39f5025f797cf849f10e6b0eae27a8 Signed-off-by: Deepak Goyal Reviewed-on: https://git-master.nvidia.com/r/1612642 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 9 ---- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 8 --- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 +- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 95 +++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/pmu_gv11b.h | 1 + drivers/gpu/nvgpu/include/nvgpu/pmu.h | 9 ++++ 6 files changed, 106 insertions(+), 18 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 664134f9..1c5fdce0 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c @@ -37,15 +37,6 @@ #include #include -/*! - * Structure/object which single register write need to be done during PG init - * sequence to set PROD values. - */ -struct pg_init_sequence_list { - u32 regaddr; - u32 writeval; -}; - #define gm20b_dbg_pmu(fmt, arg...) \ gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 147cd020..d368bad7 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -39,14 +39,6 @@ #define gp10b_dbg_pmu(fmt, arg...) \ gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) -/*! - * Structure/object which single register write need to be done during PG init - * sequence to set PROD values. - */ -struct pg_init_sequence_list { - u32 regaddr; - u32 writeval; -}; /* PROD settings for ELPG sequencing registers*/ static struct pg_init_sequence_list _pginitseq_gp10b[] = { diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index bdf741d9..6a21eb2d 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -589,7 +589,7 @@ static const struct gpu_ops gv11b_ops = { .elcg_init_idle_filters = gv11b_elcg_init_idle_filters, }, .pmu = { - .pmu_setup_elpg = gp10b_pmu_setup_elpg, + .pmu_setup_elpg = gv11b_pmu_setup_elpg, .pmu_get_queue_head = pwr_pmu_queue_head_r, .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, .pmu_get_queue_tail = pwr_pmu_queue_tail_r, diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 3e80a51a..4b244f5a 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -42,6 +42,101 @@ #define ALIGN_4KB 12 +/* PROD settings for ELPG sequencing registers*/ +static struct pg_init_sequence_list _pginitseq_gv11b[] = { + {0x0010e0a8, 0x00000000} , + {0x0010e0ac, 0x00000000} , + {0x0010e198, 0x00000200} , + {0x0010e19c, 0x00000000} , + {0x0010e19c, 0x00000000} , + {0x0010e19c, 0x00000000} , + {0x0010e19c, 0x00000000} , + {0x0010aba8, 0x00000200} , + {0x0010abac, 0x00000000} , + {0x0010abac, 0x00000000} , + {0x0010abac, 0x00000000} , + {0x0010e09c, 0x00000731} , + {0x0010e18c, 0x00000731} , + {0x0010ab9c, 0x00000731} , + {0x0010e0a0, 0x00000200} , + {0x0010e0a4, 0x00000004} , + {0x0010e0a4, 0x80000000} , + {0x0010e0a4, 0x80000009} , + {0x0010e0a4, 0x8000001A} , + {0x0010e0a4, 0x8000001E} , + {0x0010e0a4, 0x8000002A} , + {0x0010e0a4, 0x8000002E} , + {0x0010e0a4, 0x80000016} , + {0x0010e0a4, 0x80000022} , + {0x0010e0a4, 0x80000026} , + {0x0010e0a4, 0x00000005} , + {0x0010e0a4, 0x80000001} , + {0x0010e0a4, 0x8000000A} , + {0x0010e0a4, 0x8000001B} , + {0x0010e0a4, 0x8000001F} , + {0x0010e0a4, 0x8000002B} , + {0x0010e0a4, 0x8000002F} , + {0x0010e0a4, 0x80000017} , + {0x0010e0a4, 0x80000023} , + {0x0010e0a4, 0x80000027} , + {0x0010e0a4, 0x00000006} , + {0x0010e0a4, 0x80000002} , + {0x0010e0a4, 0x8000000B} , + {0x0010e0a4, 0x8000001C} , + {0x0010e0a4, 0x80000020} , + {0x0010e0a4, 0x8000002C} , + {0x0010e0a4, 0x80000030} , + {0x0010e0a4, 0x80000018} , + {0x0010e0a4, 0x80000024} , + {0x0010e0a4, 0x80000028} , + {0x0010e0a4, 0x00000007} , + {0x0010e0a4, 0x80000003} , + {0x0010e0a4, 0x8000000C} , + {0x0010e0a4, 0x8000001D} , + {0x0010e0a4, 0x80000021} , + {0x0010e0a4, 0x8000002D} , + {0x0010e0a4, 0x80000031} , + {0x0010e0a4, 0x80000019} , + {0x0010e0a4, 0x80000025} , + {0x0010e0a4, 0x80000029} , + {0x0010e0a4, 0x80000012} , + {0x0010e0a4, 0x80000010} , + {0x0010e0a4, 0x00000013} , + {0x0010e0a4, 0x80000011} , + {0x0010e0a4, 0x80000008} , + {0x0010e0a4, 0x8000000D} , + {0x0010e190, 0x00000200} , + {0x0010e194, 0x80000015} , + {0x0010e194, 0x80000014} , + {0x0010aba0, 0x00000200} , + {0x0010aba4, 0x8000000E} , + {0x0010aba4, 0x0000000F} , + {0x0010ab34, 0x00000001} , + {0x00020004, 0x00000000} , +}; + +int gv11b_pmu_setup_elpg(struct gk20a *g) +{ + int ret = 0; + u32 reg_writes; + u32 index; + + gk20a_dbg_fn(""); + + if (g->elpg_enabled) { + reg_writes = ((sizeof(_pginitseq_gv11b) / + sizeof((_pginitseq_gv11b)[0]))); + /* Initialize registers with production values*/ + for (index = 0; index < reg_writes; index++) { + gk20a_writel(g, _pginitseq_gv11b[index].regaddr, + _pginitseq_gv11b[index].writeval); + } + } + + gk20a_dbg_fn("done"); + return ret; +} + bool gv11b_is_pmu_supported(struct gk20a *g) { return true; diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h index 809970ff..e917188d 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h @@ -33,5 +33,6 @@ int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id); int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id); bool gv11b_is_lazy_bootstrap(u32 falcon_id); bool gv11b_is_priv_load(u32 falcon_id); +int gv11b_pmu_setup_elpg(struct gk20a *g); #endif /*__PMU_GV11B_H_*/ diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h index a818f3d0..c0ceca61 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h @@ -380,6 +380,15 @@ struct pmu_pg_stats_data { u32 avg_exit_latency_us; }; +/*! + * Structure/object which single register write need to be done during PG init + * sequence to set PROD values. + */ +struct pg_init_sequence_list { + u32 regaddr; + u32 writeval; +}; + /* PMU IPC Methods */ void nvgpu_pmu_seq_init(struct nvgpu_pmu *pmu); -- cgit v1.2.2