From cce0a55d2106865be14b3b39c083a0f55881f2a5 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Tue, 1 Aug 2017 17:12:03 -0700 Subject: gpu: nvgpu: gv11b: Reorg pmu HAL init Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the pmu sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I3f8a763a7bebf201c2242eecde7ff998aad07d0a Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1530983 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 51 ++++++++++++++++++++++++++-- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 67 +++++++++++++++++++++++++++++++++++-- drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 32 +++--------------- drivers/gpu/nvgpu/gv11b/pmu_gv11b.h | 5 ++- 4 files changed, 122 insertions(+), 33 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 74bc48fb..bd13ec08 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -32,19 +32,23 @@ #include "gk20a/regops_gk20a.h" #include "gk20a/fb_gk20a.h" #include "gk20a/mm_gk20a.h" +#include "gk20a/pmu_gk20a.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/fifo_gm20b.h" #include "gm20b/fb_gm20b.h" #include "gm20b/mm_gm20b.h" +#include "gm20b/pmu_gm20b.h" +#include "gm20b/acr_gm20b.h" #include "gp10b/fb_gp10b.h" #include "gp106/clk_gp106.h" #include "gp106/clk_arb_gp106.h" #include "gp106/pmu_gp106.h" - +#include "gp106/acr_gp106.h" +#include "gp106/sec2_gp106.h" #include "gm206/bios_gm206.h" #include "gp106/therm_gp106.h" #include "gp106/xve_gp106.h" @@ -58,6 +62,7 @@ #include "gp10b/fifo_gp10b.h" #include "gp10b/fecs_trace_gp10b.h" #include "gp10b/mm_gp10b.h" +#include "gp10b/pmu_gp10b.h" #include "gv11b/hal_gv11b.h" #include "gv11b/gr_gv11b.h" @@ -87,6 +92,7 @@ #include #include #include +#include static int gv100_get_litter_value(struct gk20a *g, int value) { @@ -345,6 +351,45 @@ static const struct gpu_ops gv100_ops = { .exit = gk20a_pramin_exit, .data032_r = pram_data032_r, }, + .pmu = { + .init_wpr_region = gm20b_pmu_init_acr, + .load_lsfalcon_ucode = gp106_load_falcon_ucode, + .is_lazy_bootstrap = gp106_is_lazy_bootstrap, + .is_priv_load = gp106_is_priv_load, + .prepare_ucode = gp106_prepare_ucode_blob, + .pmu_setup_hw_and_bootstrap = gp106_bootstrap_hs_flcn, + .get_wpr = gp106_wpr_info, + .alloc_blob_space = gp106_alloc_blob_space, + .pmu_populate_loader_cfg = gp106_pmu_populate_loader_cfg, + .flcn_populate_bl_dmem_desc = gp106_flcn_populate_bl_dmem_desc, + .falcon_wait_for_halt = sec2_wait_for_halt, + .falcon_clear_halt_interrupt_status = + sec2_clear_halt_interrupt_status, + .init_falcon_setup_hw = init_sec2_setup_hw1, + .pmu_queue_tail = gk20a_pmu_queue_tail, + .pmu_get_queue_head = pwr_pmu_queue_head_r, + .pmu_mutex_release = gk20a_pmu_mutex_release, + .is_pmu_supported = gp106_is_pmu_supported, + .pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list, + .pmu_elpg_statistics = gp106_pmu_elpg_statistics, + .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, + .pmu_is_lpwr_feature_supported = + gp106_pmu_is_lpwr_feature_supported, + .pmu_msgq_tail = gk20a_pmu_msgq_tail, + .pmu_pg_engines_feature_list = gp106_pmu_pg_feature_list, + .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, + .pmu_queue_head = gk20a_pmu_queue_head, + .pmu_pg_param_post_init = nvgpu_lpwr_post_init, + .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, + .pmu_pg_init_param = gp106_pg_param_init, + .reset_engine = gp106_pmu_engine_reset, + .pmu_lpwr_disable_pg = nvgpu_lpwr_disable_pg, + .write_dmatrfbase = gp10b_write_dmatrfbase, + .pmu_mutex_size = pwr_pmu_mutex__size_1_v, + .is_engine_in_reset = gp106_pmu_is_engine_in_reset, + .pmu_get_queue_tail = pwr_pmu_queue_tail_r, + .pmu_lpwr_enable_pg = nvgpu_lpwr_enable_pg, + }, .clk = { .init_clk_support = gp106_init_clk_support, .get_crystal_clk_hz = gp106_crystal_clk_hz, @@ -444,6 +489,7 @@ int gv100_init_hal(struct gk20a *g) gops->fecs_trace = gv100_ops.fecs_trace; gops->pramin = gv100_ops.pramin; gops->therm = gv100_ops.therm; + gops->pmu = gv100_ops.pmu; gops->mc = gv100_ops.mc; gops->debug = gv100_ops.debug; gops->dbg_session_ops = gv100_ops.dbg_session_ops; @@ -470,13 +516,14 @@ int gv100_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); + __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); /* for now */ __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); + g->pmu_lsf_pmu_wpr_init_done = 0; g->bootstrap_owner = LSF_FALCON_ID_SEC2; gv11b_init_gr(g); - gp106_init_pmu_ops(g); gv11b_init_uncompressed_kind_map(); gv11b_init_kind_attr(); diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index f572084d..521cafa3 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -31,12 +31,15 @@ #include "gk20a/flcn_gk20a.h" #include "gk20a/regops_gk20a.h" #include "gk20a/fb_gk20a.h" +#include "gk20a/pmu_gk20a.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/fb_gm20b.h" #include "gm20b/fifo_gm20b.h" #include "gm20b/mm_gm20b.h" +#include "gm20b/acr_gm20b.h" +#include "gm20b/pmu_gm20b.h" #include "gp10b/ltc_gp10b.h" #include "gp10b/therm_gp10b.h" @@ -47,6 +50,9 @@ #include "gp10b/fecs_trace_gp10b.h" #include "gp10b/fb_gp10b.h" #include "gp10b/mm_gp10b.h" +#include "gp10b/pmu_gp10b.h" + +#include "gp106/pmu_gp106.h" #include "hal_gv11b.h" #include "gr_gv11b.h" @@ -70,6 +76,7 @@ #include #include #include +#include static int gv11b_get_litter_value(struct gk20a *g, int value) { @@ -368,6 +375,30 @@ static const struct gpu_ops gv11b_ops = { .init_therm_setup_hw = gp10b_init_therm_setup_hw, .elcg_init_idle_filters = gp10b_elcg_init_idle_filters, }, + .pmu = { + .pmu_setup_elpg = gp10b_pmu_setup_elpg, + .pmu_get_queue_head = pwr_pmu_queue_head_r, + .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, + .pmu_get_queue_tail = pwr_pmu_queue_tail_r, + .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, + .pmu_queue_head = gk20a_pmu_queue_head, + .pmu_queue_tail = gk20a_pmu_queue_tail, + .pmu_msgq_tail = gk20a_pmu_msgq_tail, + .pmu_mutex_size = pwr_pmu_mutex__size_1_v, + .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, + .pmu_mutex_release = gk20a_pmu_mutex_release, + .write_dmatrfbase = gp10b_write_dmatrfbase, + .pmu_elpg_statistics = gp106_pmu_elpg_statistics, + .pmu_pg_init_param = gv11b_pg_gr_init, + .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, + .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, + .dump_secure_fuses = pmu_dump_security_fuses_gp10b, + .reset_engine = gp106_pmu_engine_reset, + .is_engine_in_reset = gp106_pmu_is_engine_in_reset, + .pmu_nsbootstrap = gv11b_pmu_bootstrap, + .pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask, + .is_pmu_supported = gv11b_is_pmu_supported, + }, .regops = { .get_global_whitelist_ranges = gv11b_get_global_whitelist_ranges, @@ -463,6 +494,7 @@ int gv11b_init_hal(struct gk20a *g) gops->mm = gv11b_ops.mm; gops->fecs_trace = gv11b_ops.fecs_trace; gops->therm = gv11b_ops.therm; + gops->pmu = gv11b_ops.pmu; gops->regops = gv11b_ops.regops; gops->mc = gv11b_ops.mc; gops->debug = gv11b_ops.debug; @@ -479,13 +511,44 @@ int gv11b_init_hal(struct gk20a *g) gv11b_ops.chip_init_gpu_characteristics; gops->get_litter_value = gv11b_ops.get_litter_value; - /* boot in non-secure modes for time beeing */ + /* boot in non-secure modes for time being */ __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false); __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); + /* priv security dependent ops */ + if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { + /* Add in ops from gm20b acr */ + gops->pmu.prepare_ucode = prepare_ucode_blob, + gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn, + gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap, + gops->pmu.is_priv_load = gm20b_is_priv_load, + gops->pmu.get_wpr = gm20b_wpr_info, + gops->pmu.alloc_blob_space = gm20b_alloc_blob_space, + gops->pmu.pmu_populate_loader_cfg = + gm20b_pmu_populate_loader_cfg, + gops->pmu.flcn_populate_bl_dmem_desc = + gm20b_flcn_populate_bl_dmem_desc, + gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt, + gops->pmu.falcon_clear_halt_interrupt_status = + clear_halt_interrupt_status, + gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1, + + gops->pmu.init_wpr_region = gm20b_pmu_init_acr; + gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; + gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap; + gops->pmu.is_priv_load = gp10b_is_priv_load; + } else { + /* Inherit from gk20a */ + gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, + gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1, + + gops->pmu.load_lsfalcon_ucode = NULL; + gops->pmu.init_wpr_region = NULL; + gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; + } + gv11b_init_gr(g); - gv11b_init_pmu_ops(g); gv11b_init_uncompressed_kind_map(); gv11b_init_kind_attr(); diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 35719dff..2b89fbcc 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c @@ -36,12 +36,12 @@ #define ALIGN_4KB 12 -static bool gv11b_is_pmu_supported(struct gk20a *g) +bool gv11b_is_pmu_supported(struct gk20a *g) { return true; } -static int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu) +int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu) { struct gk20a *g = gk20a_from_pmu(pmu); struct mm_gk20a *mm = &g->mm; @@ -178,7 +178,7 @@ static void pmu_handle_pg_param_msg(struct gk20a *g, struct pmu_msg *msg, msg->msg.pg.msg_type); } -static int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) +int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) { struct nvgpu_pmu *pmu = &g->pmu; struct pmu_cmd cmd; @@ -206,7 +206,7 @@ static int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) return 0; } -static int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id) +int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id) { struct nvgpu_pmu *pmu = &g->pmu; struct pmu_cmd cmd; @@ -234,27 +234,3 @@ static int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id) return 0; } - -void gv11b_init_pmu_ops(struct gk20a *g) -{ - struct gpu_ops *gops = &g->ops; - - gp10b_init_pmu_ops(g); - gops->pmu.pmu_nsbootstrap = gv11b_pmu_bootstrap; - gops->pmu.is_pmu_supported = gv11b_is_pmu_supported; - gops->pmu.reset_engine = gp106_pmu_engine_reset; - gops->pmu.is_engine_in_reset = gp106_pmu_is_engine_in_reset; - gops->pmu.pmu_get_queue_head = pwr_pmu_queue_head_r; - gops->pmu.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v; - gops->pmu.pmu_get_queue_tail = pwr_pmu_queue_tail_r; - gops->pmu.pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v; - gops->pmu.pmu_queue_head = gk20a_pmu_queue_head; - gops->pmu.pmu_queue_tail = gk20a_pmu_queue_tail; - gops->pmu.pmu_mutex_acquire = gk20a_pmu_mutex_acquire; - gops->pmu.pmu_mutex_release = gk20a_pmu_mutex_release; - gops->pmu.pmu_msgq_tail = gk20a_pmu_msgq_tail; - gops->pmu.pmu_mutex_size = pwr_pmu_mutex__size_1_v; - gops->pmu.pmu_elpg_statistics = gp106_pmu_elpg_statistics; - gops->pmu.pmu_pg_init_param = gv11b_pg_gr_init; - gops->pmu.pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask; -} diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h index ce10c4cb..03fec2a3 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h @@ -18,6 +18,9 @@ struct gk20a; -void gv11b_init_pmu_ops(struct gk20a *g); +bool gv11b_is_pmu_supported(struct gk20a *g); +int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu); +int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id); +int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id); #endif /*__PMU_GV11B_H_*/ -- cgit v1.2.2