From 98dce7eaac374ccd5c4d7cf6d76decc4e9cd3896 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Tue, 17 Apr 2018 17:26:34 -0700 Subject: gpu: nvgpu: move mss nvlink credit init to os specific code The code uses ioremap, readl_relaxed/writel_relaxed, which only exists on linux. So move them to linux folder. Also fix build errors on qnx. Jira VQRM-2344 Change-Id: Ide1176d0bf954a804187aa842a6bbfdecbdb0286 Signed-off-by: Richard Zhao Reviewed-on: https://git-master.nvidia.com/r/1698973 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/linux/nvlink.c | 34 +++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 35 ++------------------------------ drivers/gpu/nvgpu/include/nvgpu/nvlink.h | 3 +++ 3 files changed, 39 insertions(+), 33 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/common/linux/nvlink.c b/drivers/gpu/nvgpu/common/linux/nvlink.c index f2faa682..5a2f4ded 100644 --- a/drivers/gpu/nvgpu/common/linux/nvlink.c +++ b/drivers/gpu/nvgpu/common/linux/nvlink.c @@ -539,3 +539,37 @@ free_ndev: #endif } +void nvgpu_mss_nvlink_init_credits(struct gk20a *g) +{ + /* MSS_NVLINK_1_BASE */ + void __iomem *soc1 = ioremap(0x01f20010, 4096); + /* MSS_NVLINK_2_BASE */ + void __iomem *soc2 = ioremap(0x01f40010, 4096); + /* MSS_NVLINK_3_BASE */ + void __iomem *soc3 = ioremap(0x01f60010, 4096); + /* MSS_NVLINK_4_BASE */ + void __iomem *soc4 = ioremap(0x01f80010, 4096); + u32 val; + + nvgpu_log(g, gpu_dbg_info, "init nvlink soc credits"); + + val = readl_relaxed(soc1); + writel_relaxed(val, soc1); + val = readl_relaxed(soc1 + 4); + writel_relaxed(val, soc1 + 4); + + val = readl_relaxed(soc2); + writel_relaxed(val, soc2); + val = readl_relaxed(soc2 + 4); + writel_relaxed(val, soc2 + 4); + + val = readl_relaxed(soc3); + writel_relaxed(val, soc3); + val = readl_relaxed(soc3 + 4); + writel_relaxed(val, soc3 + 4); + + val = readl_relaxed(soc4); + writel_relaxed(val, soc4); + val = readl_relaxed(soc4 + 4); + writel_relaxed(val, soc4 + 4); +} diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 4ad350d1..30a2bca2 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -22,13 +22,12 @@ * DEALINGS IN THE SOFTWARE. */ -#include - #include #include #include #include #include +#include #include #include "gk20a/gk20a.h" @@ -57,37 +56,7 @@ static void gv11b_init_nvlink_soc_credits(struct gk20a *g) nvgpu_log(g, gpu_dbg_info, "nvlink soc credits init done by bpmp"); } else { #ifndef __NVGPU_POSIX__ - /* MSS_NVLINK_1_BASE */ - void __iomem *soc1 = ioremap(0x01f20010, 4096); - /* MSS_NVLINK_2_BASE */ - void __iomem *soc2 = ioremap(0x01f40010, 4096); - /* MSS_NVLINK_3_BASE */ - void __iomem *soc3 = ioremap(0x01f60010, 4096); - /* MSS_NVLINK_4_BASE */ - void __iomem *soc4 = ioremap(0x01f80010, 4096); - u32 val; - - nvgpu_log(g, gpu_dbg_info, "init nvlink soc credits"); - - val = readl_relaxed(soc1); - writel_relaxed(val, soc1); - val = readl_relaxed(soc1 + 4); - writel_relaxed(val, soc1 + 4); - - val = readl_relaxed(soc2); - writel_relaxed(val, soc2); - val = readl_relaxed(soc2 + 4); - writel_relaxed(val, soc2 + 4); - - val = readl_relaxed(soc3); - writel_relaxed(val, soc3); - val = readl_relaxed(soc3 + 4); - writel_relaxed(val, soc3 + 4); - - val = readl_relaxed(soc4); - writel_relaxed(val, soc4); - val = readl_relaxed(soc4 + 4); - writel_relaxed(val, soc4 + 4); + nvgpu_mss_nvlink_init_credits(g); #endif } } diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvlink.h b/drivers/gpu/nvgpu/include/nvgpu/nvlink.h index 0ef8a2f5..dfa3be3f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/nvlink.h +++ b/drivers/gpu/nvgpu/include/nvgpu/nvlink.h @@ -211,4 +211,7 @@ struct nvgpu_nvlink_dev { int nvgpu_nvlink_enumerate(struct gk20a *g); int nvgpu_nvlink_train(struct gk20a *g, u32 link_id, bool from_off); int nvgpu_nvlink_probe(struct gk20a *g); + +void nvgpu_mss_nvlink_init_credits(struct gk20a *g); + #endif -- cgit v1.2.2