From 959c02d6757c3c40748f7d2db1515885a5066a12 Mon Sep 17 00:00:00 2001 From: Sunny He Date: Mon, 31 Jul 2017 18:54:38 -0700 Subject: gpu: nvgpu: Reorg mm HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the mm sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ieb87a62f047510e51c52e6563d8e3fd5a65b5f28 Signed-off-by: Sunny He Reviewed-on: https://git-master.nvidia.com/r/1537753 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- .../gpu/nvgpu/common/linux/platform_gk20a_tegra.c | 2 +- drivers/gpu/nvgpu/gk20a/gk20a.h | 17 +++++------ drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 12 ++++---- drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 24 +++++++++++++++- drivers/gpu/nvgpu/gm20b/mm_gm20b.c | 33 ++++------------------ drivers/gpu/nvgpu/gm20b/mm_gm20b.h | 12 +++++--- drivers/gpu/nvgpu/gp106/hal_gp106.c | 29 ++++++++++++++++++- drivers/gpu/nvgpu/gp106/mm_gp106.c | 11 ++------ drivers/gpu/nvgpu/gp106/mm_gp106.h | 6 ++-- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 29 +++++++++++++++++-- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 30 ++++++-------------- drivers/gpu/nvgpu/gp10b/mm_gp10b.h | 19 +++++++++++-- 12 files changed, 136 insertions(+), 88 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/common/linux/platform_gk20a_tegra.c b/drivers/gpu/nvgpu/common/linux/platform_gk20a_tegra.c index 36ca850e..71081be5 100644 --- a/drivers/gpu/nvgpu/common/linux/platform_gk20a_tegra.c +++ b/drivers/gpu/nvgpu/common/linux/platform_gk20a_tegra.c @@ -662,7 +662,7 @@ void gk20a_tegra_idle(struct device *dev) void gk20a_tegra_init_secure_alloc(struct gk20a *g) { - g->ops.mm.secure_alloc = gk20a_tegra_secure_alloc; + g->ops.secure_alloc = gk20a_tegra_secure_alloc; } #ifdef CONFIG_COMMON_CLK diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 7b998204..58558159 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -734,16 +734,17 @@ struct gpu_ops { void (*init_inst_block)(struct nvgpu_mem *inst_block, struct vm_gk20a *vm, u32 big_page_size); bool (*mmu_fault_pending)(struct gk20a *g); - /* This function is called to allocate secure memory (memory - * that the CPU cannot see). The function should fill the - * context buffer descriptor (especially fields destroy, sgt, - * size). - */ - int (*secure_alloc)(struct gk20a *g, - struct gr_ctx_buffer_desc *desc, - size_t size); void (*fault_info_mem_destroy)(struct gk20a *g); } mm; + /* + * This function is called to allocate secure memory (memory + * that the CPU cannot see). The function should fill the + * context buffer descriptor (especially fields destroy, sgt, + * size). + */ + int (*secure_alloc)(struct gk20a *g, + struct gr_ctx_buffer_desc *desc, + size_t size); struct { u32 (*enter)(struct gk20a *g, struct nvgpu_mem *mem, struct page_alloc_chunk *chunk, u32 w); diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 497e7ee2..608b011a 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -2524,8 +2524,8 @@ static int gr_gk20a_alloc_global_ctx_buffers(struct gk20a *g) if (err) goto clean_up; - if (g->ops.mm.secure_alloc) - g->ops.mm.secure_alloc(g, + if (g->ops.secure_alloc) + g->ops.secure_alloc(g, &gr->global_ctx_buffer[CIRCULAR_VPR], cb_buffer_size); @@ -2536,8 +2536,8 @@ static int gr_gk20a_alloc_global_ctx_buffers(struct gk20a *g) if (err) goto clean_up; - if (g->ops.mm.secure_alloc) - g->ops.mm.secure_alloc(g, + if (g->ops.secure_alloc) + g->ops.secure_alloc(g, &gr->global_ctx_buffer[PAGEPOOL_VPR], pagepool_buffer_size); @@ -2548,8 +2548,8 @@ static int gr_gk20a_alloc_global_ctx_buffers(struct gk20a *g) if (err) goto clean_up; - if (g->ops.mm.secure_alloc) - g->ops.mm.secure_alloc(g, + if (g->ops.secure_alloc) + g->ops.secure_alloc(g, &gr->global_ctx_buffer[ATTRIBUTE_VPR], attr_buffer_size); diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index a540de64..073c377e 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -19,6 +19,7 @@ #include "gk20a/fb_gk20a.h" #include "gk20a/fifo_gk20a.h" #include "gk20a/therm_gk20a.h" +#include "gk20a/mm_gk20a.h" #include "gk20a/css_gr_gk20a.h" #include "gk20a/mc_gk20a.h" #include "gk20a/bus_gk20a.h" @@ -287,6 +288,27 @@ static const struct gpu_ops gm20b_ops = { .get_netlist_name = gr_gm20b_get_netlist_name, .is_fw_defined = gr_gm20b_is_firmware_defined, }, + .mm = { + .support_sparse = gm20b_mm_support_sparse, + .gmmu_map = gk20a_locked_gmmu_map, + .gmmu_unmap = gk20a_locked_gmmu_unmap, + .vm_bind_channel = gk20a_vm_bind_channel, + .fb_flush = gk20a_mm_fb_flush, + .l2_invalidate = gk20a_mm_l2_invalidate, + .l2_flush = gk20a_mm_l2_flush, + .cbc_clean = gk20a_mm_cbc_clean, + .set_big_page_size = gm20b_mm_set_big_page_size, + .get_big_page_sizes = gm20b_mm_get_big_page_sizes, + .get_default_big_page_size = gm20b_mm_get_default_big_page_size, + .gpu_phys_addr = gm20b_gpu_phys_addr, + .get_physical_addr_bits = gk20a_mm_get_physical_addr_bits, + .get_mmu_levels = gk20a_mm_get_mmu_levels, + .init_pdb = gk20a_mm_init_pdb, + .init_mm_setup_hw = gk20a_init_mm_setup_hw, + .is_bar1_supported = gm20b_mm_is_bar1_supported, + .init_inst_block = gk20a_init_inst_block, + .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, + }, .therm = { .init_therm_setup_hw = gm20b_init_therm_setup_hw, .elcg_init_idle_filters = gk20a_elcg_init_idle_filters, @@ -398,6 +420,7 @@ int gm20b_init_hal(struct gk20a *g) gops->clock_gating = gm20b_ops.clock_gating; gops->fifo = gm20b_ops.fifo; gops->gr_ctx = gm20b_ops.gr_ctx; + gops->mm = gm20b_ops.mm; gops->therm = gm20b_ops.therm; /* * clk must be assigned member by member @@ -462,7 +485,6 @@ int gm20b_init_hal(struct gk20a *g) #endif g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; gm20b_init_gr(g); - gm20b_init_mm(gops); gm20b_init_pmu_ops(g); gm20b_init_uncompressed_kind_map(); diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c index bbcd6314..05752f03 100644 --- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c @@ -20,7 +20,7 @@ #include #include -static void gm20b_mm_set_big_page_size(struct gk20a *g, +void gm20b_mm_set_big_page_size(struct gk20a *g, struct nvgpu_mem *mem, int size) { u32 val; @@ -40,22 +40,22 @@ static void gm20b_mm_set_big_page_size(struct gk20a *g, gk20a_dbg_fn("done"); } -static u32 gm20b_mm_get_big_page_sizes(void) +u32 gm20b_mm_get_big_page_sizes(void) { return SZ_64K | SZ_128K; } -static u32 gm20b_mm_get_default_big_page_size(void) +u32 gm20b_mm_get_default_big_page_size(void) { return SZ_128K; } -static bool gm20b_mm_support_sparse(struct gk20a *g) +bool gm20b_mm_support_sparse(struct gk20a *g) { return true; } -static bool gm20b_mm_is_bar1_supported(struct gk20a *g) +bool gm20b_mm_is_bar1_supported(struct gk20a *g) { return true; } @@ -65,26 +65,3 @@ u64 gm20b_gpu_phys_addr(struct gk20a *g, { return phys; } - -void gm20b_init_mm(struct gpu_ops *gops) -{ - gops->mm.support_sparse = gm20b_mm_support_sparse; - gops->mm.gmmu_map = gk20a_locked_gmmu_map; - gops->mm.gmmu_unmap = gk20a_locked_gmmu_unmap; - gops->mm.vm_bind_channel = gk20a_vm_bind_channel; - gops->mm.fb_flush = gk20a_mm_fb_flush; - gops->mm.l2_invalidate = gk20a_mm_l2_invalidate; - gops->mm.l2_flush = gk20a_mm_l2_flush; - gops->mm.cbc_clean = gk20a_mm_cbc_clean; - gops->mm.set_big_page_size = gm20b_mm_set_big_page_size; - gops->mm.get_big_page_sizes = gm20b_mm_get_big_page_sizes; - gops->mm.get_default_big_page_size = gm20b_mm_get_default_big_page_size; - gops->mm.gpu_phys_addr = gm20b_gpu_phys_addr; - gops->mm.get_physical_addr_bits = gk20a_mm_get_physical_addr_bits; - gops->mm.get_mmu_levels = gk20a_mm_get_mmu_levels; - gops->mm.init_pdb = gk20a_mm_init_pdb; - gops->mm.init_mm_setup_hw = gk20a_init_mm_setup_hw; - gops->mm.is_bar1_supported = gm20b_mm_is_bar1_supported; - gops->mm.init_inst_block = gk20a_init_inst_block; - gops->mm.mmu_fault_pending = gk20a_fifo_mmu_fault_pending; -} diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.h b/drivers/gpu/nvgpu/gm20b/mm_gm20b.h index 2bb29ea8..b1bb38a3 100644 --- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.h @@ -1,7 +1,7 @@ /* * GM20B GMMU * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -20,9 +20,13 @@ struct gk20a; #define PDE_ADDR_START(x, y) ((x) & ~((0x1UL << (y)) - 1)) #define PDE_ADDR_END(x, y) ((x) | ((0x1UL << (y)) - 1)) +void gm20b_mm_set_big_page_size(struct gk20a *g, + struct nvgpu_mem *mem, int size); +u32 gm20b_mm_get_big_page_sizes(void); +u32 gm20b_mm_get_default_big_page_size(void); +bool gm20b_mm_support_sparse(struct gk20a *g); +bool gm20b_mm_is_bar1_supported(struct gk20a *g); +int gm20b_mm_mmu_vpr_info_fetch(struct gk20a *g); u64 gm20b_gpu_phys_addr(struct gk20a *g, struct nvgpu_gmmu_attrs *attrs, u64 phys); - -void gm20b_init_mm(struct gpu_ops *gops); -int gm20b_mm_mmu_vpr_info_fetch(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 361a7b0f..6a50be34 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -17,6 +17,7 @@ #include "gk20a/fifo_gk20a.h" #include "gk20a/ctxsw_trace_gk20a.h" #include "gk20a/fecs_trace_gk20a.h" +#include "gk20a/mm_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/css_gr_gk20a.h" #include "gk20a/bus_gk20a.h" @@ -44,6 +45,7 @@ #include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/fifo_gm20b.h" +#include "gm20b/mm_gm20b.h" #include "gm20b/pmu_gm20b.h" #include "gm20b/fb_gm20b.h" @@ -356,6 +358,31 @@ static const struct gpu_ops gp106_ops = { .max_entries = gk20a_gr_max_entries, }, #endif /* CONFIG_GK20A_CTXSW_TRACE */ + .mm = { + .support_sparse = gm20b_mm_support_sparse, + .gmmu_map = gk20a_locked_gmmu_map, + .gmmu_unmap = gk20a_locked_gmmu_unmap, + .vm_bind_channel = gk20a_vm_bind_channel, + .fb_flush = gk20a_mm_fb_flush, + .l2_invalidate = gk20a_mm_l2_invalidate, + .l2_flush = gk20a_mm_l2_flush, + .cbc_clean = gk20a_mm_cbc_clean, + .set_big_page_size = gm20b_mm_set_big_page_size, + .get_big_page_sizes = gm20b_mm_get_big_page_sizes, + .get_default_big_page_size = gp10b_mm_get_default_big_page_size, + .gpu_phys_addr = gm20b_gpu_phys_addr, + .get_physical_addr_bits = NULL, + .get_mmu_levels = gp10b_mm_get_mmu_levels, + .init_pdb = gp10b_mm_init_pdb, + .init_mm_setup_hw = gp10b_init_mm_setup_hw, + .is_bar1_supported = gm20b_mm_is_bar1_supported, + .init_inst_block = gk20a_init_inst_block, + .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, + .init_bar2_vm = gb10b_init_bar2_vm, + .init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup, + .remove_bar2_vm = gp10b_remove_bar2_vm, + .get_vidmem_size = gp106_mm_get_vidmem_size, + }, .pramin = { .enter = gk20a_pramin_enter, .exit = gk20a_pramin_exit, @@ -502,6 +529,7 @@ int gp106_init_hal(struct gk20a *g) gops->fifo = gp106_ops.fifo; gops->gr_ctx = gp106_ops.gr_ctx; gops->fecs_trace = gp106_ops.fecs_trace; + gops->mm = gp106_ops.mm; gops->pramin = gp106_ops.pramin; gops->therm = gp106_ops.therm; /* @@ -543,7 +571,6 @@ int gp106_init_hal(struct gk20a *g) g->bootstrap_owner = LSF_FALCON_ID_SEC2; gp106_init_gr(g); - gp106_init_mm(gops); gp106_init_pmu_ops(g); gp10b_init_uncompressed_kind_map(); diff --git a/drivers/gpu/nvgpu/gp106/mm_gp106.c b/drivers/gpu/nvgpu/gp106/mm_gp106.c index b7d7e8b8..82c58e97 100644 --- a/drivers/gpu/nvgpu/gp106/mm_gp106.c +++ b/drivers/gpu/nvgpu/gp106/mm_gp106.c @@ -1,7 +1,7 @@ /* * GP106 memory management * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -19,7 +19,7 @@ #include -static size_t gp106_mm_get_vidmem_size(struct gk20a *g) +size_t gp106_mm_get_vidmem_size(struct gk20a *g) { u32 range = gk20a_readl(g, fb_mmu_local_memory_range_r()); u32 mag = fb_mmu_local_memory_range_lower_mag_v(range); @@ -32,10 +32,3 @@ static size_t gp106_mm_get_vidmem_size(struct gk20a *g) return bytes; } - -void gp106_init_mm(struct gpu_ops *gops) -{ - gp10b_init_mm(gops); - gops->mm.get_vidmem_size = gp106_mm_get_vidmem_size; - gops->mm.get_physical_addr_bits = NULL; -} diff --git a/drivers/gpu/nvgpu/gp106/mm_gp106.h b/drivers/gpu/nvgpu/gp106/mm_gp106.h index 36a89a11..73b128a6 100644 --- a/drivers/gpu/nvgpu/gp106/mm_gp106.h +++ b/drivers/gpu/nvgpu/gp106/mm_gp106.h @@ -1,7 +1,7 @@ /* * GP106 memory management * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,8 +16,8 @@ #ifndef MM_GP106_H #define MM_GP106_H -struct gpu_ops; +struct gk20a; -void gp106_init_mm(struct gpu_ops *gops); +size_t gp106_mm_get_vidmem_size(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index b0871155..a37295bb 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -17,6 +17,7 @@ #include "gk20a/fifo_gk20a.h" #include "gk20a/ctxsw_trace_gk20a.h" #include "gk20a/fecs_trace_gk20a.h" +#include "gk20a/mm_gk20a.h" #include "gk20a/dbg_gpu_gk20a.h" #include "gk20a/css_gr_gk20a.h" #include "gk20a/bus_gk20a.h" @@ -47,8 +48,8 @@ #include "gm20b/fifo_gm20b.h" #include "gm20b/pmu_gm20b.h" #include "gm20b/clk_gm20b.h" -#include "gm20b/fifo_gm20b.h" #include "gm20b/fb_gm20b.h" +#include "gm20b/mm_gm20b.h" #include "gp10b.h" #include "hal_gp10b.h" @@ -319,6 +320,30 @@ static const struct gpu_ops gp10b_ops = { .max_entries = gk20a_gr_max_entries, }, #endif /* CONFIG_GK20A_CTXSW_TRACE */ + .mm = { + .support_sparse = gm20b_mm_support_sparse, + .gmmu_map = gk20a_locked_gmmu_map, + .gmmu_unmap = gk20a_locked_gmmu_unmap, + .vm_bind_channel = gk20a_vm_bind_channel, + .fb_flush = gk20a_mm_fb_flush, + .l2_invalidate = gk20a_mm_l2_invalidate, + .l2_flush = gk20a_mm_l2_flush, + .cbc_clean = gk20a_mm_cbc_clean, + .set_big_page_size = gm20b_mm_set_big_page_size, + .get_big_page_sizes = gm20b_mm_get_big_page_sizes, + .get_default_big_page_size = gp10b_mm_get_default_big_page_size, + .gpu_phys_addr = gm20b_gpu_phys_addr, + .get_physical_addr_bits = gp10b_mm_get_physical_addr_bits, + .get_mmu_levels = gp10b_mm_get_mmu_levels, + .init_pdb = gp10b_mm_init_pdb, + .init_mm_setup_hw = gp10b_init_mm_setup_hw, + .is_bar1_supported = gm20b_mm_is_bar1_supported, + .init_inst_block = gk20a_init_inst_block, + .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, + .init_bar2_vm = gb10b_init_bar2_vm, + .init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup, + .remove_bar2_vm = gp10b_remove_bar2_vm, + }, .pramin = { .enter = gk20a_pramin_enter, .exit = gk20a_pramin_exit, @@ -427,6 +452,7 @@ int gp10b_init_hal(struct gk20a *g) gops->fifo = gp10b_ops.fifo; gops->gr_ctx = gp10b_ops.gr_ctx; gops->fecs_trace = gp10b_ops.fecs_trace; + gops->mm = gp10b_ops.mm; gops->pramin = gp10b_ops.pramin; gops->therm = gp10b_ops.therm; gops->regops = gp10b_ops.regops; @@ -489,7 +515,6 @@ int gp10b_init_hal(struct gk20a *g) g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; gp10b_init_gr(g); - gp10b_init_mm(gops); gp10b_init_pmu_ops(g); gp10b_init_uncompressed_kind_map(); diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 9aa72e64..6b629ecf 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -27,17 +27,17 @@ #include #include -static u32 gp10b_mm_get_default_big_page_size(void) +u32 gp10b_mm_get_default_big_page_size(void) { return SZ_64K; } -static u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g) +u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g) { return 36; } -static int gp10b_init_mm_setup_hw(struct gk20a *g) +int gp10b_init_mm_setup_hw(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; struct nvgpu_mem *inst_block = &mm->bar1.inst_block; @@ -68,7 +68,7 @@ static int gp10b_init_mm_setup_hw(struct gk20a *g) } -static int gb10b_init_bar2_vm(struct gk20a *g) +int gb10b_init_bar2_vm(struct gk20a *g) { int err; struct mm_gk20a *mm = &g->mm; @@ -99,7 +99,7 @@ clean_up_va: return err; } -static int gb10b_init_bar2_mm_hw_setup(struct gk20a *g) +int gb10b_init_bar2_mm_hw_setup(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; struct nvgpu_mem *inst_block = &mm->bar2.inst_block; @@ -333,13 +333,13 @@ static const struct gk20a_mmu_level gp10b_mm_levels[] = { {.update_entry = NULL} }; -static const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g, +const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g, u32 big_page_size) { return gp10b_mm_levels; } -static void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, +void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, struct vm_gk20a *vm) { u64 pdb_addr = nvgpu_mem_get_addr(g, vm->pdb.mem); @@ -360,7 +360,7 @@ static void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, ram_in_page_dir_base_hi_f(pdb_addr_hi)); } -static void gp10b_remove_bar2_vm(struct gk20a *g) +void gp10b_remove_bar2_vm(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; @@ -368,17 +368,3 @@ static void gp10b_remove_bar2_vm(struct gk20a *g) gk20a_free_inst_block(g, &mm->bar2.inst_block); nvgpu_vm_put(mm->bar2.vm); } - - -void gp10b_init_mm(struct gpu_ops *gops) -{ - gm20b_init_mm(gops); - gops->mm.get_default_big_page_size = gp10b_mm_get_default_big_page_size; - gops->mm.get_physical_addr_bits = gp10b_mm_get_physical_addr_bits; - gops->mm.init_mm_setup_hw = gp10b_init_mm_setup_hw; - gops->mm.init_bar2_vm = gb10b_init_bar2_vm; - gops->mm.init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup; - gops->mm.get_mmu_levels = gp10b_mm_get_mmu_levels; - gops->mm.init_pdb = gp10b_mm_init_pdb; - gops->mm.remove_bar2_vm = gp10b_remove_bar2_vm; -} diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h index 4cc71ea6..a0b9acd6 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -14,7 +14,20 @@ #ifndef MM_GP10B_H #define MM_GP10B_H -struct gpu_ops; +struct gk20a; +struct gk20a_mmu_level; +struct nvgpu_mem; +struct vm_gk20a; + +u32 gp10b_mm_get_default_big_page_size(void); +u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g); +int gp10b_init_mm_setup_hw(struct gk20a *g); +int gb10b_init_bar2_vm(struct gk20a *g); +int gb10b_init_bar2_mm_hw_setup(struct gk20a *g); +const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g, + u32 big_page_size); +void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, + struct vm_gk20a *vm); +void gp10b_remove_bar2_vm(struct gk20a *g); -void gp10b_init_mm(struct gpu_ops *gops); #endif -- cgit v1.2.2