From 8fe633449f92d35b60a60de647a4e8fc1b5c8936 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 9 Nov 2017 14:13:25 -0800 Subject: gpu: nvgpu: Add check_priv_security fuse ops -New fuse ops is added to set NVGPU_SEC_PRIVSECURITY and NVGPU_SEC_SECUREGPCCS bits in g->enabled_flags during hal initialization -For igpu non simulation platforms, fuses are read to decide if gpu should be allowed to boot or not. --Do not boot gpu if priv_sec_en is set but wpr_enabled is not set to 1 or vpr_auto_fetch_disable is not set to 0 --With priv_sec_en set, all falcons have to boot in LS mode and this needs wpr_enabled set to 1 AND vpr_auto_fetch_disable set to 0. In this case gmmu tries to pull wpr and vpr settings from tegra mc Bug 2018223 Change-Id: Iceaa1b0b3214e9a3d6cef5d77a82e034302f748b Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1595454 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 5 ++ .../common/linux/vgpu/gm20b/vgpu_fuse_gm20b.c | 37 +++++++++ .../common/linux/vgpu/gm20b/vgpu_fuse_gm20b.h | 30 +++++++ .../nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c | 22 +++--- .../common/linux/vgpu/gp10b/vgpu_fuse_gp10b.c | 38 +++++++++ .../common/linux/vgpu/gp10b/vgpu_fuse_gp10b.h | 30 +++++++ .../nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c | 27 +++---- drivers/gpu/nvgpu/gk20a/gk20a.h | 4 + drivers/gpu/nvgpu/gm20b/fuse_gm20b.c | 90 +++++++++++++++++++++ drivers/gpu/nvgpu/gm20b/fuse_gm20b.h | 37 +++++++++ drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 22 +++--- drivers/gpu/nvgpu/gp106/fuse_gp106.c | 35 +++++++++ drivers/gpu/nvgpu/gp106/fuse_gp106.h | 32 ++++++++ drivers/gpu/nvgpu/gp106/hal_gp106.c | 11 ++- drivers/gpu/nvgpu/gp10b/fuse_gp10b.c | 91 ++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/fuse_gp10b.h | 32 ++++++++ drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 27 +++---- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 21 +++-- 18 files changed, 515 insertions(+), 76 deletions(-) create mode 100644 drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.c create mode 100644 drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.h create mode 100644 drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.c create mode 100644 drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.h create mode 100644 drivers/gpu/nvgpu/gm20b/fuse_gm20b.c create mode 100644 drivers/gpu/nvgpu/gm20b/fuse_gm20b.h create mode 100644 drivers/gpu/nvgpu/gp106/fuse_gp106.c create mode 100644 drivers/gpu/nvgpu/gp106/fuse_gp106.h create mode 100644 drivers/gpu/nvgpu/gp10b/fuse_gp10b.c create mode 100644 drivers/gpu/nvgpu/gp10b/fuse_gp10b.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 72946fc0..a4ef22e5 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -114,6 +114,7 @@ nvgpu-y := \ gm20b/mm_gm20b.o \ gm20b/regops_gm20b.o \ gm20b/therm_gm20b.o \ + gm20b/fuse_gm20b.o \ boardobj/boardobj.o \ boardobj/boardobjgrp.o \ boardobj/boardobjgrpmask.o \ @@ -166,6 +167,7 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ common/linux/vgpu/css_vgpu.o \ common/linux/vgpu/gm20b/vgpu_hal_gm20b.o \ common/linux/vgpu/gm20b/vgpu_gr_gm20b.o \ + common/linux/vgpu/gm20b/vgpu_fuse_gm20b.o \ common/linux/vgpu/sysfs_vgpu.o nvgpu-$(CONFIG_COMMON_CLK) += \ @@ -195,6 +197,7 @@ nvgpu-y += \ gp10b/fecs_trace_gp10b.o \ gp10b/priv_ring_gp10b.o \ gp10b/gp10b.o \ + gp10b/fuse_gp10b.o \ gp106/hal_gp106.o \ gp106/mm_gp106.o \ gp106/flcn_gp106.o \ @@ -208,6 +211,7 @@ nvgpu-y += \ gp106/fb_gp106.o \ gp106/regops_gp106.o \ gp106/bios_gp106.o \ + gp106/fuse_gp106.o \ pstate/pstate.o \ clk/clk_vin.o \ clk/clk_fll.o \ @@ -247,6 +251,7 @@ nvgpu-$(CONFIG_TEGRA_GK20A) += common/linux/platform_gp10b_tegra.o nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ common/linux/vgpu/gp10b/vgpu_hal_gp10b.o \ common/linux/vgpu/gp10b/vgpu_gr_gp10b.o \ + common/linux/vgpu/gp10b/vgpu_fuse_gp10b.o \ common/linux/vgpu/gp10b/vgpu_mm_gp10b.o ifeq ($(CONFIG_ARCH_TEGRA_19x_SOC),y) diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.c new file mode 100644 index 00000000..2ab745ab --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.c @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +#include "gk20a/gk20a.h" + +int vgpu_gm20b_fuse_check_priv_security(struct gk20a *g) +{ + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); + + if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); + else + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); + + return 0; +} diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.h new file mode 100644 index 00000000..39da09fa --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _VGPU_GM20B_FUSE +#define _VGPU_GM20B_FUSE + +struct gk20a; + +int vgpu_gm20b_fuse_check_priv_security(struct gk20a *g); + +#endif diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c index b9d3f734..0e560981 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c @@ -24,6 +24,7 @@ #include "common/linux/vgpu/fecs_trace_vgpu.h" #include "common/linux/vgpu/css_vgpu.h" #include "vgpu_gr_gm20b.h" +#include "vgpu_fuse_gm20b.h" #include "gk20a/bus_gk20a.h" #include "gk20a/flcn_gk20a.h" @@ -456,6 +457,9 @@ static const struct gpu_ops vgpu_gm20b_ops = { .priv_ring = { .isr = gk20a_priv_ring_isr, }, + .fuse = { + .check_priv_security = vgpu_gm20b_fuse_check_priv_security, + }, .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics, .get_litter_value = gm20b_get_litter_value, }; @@ -463,7 +467,6 @@ static const struct gpu_ops vgpu_gm20b_ops = { int vgpu_gm20b_init_hal(struct gk20a *g) { struct gpu_ops *gops = &g->ops; - u32 val; gops->ltc = vgpu_gm20b_ops.ltc; gops->ce2 = vgpu_gm20b_ops.ce2; @@ -499,26 +502,19 @@ int vgpu_gm20b_init_hal(struct gk20a *g) gops->priv_ring = vgpu_gm20b_ops.priv_ring; + gops->fuse = vgpu_gm20b_ops.fuse; + /* Lone functions */ gops->chip_init_gpu_characteristics = vgpu_gm20b_ops.chip_init_gpu_characteristics; gops->get_litter_value = vgpu_gm20b_ops.get_litter_value; __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); - __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); - if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); - } else { - val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); - if (!val) { - gk20a_dbg_info("priv security is disabled in HW"); - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); - } else { - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); - } - } + /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ + if (gops->fuse.check_priv_security(g)) + return -EINVAL; /* Do not boot gpu */ /* priv security dependent ops */ if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.c new file mode 100644 index 00000000..5ee5d1f6 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.c @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +#include "gk20a/gk20a.h" + +int vgpu_gp10b_fuse_check_priv_security(struct gk20a *g) +{ + if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); + } else { + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); + } + + return 0; +} diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.h new file mode 100644 index 00000000..2ec8f284 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _VGPU_GP10B_FUSE +#define _VGPU_GP10B_FUSE + +struct gk20a; + +int vgpu_gp10b_fuse_check_priv_security(struct gk20a *g); + +#endif diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c index 78f88d4d..b35cac90 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c @@ -27,6 +27,7 @@ #include "common/linux/vgpu/gm20b/vgpu_gr_gm20b.h" #include "vgpu_gr_gp10b.h" #include "vgpu_mm_gp10b.h" +#include "vgpu_fuse_gp10b.h" #include "gk20a/bus_gk20a.h" #include "gk20a/pramin_gk20a.h" @@ -498,6 +499,9 @@ static const struct gpu_ops vgpu_gp10b_ops = { .priv_ring = { .isr = gp10b_priv_ring_isr, }, + .fuse = { + .check_priv_security = vgpu_gp10b_fuse_check_priv_security, + }, .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics, .get_litter_value = gp10b_get_litter_value, }; @@ -505,7 +509,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { int vgpu_gp10b_init_hal(struct gk20a *g) { struct gpu_ops *gops = &g->ops; - u32 val; gops->ltc = vgpu_gp10b_ops.ltc; gops->ce2 = vgpu_gp10b_ops.ce2; @@ -531,6 +534,8 @@ int vgpu_gp10b_init_hal(struct gk20a *g) gops->priv_ring = vgpu_gp10b_ops.priv_ring; + gops->fuse = vgpu_gp10b_ops.fuse; + /* Lone Functions */ gops->chip_init_gpu_characteristics = vgpu_gp10b_ops.chip_init_gpu_characteristics; @@ -539,23 +544,9 @@ int vgpu_gp10b_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); - if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); - __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); - } else if (g->is_virtual) { - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); - __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); - } else { - val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); - if (val) { - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); - __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); - } else { - gk20a_dbg_info("priv security is disabled in HW"); - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); - __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); - } - } + /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ + if (gops->fuse.check_priv_security(g)) + return -EINVAL; /* Do not boot gpu */ /* priv security dependent ops */ if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 8d8bfbec..8d6db4c7 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -1024,6 +1024,10 @@ struct gpu_ops { struct { void (*isr)(struct gk20a *g); } priv_ring; + struct { + int (*check_priv_security)(struct gk20a *g); + } fuse; + }; struct nvgpu_bios_ucode { diff --git a/drivers/gpu/nvgpu/gm20b/fuse_gm20b.c b/drivers/gpu/nvgpu/gm20b/fuse_gm20b.c new file mode 100644 index 00000000..165d5b43 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/fuse_gm20b.c @@ -0,0 +1,90 @@ +/* + * GM20B FUSE + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include "gk20a/gk20a.h" + +#include "fuse_gm20b.h" + +#include + +int gm20b_fuse_check_priv_security(struct gk20a *g) +{ + u32 gcplex_config; + + if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); + nvgpu_log(g, gpu_dbg_info, "priv sec is enabled in fmodel"); + return 0; + } + + if (nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &gcplex_config)) { + nvgpu_err(g, "err reading gcplex config fuse, check fuse clk"); + return -EINVAL; + } + + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); + + if (gk20a_readl(g, fuse_opt_priv_sec_en_r())) { + /* + * all falcons have to boot in LS mode and this needs + * wpr_enabled set to 1 and vpr_auto_fetch_disable + * set to 0. In this case gmmu tries to pull wpr + * and vpr settings from tegra mc + */ + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); + if ((gcplex_config & + GCPLEX_CONFIG_WPR_ENABLED_MASK) && + !(gcplex_config & + GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK)) { + if (gk20a_readl(g, fuse_opt_sec_debug_en_r())) + nvgpu_log(g, gpu_dbg_info, + "gcplex_config = 0x%08x, " + "secure mode: ACR debug", + gcplex_config); + else + nvgpu_log(g, gpu_dbg_info, + "gcplex_config = 0x%08x, " + "secure mode: ACR non debug", + gcplex_config); + } else { + nvgpu_err(g, "gcplex_config = 0x%08x " + "invalid wpr_enabled/vpr_auto_fetch_disable " + "with priv_sec_en", gcplex_config); + /* do not try to boot GPU */ + return -EINVAL; + } + } else { + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); + nvgpu_log(g, gpu_dbg_info, + "gcplex_config = 0x%08x, non secure mode", + gcplex_config); + } + + return 0; +} diff --git a/drivers/gpu/nvgpu/gm20b/fuse_gm20b.h b/drivers/gpu/nvgpu/gm20b/fuse_gm20b.h new file mode 100644 index 00000000..51734b2f --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/fuse_gm20b.h @@ -0,0 +1,37 @@ +/* + * GM20B FUSE + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NVGPU_GM20B_FUSE +#define _NVGPU_GM20B_FUSE + +#define GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK ((u32)(1 << 0)) +#define GCPLEX_CONFIG_VPR_ENABLED_MASK ((u32)(1 << 1)) +#define GCPLEX_CONFIG_WPR_ENABLED_MASK ((u32)(1 << 2)) + + +struct gk20a; + +int gm20b_fuse_check_priv_security(struct gk20a *g); + +#endif diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index bb18d2d7..779dde3d 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -54,6 +54,7 @@ #include "bus_gm20b.h" #include "hal_gm20b.h" #include "acr_gm20b.h" +#include "fuse_gm20b.h" #include #include @@ -582,6 +583,9 @@ static const struct gpu_ops gm20b_ops = { .priv_ring = { .isr = gk20a_priv_ring_isr, }, + .fuse = { + .check_priv_security = gm20b_fuse_check_priv_security, + }, .chip_init_gpu_characteristics = gk20a_init_gpu_characteristics, .get_litter_value = gm20b_get_litter_value, }; @@ -589,7 +593,6 @@ static const struct gpu_ops gm20b_ops = { int gm20b_init_hal(struct gk20a *g) { struct gpu_ops *gops = &g->ops; - u32 val; gops->ltc = gm20b_ops.ltc; gops->ce2 = gm20b_ops.ce2; @@ -625,26 +628,19 @@ int gm20b_init_hal(struct gk20a *g) gops->priv_ring = gm20b_ops.priv_ring; + gops->fuse = gm20b_ops.fuse; + /* Lone functions */ gops->chip_init_gpu_characteristics = gm20b_ops.chip_init_gpu_characteristics; gops->get_litter_value = gm20b_ops.get_litter_value; __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); - __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); - if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); - } else { - val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); - if (!val) { - gk20a_dbg_info("priv security is disabled in HW"); - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); - } else { - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); - } - } + /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ + if (gops->fuse.check_priv_security(g)) + return -EINVAL; /* Do not boot gpu */ /* priv security dependent ops */ if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { diff --git a/drivers/gpu/nvgpu/gp106/fuse_gp106.c b/drivers/gpu/nvgpu/gp106/fuse_gp106.c new file mode 100644 index 00000000..68c0db89 --- /dev/null +++ b/drivers/gpu/nvgpu/gp106/fuse_gp106.c @@ -0,0 +1,35 @@ +/* + * GP106 FUSE + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +#include "gk20a/gk20a.h" + +int gp106_fuse_check_priv_security(struct gk20a *g) +{ + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); + + return 0; +} diff --git a/drivers/gpu/nvgpu/gp106/fuse_gp106.h b/drivers/gpu/nvgpu/gp106/fuse_gp106.h new file mode 100644 index 00000000..dfb776b8 --- /dev/null +++ b/drivers/gpu/nvgpu/gp106/fuse_gp106.h @@ -0,0 +1,32 @@ +/* + * GP106 FUSE + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NVGPU_GP106_FUSE +#define _NVGPU_GP106_FUSE + +struct gk20a; + +int gp106_fuse_check_priv_security(struct gk20a *g); + +#endif diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index e9ee77fc..d63398c7 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -79,6 +79,7 @@ #include "gp106/fb_gp106.h" #include "gp106/gp106_gating_reglist.h" #include "gp106/flcn_gp106.h" +#include "gp106/fuse_gp106.h" #include "hal_gp106.h" @@ -704,6 +705,9 @@ static const struct gpu_ops gp106_ops = { .priv_ring = { .isr = gp10b_priv_ring_isr, }, + .fuse = { + .check_priv_security = gp106_fuse_check_priv_security, + }, .get_litter_value = gp106_get_litter_value, .chip_init_gpu_characteristics = gp106_init_gpu_characteristics, }; @@ -753,6 +757,7 @@ int gp106_init_hal(struct gk20a *g) gops->xve = gp106_ops.xve; gops->falcon = gp106_ops.falcon; gops->priv_ring = gp106_ops.priv_ring; + gops->fuse = gp106_ops.fuse; /* Lone functions */ gops->get_litter_value = gp106_ops.get_litter_value; @@ -760,11 +765,13 @@ int gp106_init_hal(struct gk20a *g) gp106_ops.chip_init_gpu_characteristics; __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); - __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); + /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ + if (gops->fuse.check_priv_security(g)) + return -EINVAL; /* Do not boot gpu */ + g->pmu_lsf_pmu_wpr_init_done = 0; g->bootstrap_owner = LSF_FALCON_ID_SEC2; diff --git a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c b/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c new file mode 100644 index 00000000..7743c5df --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c @@ -0,0 +1,91 @@ +/* + * GP10B FUSE + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include "gk20a/gk20a.h" + +#include "gm20b/fuse_gm20b.h" + +#include + +int gp10b_fuse_check_priv_security(struct gk20a *g) +{ + u32 gcplex_config; + + if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); + nvgpu_log(g, gpu_dbg_info, "priv sec is disabled in fmodel"); + return 0; + } + + if (nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &gcplex_config)) { + nvgpu_err(g, "err reading gcplex config fuse, check fuse clk"); + return -EINVAL; + } + + if (gk20a_readl(g, fuse_opt_priv_sec_en_r())) { + /* + * all falcons have to boot in LS mode and this needs + * wpr_enabled set to 1 and vpr_auto_fetch_disable + * set to 0. In this case gmmu tries to pull wpr + * and vpr settings from tegra mc + */ + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); + if ((gcplex_config & + GCPLEX_CONFIG_WPR_ENABLED_MASK) && + !(gcplex_config & + GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK)) { + if (gk20a_readl(g, fuse_opt_sec_debug_en_r())) + nvgpu_log(g, gpu_dbg_info, + "gcplex_config = 0x%08x, " + "secure mode: ACR debug", + gcplex_config); + else + nvgpu_log(g, gpu_dbg_info, + "gcplex_config = 0x%08x, " + "secure mode: ACR non debug", + gcplex_config); + + } else { + nvgpu_err(g, "gcplex_config = 0x%08x " + "invalid wpr_enabled/vpr_auto_fetch_disable " + "with priv_sec_en", gcplex_config); + /* do not try to boot GPU */ + return -EINVAL; + } + } else { + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); + nvgpu_log(g, gpu_dbg_info, + "gcplex_config = 0x%08x, non secure mode", + gcplex_config); + } + + return 0; +} diff --git a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.h b/drivers/gpu/nvgpu/gp10b/fuse_gp10b.h new file mode 100644 index 00000000..1acb45d1 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/fuse_gp10b.h @@ -0,0 +1,32 @@ +/* + * GP10B FUSE + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NVGPU_GP10B_FUSE +#define _NVGPU_GP10B_FUSE + +struct gk20a; + +int gp10b_fuse_check_priv_security(struct gk20a *g); + +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 0b2a5712..335eb465 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -64,6 +64,7 @@ #include "gp10b.h" #include "hal_gp10b.h" +#include "fuse_gp10b.h" #include #include @@ -619,6 +620,9 @@ static const struct gpu_ops gp10b_ops = { .priv_ring = { .isr = gp10b_priv_ring_isr, }, + .fuse = { + .check_priv_security = gp10b_fuse_check_priv_security, + }, .chip_init_gpu_characteristics = gp10b_init_gpu_characteristics, .get_litter_value = gp10b_get_litter_value, }; @@ -626,7 +630,6 @@ static const struct gpu_ops gp10b_ops = { int gp10b_init_hal(struct gk20a *g) { struct gpu_ops *gops = &g->ops; - u32 val; gops->ltc = gp10b_ops.ltc; gops->ce2 = gp10b_ops.ce2; @@ -654,6 +657,8 @@ int gp10b_init_hal(struct gk20a *g) gops->priv_ring = gp10b_ops.priv_ring; + gops->fuse = gp10b_ops.fuse; + /* Lone Functions */ gops->chip_init_gpu_characteristics = gp10b_ops.chip_init_gpu_characteristics; @@ -662,23 +667,9 @@ int gp10b_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); - if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); - __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); - } else if (g->is_virtual) { - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); - __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); - } else { - val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); - if (val) { - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); - __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); - } else { - gk20a_dbg_info("priv security is disabled in HW"); - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); - __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); - } - } + /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ + if (gops->fuse.check_priv_security(g)) + return -EINVAL; /* Do not boot gpu */ /* priv security dependent ops */ if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index fc059caa..8278d4e5 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -61,6 +61,7 @@ #include "gp10b/mm_gp10b.h" #include "gp10b/pmu_gp10b.h" #include "gp10b/gr_gp10b.h" +#include "gp10b/fuse_gp10b.h" #include "gp106/pmu_gp106.h" #include "gp106/acr_gp106.h" @@ -684,6 +685,9 @@ static const struct gpu_ops gv11b_ops = { .priv_ring = { .isr = gp10b_priv_ring_isr, }, + .fuse = { + .check_priv_security = gp10b_fuse_check_priv_security, + }, .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics, .get_litter_value = gv11b_get_litter_value, }; @@ -691,8 +695,6 @@ static const struct gpu_ops gv11b_ops = { int gv11b_init_hal(struct gk20a *g) { struct gpu_ops *gops = &g->ops; - u32 val; - bool priv_security; gops->ltc = gv11b_ops.ltc; gops->ce2 = gv11b_ops.ce2; @@ -717,23 +719,18 @@ int gv11b_init_hal(struct gk20a *g) #endif gops->falcon = gv11b_ops.falcon; gops->priv_ring = gv11b_ops.priv_ring; + gops->fuse = gv11b_ops.fuse; /* Lone functions */ gops->chip_init_gpu_characteristics = gv11b_ops.chip_init_gpu_characteristics; gops->get_litter_value = gv11b_ops.get_litter_value; - val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); - if (val) { - priv_security = true; - pr_err("priv security is enabled\n"); - } else { - priv_security = false; - pr_err("priv security is disabled\n"); - } __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false); - __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, priv_security); - __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, priv_security); + + /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ + if (gops->fuse.check_priv_security(g)) + return -EINVAL; /* Do not boot gpu */ /* priv security dependent ops */ if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { -- cgit v1.2.2