From 8fdf40a849f19dc2f00aacce976ed2e22dbb08f4 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Tue, 13 Sep 2016 13:08:01 -0700 Subject: gpu: gv11b: create modified runlist Create gv11b runlist for channel and tsg in the new specified way. Also set runlist entry size for gv11b. Bug 1735760 Change-Id: Ifd421cd71180e9d02303f4cfc92a59fd74d6d893 Signed-off-by: seshendra Gadagottu Reviewed-on: http://git-master/r/1220258 GVS: Gerrit_Virtual_Submit Reviewed-by: Aingara Paramakuru Reviewed-by: Seema Khowala Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 63 ++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h | 46 ++++++++++++------------- 2 files changed, 86 insertions(+), 23 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index af5f094d..35b36ec5 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c @@ -21,8 +21,71 @@ #include "hw_pbdma_gv11b.h" #include "fifo_gv11b.h" #include "hw_fifo_gv11b.h" +#include "hw_ram_gv11b.h" +#include "hw_ccsr_gv11b.h" + +static void gv11b_get_tsg_runlist_entry(struct tsg_gk20a *tsg, u32 *runlist) +{ + + u32 runlist_entry_0 = ram_rl_entry_type_tsg_v(); + + if (tsg->timeslice_timeout) + runlist_entry_0 |= + ram_rl_entry_tsg_timeslice_scale_f(tsg->timeslice_scale) | + ram_rl_entry_tsg_timeslice_timeout_f(tsg->timeslice_timeout); + else + runlist_entry_0 |= + ram_rl_entry_tsg_timeslice_scale_f( + ram_rl_entry_tsg_timeslice_scale_3_v()) | + ram_rl_entry_tsg_timeslice_timeout_f( + ram_rl_entry_tsg_timeslice_timeout_128_v()); + + runlist[0] = runlist_entry_0; + runlist[1] = ram_rl_entry_tsg_length_f(tsg->num_active_channels); + runlist[2] = ram_rl_entry_tsg_tsgid_f(tsg->tsgid); + runlist[3] = 0; + + gk20a_dbg_info("gv11b tsg runlist [0] %x [1] %x [2] %x [3] %x\n", + runlist[0], runlist[1], runlist[2], runlist[3]); + +} + +static void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) +{ + struct gk20a *g = c->g; + u32 addr_lo, addr_hi; + u32 runlist_entry; + + /* Time being use 0 pbdma sequencer */ + runlist_entry = ram_rl_entry_type_channel_v() | + ram_rl_entry_chan_runqueue_selector_f(0) | + ram_rl_entry_chan_userd_target_f( + ram_rl_entry_chan_userd_target_sys_mem_ncoh_v()) | + ram_rl_entry_chan_inst_target_f( + ram_rl_entry_chan_userd_target_sys_mem_ncoh_v()); + + addr_lo = u64_lo32(c->userd_iova) >> + ram_rl_entry_chan_userd_ptr_align_shift_v(); + addr_hi = u64_hi32(c->userd_iova); + runlist[0] = runlist_entry | ram_rl_entry_chan_userd_ptr_lo_f(addr_lo); + runlist[1] = ram_rl_entry_chan_userd_ptr_hi_f(addr_hi); + + addr_lo = u64_lo32(gk20a_mm_inst_block_addr(g, &c->inst_block)) >> + ram_rl_entry_chan_inst_ptr_align_shift_v(); + addr_hi = u64_hi32(gk20a_mm_inst_block_addr(g, &c->inst_block)); + + runlist[2] = ram_rl_entry_chan_inst_ptr_lo_f(addr_lo) | + ram_rl_entry_chid_f(c->hw_chid); + runlist[3] = ram_rl_entry_chan_inst_ptr_hi_f(addr_hi); + + gk20a_dbg_info("gv11b channel runlist [0] %x [1] %x [2] %x [3] %x\n", + runlist[0], runlist[1], runlist[2], runlist[3]); +} void gv11b_init_fifo(struct gpu_ops *gops) { gp10b_init_fifo(gops); + gops->fifo.runlist_entry_size = ram_rl_entry_size_v; + gops->fifo.get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry; + gops->fifo.get_ch_runlist_entry = gv11b_get_ch_runlist_entry; } diff --git a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h index c6f51acb..9cd2096a 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h @@ -462,7 +462,7 @@ static inline u32 ram_rl_entry_chan_inst_target_f(u32 v) { return (v & 0x3) << 4; } -static inline u32 ram_rl_entry_chan_inst_target_target_sys_mem_ncoh_v(void) +static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void) { return 0x00000003; } @@ -470,19 +470,19 @@ static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) { return (v & 0x3) << 6; } -static inline u32 ram_rl_entry_chan_userd_target_target_vid_mem_v(void) +static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void) { return 0x00000000; } -static inline u32 ram_rl_entry_chan_userd_target_target_vid_mem_nvlink_coh_v(void) +static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void) { return 0x00000001; } -static inline u32 ram_rl_entry_chan_userd_target_target_sys_mem_coh_v(void) +static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void) { return 0x00000002; } -static inline u32 ram_rl_entry_chan_userd_target_target_sys_mem_ncoh_v(void) +static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void) { return 0x00000003; } @@ -494,18 +494,6 @@ static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v) { return (v & 0xffffffff) << 0; } -static inline u32 ram_rl_entry_chan_userd_ptr_hi_entry_chan_inst_ptr_align_shift_v(void) -{ - return 0x0000000c; -} -static inline u32 ram_rl_entry_chan_userd_ptr_hi_entry_chan_userd_ptr_align_shift_v(void) -{ - return 0x00000008; -} -static inline u32 ram_rl_entry_chan_userd_ptr_hi_entry_chan_userd_align_shift_v(void) -{ - return 0x00000008; -} static inline u32 ram_rl_entry_chid_f(u32 v) { return (v & 0xfff) << 0; @@ -526,7 +514,7 @@ static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v) { return (v & 0xf) << 16; } -static inline u32 ram_rl_entry_tsg_timeslice_scale_entry_tsg_timeslice_scale_3_v(void) +static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void) { return 0x00000003; } @@ -534,11 +522,11 @@ static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v) { return (v & 0xff) << 24; } -static inline u32 ram_rl_entry_tsg_timeslice_timeout_entry_tsg_timeslice_timeout_128_v(void) +static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void) { return 0x00000080; } -static inline u32 ram_rl_entry_tsg_timeslice_timeout_entry_tsg_timeslice_timeout_disable_v(void) +static inline u32 ram_rl_entry_tsg_timeslice_timeout_disable_v(void) { return 0x00000000; } @@ -546,15 +534,15 @@ static inline u32 ram_rl_entry_tsg_length_f(u32 v) { return (v & 0xff) << 0; } -static inline u32 ram_rl_entry_tsg_length_entry_tsg_length_init_v(void) +static inline u32 ram_rl_entry_tsg_length_init_v(void) { return 0x00000000; } -static inline u32 ram_rl_entry_tsg_length_entry_tsg_length_min_v(void) +static inline u32 ram_rl_entry_tsg_length_min_v(void) { return 0x00000001; } -static inline u32 ram_rl_entry_tsg_length_entry_tsg_length_max_v(void) +static inline u32 ram_rl_entry_tsg_length_max_v(void) { return 0x00000080; } @@ -562,4 +550,16 @@ static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v) { return (v & 0xfff) << 0; } +static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void) +{ + return 0x00000008; +} +static inline u32 ram_rl_entry_chan_userd_align_shift_v(void) +{ + return 0x00000008; +} #endif -- cgit v1.2.2