From 85f9729af4a05057b0d9f1e48542f6f9e3acecab Mon Sep 17 00:00:00 2001 From: Vaikundanathan S Date: Mon, 23 Apr 2018 16:52:43 +0530 Subject: gpu: nvgpu: vf inject changes - Added vf change inject support for gv10x - Updated clk_pmu_vf_inject() to fill required data for pascal or volta vf change inject support - Added new ctrl clk interface for gv10x clk domain list - Added pmu interface for gv10x clk domain list & vf change inject request - Modified clk cmd, msg & RPC id's to match with chips_a_23609936 branch Bug 200399373 Change-Id: Ib9dc10073386f63bdfd92110c7ec3e09b1c484ce Signed-off-by: Vaikundanathan S Signed-off-by: Mahantesh Kumbar Reviewed-on: https://git-master.nvidia.com/r/1700746 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/clk/clk.c | 89 ++++++++++++++++------ drivers/gpu/nvgpu/clk/clk.h | 6 ++ drivers/gpu/nvgpu/common/pmu/pmu_fw.c | 4 + drivers/gpu/nvgpu/ctrl/ctrlclk.h | 13 ++++ drivers/gpu/nvgpu/gk20a/gk20a.h | 3 + drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h | 27 +++++-- drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h | 2 +- 7 files changed, 115 insertions(+), 29 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/clk/clk.c b/drivers/gpu/nvgpu/clk/clk.c index a8d99bbb..28f08cb6 100644 --- a/drivers/gpu/nvgpu/clk/clk.c +++ b/drivers/gpu/nvgpu/clk/clk.c @@ -219,31 +219,13 @@ done: return status; } -static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk) +u32 nvgpu_clk_vf_change_inject_data_fill_gp10x(struct gk20a *g, + struct nv_pmu_clk_rpc *rpccall, + struct set_fll_clk *setfllclk) { - struct pmu_cmd cmd; - struct pmu_payload payload; - u32 status; - u32 seqdesc; - struct nv_pmu_clk_rpc rpccall; - struct clkrpc_pmucmdhandler_params handler; struct nv_pmu_clk_vf_change_inject *vfchange; - memset(&payload, 0, sizeof(struct pmu_payload)); - memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc)); - memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params)); - - if ((setfllclk->gpc2clkmhz == 0) || (setfllclk->xbar2clkmhz == 0) || - (setfllclk->sys2clkmhz == 0) || (setfllclk->voltuv == 0)) - return -EINVAL; - - if ((setfllclk->target_regime_id_gpc > CTRL_CLK_FLL_REGIME_ID_FR) || - (setfllclk->target_regime_id_sys > CTRL_CLK_FLL_REGIME_ID_FR) || - (setfllclk->target_regime_id_xbar > CTRL_CLK_FLL_REGIME_ID_FR)) - return -EINVAL; - - rpccall.function = NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT; - vfchange = &rpccall.params.clk_vf_change_inject; + vfchange = &rpccall->params.clk_vf_change_inject; vfchange->flags = 0; vfchange->clk_list.num_domains = 3; vfchange->clk_list.clk_domains[0].clk_domain = CTRL_CLK_DOMAIN_GPC2CLK; @@ -276,6 +258,69 @@ static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk) vfchange->volt_list.rails[0].voltage_min_noise_unaware_uv = setfllclk->voltuv; + return 0; +} + +u32 nvgpu_clk_vf_change_inject_data_fill_gv10x(struct gk20a *g, + struct nv_pmu_clk_rpc *rpccall, + struct set_fll_clk *setfllclk) +{ + struct nv_pmu_clk_vf_change_inject_v1 *vfchange; + + vfchange = &rpccall->params.clk_vf_change_inject_v1; + vfchange->flags = 0; + vfchange->clk_list.num_domains = 4; + vfchange->clk_list.clk_domains[0].clk_domain = CTRL_CLK_DOMAIN_GPCCLK; + vfchange->clk_list.clk_domains[0].clk_freq_khz = + setfllclk->gpc2clkmhz * 1000; + + vfchange->clk_list.clk_domains[1].clk_domain = CTRL_CLK_DOMAIN_XBARCLK; + vfchange->clk_list.clk_domains[1].clk_freq_khz = + setfllclk->xbar2clkmhz * 1000; + + vfchange->clk_list.clk_domains[2].clk_domain = CTRL_CLK_DOMAIN_SYSCLK; + vfchange->clk_list.clk_domains[2].clk_freq_khz = + setfllclk->sys2clkmhz * 1000; + + vfchange->clk_list.clk_domains[3].clk_domain = CTRL_CLK_DOMAIN_NVDCLK; + vfchange->clk_list.clk_domains[3].clk_freq_khz = 855 * 1000; + + vfchange->volt_list.num_rails = 1; + vfchange->volt_list.rails[0].rail_idx = 0; + vfchange->volt_list.rails[0].voltage_uv = setfllclk->voltuv; + vfchange->volt_list.rails[0].voltage_min_noise_unaware_uv = + setfllclk->voltuv; + + return 0; +} + +static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk) +{ + struct pmu_cmd cmd; + struct pmu_payload payload; + u32 status; + u32 seqdesc; + struct nv_pmu_clk_rpc rpccall; + struct clkrpc_pmucmdhandler_params handler; + + memset(&payload, 0, sizeof(struct pmu_payload)); + memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc)); + memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params)); + + if ((setfllclk->gpc2clkmhz == 0) || (setfllclk->xbar2clkmhz == 0) || + (setfllclk->sys2clkmhz == 0) || (setfllclk->voltuv == 0)) + return -EINVAL; + + if ((setfllclk->target_regime_id_gpc > CTRL_CLK_FLL_REGIME_ID_FR) || + (setfllclk->target_regime_id_sys > CTRL_CLK_FLL_REGIME_ID_FR) || + (setfllclk->target_regime_id_xbar > CTRL_CLK_FLL_REGIME_ID_FR)) + return -EINVAL; + + rpccall.function = NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT; + + g->ops.pmu_ver.clk.clk_vf_change_inject_data_fill(g, + &rpccall, setfllclk); + cmd.hdr.unit_id = PMU_UNIT_CLK; cmd.hdr.size = (u32)sizeof(struct nv_pmu_clk_cmd) + (u32)sizeof(struct pmu_hdr); diff --git a/drivers/gpu/nvgpu/clk/clk.h b/drivers/gpu/nvgpu/clk/clk.h index a19e2e77..019a1c11 100644 --- a/drivers/gpu/nvgpu/clk/clk.h +++ b/drivers/gpu/nvgpu/clk/clk.h @@ -127,4 +127,10 @@ u32 clk_domain_get_f_points( int clk_get_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk); int clk_set_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk); int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx); +u32 nvgpu_clk_vf_change_inject_data_fill_gv10x(struct gk20a *g, + struct nv_pmu_clk_rpc *rpccall, + struct set_fll_clk *setfllclk); +u32 nvgpu_clk_vf_change_inject_data_fill_gp10x(struct gk20a *g, + struct nv_pmu_clk_rpc *rpccall, + struct set_fll_clk *setfllclk); #endif diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c index c610c391..2dc2dba1 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c @@ -1309,6 +1309,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu) nvgpu_clk_get_vbios_clk_domain_gv10x; g->ops.pmu_ver.clk.clk_avfs_get_vin_cal_data = clk_avfs_get_vin_cal_fuse_v20; + g->ops.pmu_ver.clk.clk_vf_change_inject_data_fill = + nvgpu_clk_vf_change_inject_data_fill_gv10x; } else { g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params = get_pmu_init_msg_pmu_queue_params_v4; @@ -1478,6 +1480,8 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu) nvgpu_clk_get_vbios_clk_domain_gp10x; g->ops.pmu_ver.clk.clk_avfs_get_vin_cal_data = clk_avfs_get_vin_cal_fuse_v10; + g->ops.pmu_ver.clk.clk_vf_change_inject_data_fill = + nvgpu_clk_vf_change_inject_data_fill_gp10x; break; case APP_VERSION_GM20B: g->ops.pmu_ver.pg_cmd_eng_buf_load_size = diff --git a/drivers/gpu/nvgpu/ctrl/ctrlclk.h b/drivers/gpu/nvgpu/ctrl/ctrlclk.h index 3d50f413..537ae0ef 100644 --- a/drivers/gpu/nvgpu/ctrl/ctrlclk.h +++ b/drivers/gpu/nvgpu/ctrl/ctrlclk.h @@ -176,6 +176,19 @@ struct ctrl_clk_clk_domain_list_item { u8 target_regime_id; }; +struct ctrl_clk_clk_domain_list_item_v1 { + u32 clk_domain; + u32 clk_freq_khz; + u8 regime_id; + u8 source; +}; + +struct ctrl_clk_clk_domain_list { + u8 num_domains; + struct ctrl_clk_clk_domain_list_item_v1 + clk_domains[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS]; +}; + #define CTRL_CLK_VF_PAIR_FREQ_MHZ_GET(pvfpair) \ ((pvfpair)->freq_mhz) diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index c05bc046..23e85ee9 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -804,6 +804,9 @@ struct gpu_ops { u32 (*clk_avfs_get_vin_cal_data)(struct gk20a *g, struct avfsvinobjs *pvinobjs, struct vin_device_v20 *pvindev); + u32 (*clk_vf_change_inject_data_fill)(struct gk20a *g, + struct nv_pmu_clk_rpc *rpccall, + struct set_fll_clk *setfllclk); }clk; } pmu_ver; struct { diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h index e0a3313b..dde85435 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h @@ -336,12 +336,24 @@ struct nv_pmu_clk_clk_domain_list { NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS]; }; +struct nv_pmu_clk_clk_domain_list_v1 { + u8 num_domains; + struct ctrl_clk_clk_domain_list_item_v1 clk_domains[ + NV_PMU_VF_INJECT_MAX_CLOCK_DOMAINS]; +}; + struct nv_pmu_clk_vf_change_inject { u8 flags; struct nv_pmu_clk_clk_domain_list clk_list; struct nv_pmu_volt_volt_rail_list volt_list; }; +struct nv_pmu_clk_vf_change_inject_v1 { + u8 flags; + struct nv_pmu_clk_clk_domain_list_v1 clk_list; + struct nv_pmu_volt_volt_rail_list_v1 volt_list; +}; + #define NV_NV_PMU_CLK_LOAD_FEATURE_VIN (0x00000002) #define NV_NV_PMU_CLK_LOAD_ACTION_MASK_VIN_HW_CAL_PROGRAM_YES (0x00000001) @@ -400,12 +412,14 @@ union nv_pmu_clk_clk_freq_controller_boardobj_set_union { NV_PMU_BOARDOBJ_GRP_SET_MAKE_E32(clk, clk_freq_controller); /* CLK CMD ID definitions. */ -#define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_SET (0x00000000) -#define NV_PMU_CLK_CMD_ID_RPC (0x00000001) +#define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_SET (0x00000001) +#define NV_PMU_CLK_CMD_ID_RPC (0x00000000) #define NV_PMU_CLK_CMD_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) -#define NV_PMU_CLK_RPC_ID_LOAD (0x00000002) -#define NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT (0x00000001) +#define NV_PMU_CLK_RPC_ID_LOAD (0x00000001) +#define NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT (0x00000000) +#define NV_PMU_CLK_RPC_ID_CLK_FREQ_EFF_AVG (0x00000002) + struct nv_pmu_clk_cmd_rpc { u8 cmd_type; @@ -432,13 +446,14 @@ struct nv_pmu_clk_rpc { flcn_status flcn_status; union { struct nv_pmu_clk_vf_change_inject clk_vf_change_inject; + struct nv_pmu_clk_vf_change_inject_v1 clk_vf_change_inject_v1; struct nv_pmu_clk_load clk_load; } params; }; /* CLK MSG ID definitions */ -#define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_SET (0x00000000) -#define NV_PMU_CLK_MSG_ID_RPC (0x00000001) +#define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_SET (0x00000001) +#define NV_PMU_CLK_MSG_ID_RPC (0x00000000) #define NV_PMU_CLK_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000002) struct nv_pmu_clk_msg_rpc { diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h index 313a3b2a..b763c487 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifvolt.h @@ -343,7 +343,7 @@ struct nv_pmu_volt_volt_rail_list { rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS]; }; -struct nv_pmu_volt_volt_rail_list_V1 { +struct nv_pmu_volt_volt_rail_list_v1 { u8 num_rails; struct ctrl_volt_volt_rail_list_item_v1 rails[NV_PMU_VF_INJECT_MAX_VOLT_RAILS]; -- cgit v1.2.2