From 744f7f049867c83ecb2c76681cb80ec789459491 Mon Sep 17 00:00:00 2001
From: Seema Khowala <seemaj@nvidia.com>
Date: Wed, 18 Apr 2018 16:18:59 -0700
Subject: gpu: nvgpu: add gr hal for fecs_ctxsw_mailbox size

fecs_ctxsw_mailbox_size varies per chip. Use hal to
get the size. Also dump fecs_ctxsw_status_1 to help
debug

Bug 2093809

Change-Id: I5a50281e9d78fe0e4a75d03971169e3e9679967a
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1698026
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
---
 drivers/gpu/nvgpu/gk20a/gk20a.h     | 1 +
 drivers/gpu/nvgpu/gk20a/gr_gk20a.c  | 4 +++-
 drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 +
 drivers/gpu/nvgpu/gp106/hal_gp106.c | 2 ++
 drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 ++
 drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 ++
 drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 ++
 7 files changed, 13 insertions(+), 1 deletion(-)

(limited to 'drivers/gpu')

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 65750a15..e48af08c 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -474,6 +474,7 @@ struct gpu_ops {
 					u32 num_fbpas,
 					u32 *priv_addr_table,
 					u32 *priv_addr_table_index);
+		u32 (*fecs_ctxsw_mailbox_size)(void);
 	} gr;
 	struct {
 		void (*init_hw)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 51bb2551..d26d8a93 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -155,8 +155,10 @@ void gk20a_fecs_dump_falcon_stats(struct gk20a *g)
 		gk20a_readl(g, gr_fecs_debug1_r()));
 	nvgpu_err(g, "gr_fecs_debuginfo_r : 0x%x",
 		gk20a_readl(g, gr_fecs_debuginfo_r()));
+	nvgpu_err(g, "gr_fecs_ctxsw_status_1_r : 0x%x",
+		gk20a_readl(g, gr_fecs_ctxsw_status_1_r()));
 
-	for (i = 0; i < gr_fecs_ctxsw_mailbox__size_1_v(); i++)
+	for (i = 0; i < g->ops.gr.fecs_ctxsw_mailbox_size(); i++)
 		nvgpu_err(g, "gr_fecs_ctxsw_mailbox_r(%d) : 0x%x",
 			i, gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(i)));
 
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 9fc3a494..76837ab7 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -324,6 +324,7 @@ static const struct gpu_ops gm20b_ops = {
 		.get_pmm_per_chiplet_offset =
 			gr_gm20b_get_pmm_per_chiplet_offset,
 		.split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,
+		.fecs_ctxsw_mailbox_size = gr_fecs_ctxsw_mailbox__size_1_v,
 	},
 	.fb = {
 		.reset = fb_gk20a_reset,
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index d1b60af5..43b1d2e0 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -97,6 +97,7 @@
 #include <nvgpu/hw/gp106/hw_top_gp106.h>
 #include <nvgpu/hw/gp106/hw_pram_gp106.h>
 #include <nvgpu/hw/gp106/hw_pwr_gp106.h>
+#include <nvgpu/hw/gp106/hw_gr_gp106.h>
 
 
 static int gp106_get_litter_value(struct gk20a *g, int value)
@@ -387,6 +388,7 @@ static const struct gpu_ops gp106_ops = {
 		.get_pmm_per_chiplet_offset =
 			gr_gm20b_get_pmm_per_chiplet_offset,
 		.split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,
+		.fecs_ctxsw_mailbox_size = gr_fecs_ctxsw_mailbox__size_1_v,
 	},
 	.fb = {
 		.reset = gp106_fb_reset,
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index a8ee7412..42350dbc 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -80,6 +80,7 @@
 #include <nvgpu/hw/gp10b/hw_top_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_pram_gp10b.h>
 #include <nvgpu/hw/gp10b/hw_pwr_gp10b.h>
+#include <nvgpu/hw/gp10b/hw_gr_gp10b.h>
 
 int gp10b_get_litter_value(struct gk20a *g, int value)
 {
@@ -355,6 +356,7 @@ static const struct gpu_ops gp10b_ops = {
 		.get_pmm_per_chiplet_offset =
 			gr_gm20b_get_pmm_per_chiplet_offset,
 		.split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,
+		.fecs_ctxsw_mailbox_size = gr_fecs_ctxsw_mailbox__size_1_v,
 	},
 	.fb = {
 		.reset = fb_gk20a_reset,
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index d972d4a5..fbf6e046 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -111,6 +111,7 @@
 #include <nvgpu/hw/gv100/hw_top_gv100.h>
 #include <nvgpu/hw/gv100/hw_pram_gv100.h>
 #include <nvgpu/hw/gv100/hw_pwr_gv100.h>
+#include <nvgpu/hw/gv100/hw_gr_gv100.h>
 
 static int gv100_get_litter_value(struct gk20a *g, int value)
 {
@@ -434,6 +435,7 @@ static const struct gpu_ops gv100_ops = {
 		.get_pmm_per_chiplet_offset =
 			gr_gv11b_get_pmm_per_chiplet_offset,
 		.split_fbpa_broadcast_addr = gr_gv100_split_fbpa_broadcast_addr,
+		.fecs_ctxsw_mailbox_size = gr_fecs_ctxsw_mailbox__size_1_v,
 	},
 	.fb = {
 		.reset = gv100_fb_reset,
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 47f832a6..a2ee3206 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -93,6 +93,7 @@
 #include <nvgpu/hw/gv11b/hw_top_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_pwr_gv11b.h>
 #include <nvgpu/hw/gv11b/hw_fuse_gv11b.h>
+#include <nvgpu/hw/gv11b/hw_gr_gv11b.h>
 
 int gv11b_get_litter_value(struct gk20a *g, int value)
 {
@@ -407,6 +408,7 @@ static const struct gpu_ops gv11b_ops = {
 		.get_pmm_per_chiplet_offset =
 			gr_gv11b_get_pmm_per_chiplet_offset,
 		.split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,
+		.fecs_ctxsw_mailbox_size = gr_fecs_ctxsw_mailbox__size_1_v,
 	},
 	.fb = {
 		.reset = gv11b_fb_reset,
-- 
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