From 719923ad9fa7c6b2ca68a25d1ce4518aab844bc2 Mon Sep 17 00:00:00 2001 From: Konsta Holtta Date: Mon, 29 Sep 2014 13:16:15 +0300 Subject: gpu: nvgpu: rename gpu ioctls and structs to nvgpu To help remove the nvhost dependency from nvgpu, rename ioctl defines and structures used by nvgpu such that nvhost is replaced by nvgpu. Duplicate some structures as needed. Update header guards and such accordingly. Change-Id: Ifc3a867713072bae70256502735583ab38381877 Signed-off-by: Konsta Holtta Reviewed-on: http://git-master/r/542620 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gk20a/as_gk20a.c | 60 ++++----- drivers/gpu/nvgpu/gk20a/as_gk20a.h | 10 +- drivers/gpu/nvgpu/gk20a/cde_gk20a.c | 50 ++++---- drivers/gpu/nvgpu/gk20a/cde_gk20a.h | 8 +- drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 166 ++++++++++++------------- drivers/gpu/nvgpu/gk20a/channel_gk20a.h | 22 ++-- drivers/gpu/nvgpu/gk20a/clk_gk20a.h | 15 +-- drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c | 64 +++++----- drivers/gpu/nvgpu/gk20a/ctrl_gk20a.h | 15 +-- drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c | 90 +++++++------- drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.h | 8 +- drivers/gpu/nvgpu/gk20a/debug_gk20a.c | 5 + drivers/gpu/nvgpu/gk20a/debug_gk20a.h | 2 + drivers/gpu/nvgpu/gk20a/fb_gk20a.h | 6 +- drivers/gpu/nvgpu/gk20a/fence_gk20a.c | 5 +- drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 21 ++-- drivers/gpu/nvgpu/gk20a/gk20a.c | 23 ++-- drivers/gpu/nvgpu/gk20a/gk20a.h | 31 +++-- drivers/gpu/nvgpu/gk20a/gk20a_allocator.h | 8 +- drivers/gpu/nvgpu/gk20a/gk20a_scale.h | 1 - drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 33 ++--- drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 18 +-- drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h | 6 +- drivers/gpu/nvgpu/gk20a/ltc_gk20a.h | 4 +- drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 37 +++--- drivers/gpu/nvgpu/gk20a/mm_gk20a.h | 33 ++--- drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c | 1 + drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 8 +- drivers/gpu/nvgpu/gk20a/regops_gk20a.c | 15 ++- drivers/gpu/nvgpu/gk20a/regops_gk20a.h | 11 +- drivers/gpu/nvgpu/gk20a/semaphore_gk20a.h | 14 ++- drivers/gpu/nvgpu/gk20a/sync_gk20a.c | 2 - drivers/gpu/nvgpu/gk20a/therm_gk20a.h | 17 +-- drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 5 +- drivers/gpu/nvgpu/gm20b/regops_gm20b.c | 1 - 35 files changed, 385 insertions(+), 430 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gk20a/as_gk20a.c b/drivers/gpu/nvgpu/gk20a/as_gk20a.c index a2741fe8..c13d055e 100644 --- a/drivers/gpu/nvgpu/gk20a/as_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/as_gk20a.c @@ -1,6 +1,4 @@ /* - * drivers/video/tegra/host/gk20a/as_gk20a.c - * * GK20A Address Spaces * * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. @@ -22,6 +20,8 @@ #include +#include + #include "gk20a.h" /* dumb allocator... */ @@ -93,7 +93,7 @@ int gk20a_as_release_share(struct gk20a_as_share *as_share) static int gk20a_as_ioctl_bind_channel( struct gk20a_as_share *as_share, - struct nvhost_as_bind_channel_args *args) + struct nvgpu_as_bind_channel_args *args) { int err = 0; struct channel_gk20a *ch; @@ -118,7 +118,7 @@ static int gk20a_as_ioctl_bind_channel( static int gk20a_as_ioctl_alloc_space( struct gk20a_as_share *as_share, - struct nvhost_as_alloc_space_args *args) + struct nvgpu_as_alloc_space_args *args) { gk20a_dbg_fn(""); return gk20a_vm_alloc_space(as_share, args); @@ -126,7 +126,7 @@ static int gk20a_as_ioctl_alloc_space( static int gk20a_as_ioctl_free_space( struct gk20a_as_share *as_share, - struct nvhost_as_free_space_args *args) + struct nvgpu_as_free_space_args *args) { gk20a_dbg_fn(""); return gk20a_vm_free_space(as_share, args); @@ -134,12 +134,12 @@ static int gk20a_as_ioctl_free_space( static int gk20a_as_ioctl_map_buffer_ex( struct gk20a_as_share *as_share, - struct nvhost_as_map_buffer_ex_args *args) + struct nvgpu_as_map_buffer_ex_args *args) { gk20a_dbg_fn(""); return gk20a_vm_map_buffer(as_share, args->dmabuf_fd, - &args->as_offset, args->flags, + &args->offset, args->flags, args->kind, args->buffer_offset, args->mapping_size @@ -148,10 +148,10 @@ static int gk20a_as_ioctl_map_buffer_ex( static int gk20a_as_ioctl_map_buffer( struct gk20a_as_share *as_share, - struct nvhost_as_map_buffer_args *args) + struct nvgpu_as_map_buffer_args *args) { gk20a_dbg_fn(""); - return gk20a_vm_map_buffer(as_share, args->nvmap_handle, + return gk20a_vm_map_buffer(as_share, args->dmabuf_fd, &args->o_a.offset, args->flags, NV_KIND_DEFAULT, 0, 0); @@ -160,7 +160,7 @@ static int gk20a_as_ioctl_map_buffer( static int gk20a_as_ioctl_unmap_buffer( struct gk20a_as_share *as_share, - struct nvhost_as_unmap_buffer_args *args) + struct nvgpu_as_unmap_buffer_args *args) { gk20a_dbg_fn(""); return gk20a_vm_unmap_buffer(as_share, args->offset); @@ -214,14 +214,14 @@ long gk20a_as_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) struct gk20a_as_share *as_share = filp->private_data; struct gk20a *g = gk20a_from_as(as_share->as); - u8 buf[NVHOST_AS_IOCTL_MAX_ARG_SIZE]; + u8 buf[NVGPU_AS_IOCTL_MAX_ARG_SIZE]; - if ((_IOC_TYPE(cmd) != NVHOST_AS_IOCTL_MAGIC) || + if ((_IOC_TYPE(cmd) != NVGPU_AS_IOCTL_MAGIC) || (_IOC_NR(cmd) == 0) || - (_IOC_NR(cmd) > NVHOST_AS_IOCTL_LAST)) + (_IOC_NR(cmd) > NVGPU_AS_IOCTL_LAST)) return -EINVAL; - BUG_ON(_IOC_SIZE(cmd) > NVHOST_AS_IOCTL_MAX_ARG_SIZE); + BUG_ON(_IOC_SIZE(cmd) > NVGPU_AS_IOCTL_MAX_ARG_SIZE); if (_IOC_DIR(cmd) & _IOC_WRITE) { if (copy_from_user(buf, (void __user *)arg, _IOC_SIZE(cmd))) @@ -233,17 +233,17 @@ long gk20a_as_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) return err; switch (cmd) { - case NVHOST_AS_IOCTL_BIND_CHANNEL: + case NVGPU_AS_IOCTL_BIND_CHANNEL: trace_gk20a_as_ioctl_bind_channel(dev_name(dev_from_gk20a(g))); err = gk20a_as_ioctl_bind_channel(as_share, - (struct nvhost_as_bind_channel_args *)buf); + (struct nvgpu_as_bind_channel_args *)buf); break; - case NVHOST32_AS_IOCTL_ALLOC_SPACE: + case NVGPU32_AS_IOCTL_ALLOC_SPACE: { - struct nvhost32_as_alloc_space_args *args32 = - (struct nvhost32_as_alloc_space_args *)buf; - struct nvhost_as_alloc_space_args args; + struct nvgpu32_as_alloc_space_args *args32 = + (struct nvgpu32_as_alloc_space_args *)buf; + struct nvgpu_as_alloc_space_args args; args.pages = args32->pages; args.page_size = args32->page_size; @@ -254,30 +254,30 @@ long gk20a_as_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) args32->o_a.offset = args.o_a.offset; break; } - case NVHOST_AS_IOCTL_ALLOC_SPACE: + case NVGPU_AS_IOCTL_ALLOC_SPACE: trace_gk20a_as_ioctl_alloc_space(dev_name(dev_from_gk20a(g))); err = gk20a_as_ioctl_alloc_space(as_share, - (struct nvhost_as_alloc_space_args *)buf); + (struct nvgpu_as_alloc_space_args *)buf); break; - case NVHOST_AS_IOCTL_FREE_SPACE: + case NVGPU_AS_IOCTL_FREE_SPACE: trace_gk20a_as_ioctl_free_space(dev_name(dev_from_gk20a(g))); err = gk20a_as_ioctl_free_space(as_share, - (struct nvhost_as_free_space_args *)buf); + (struct nvgpu_as_free_space_args *)buf); break; - case NVHOST_AS_IOCTL_MAP_BUFFER: + case NVGPU_AS_IOCTL_MAP_BUFFER: trace_gk20a_as_ioctl_map_buffer(dev_name(dev_from_gk20a(g))); err = gk20a_as_ioctl_map_buffer(as_share, - (struct nvhost_as_map_buffer_args *)buf); + (struct nvgpu_as_map_buffer_args *)buf); break; - case NVHOST_AS_IOCTL_MAP_BUFFER_EX: + case NVGPU_AS_IOCTL_MAP_BUFFER_EX: trace_gk20a_as_ioctl_map_buffer(dev_name(dev_from_gk20a(g))); err = gk20a_as_ioctl_map_buffer_ex(as_share, - (struct nvhost_as_map_buffer_ex_args *)buf); + (struct nvgpu_as_map_buffer_ex_args *)buf); break; - case NVHOST_AS_IOCTL_UNMAP_BUFFER: + case NVGPU_AS_IOCTL_UNMAP_BUFFER: trace_gk20a_as_ioctl_unmap_buffer(dev_name(dev_from_gk20a(g))); err = gk20a_as_ioctl_unmap_buffer(as_share, - (struct nvhost_as_unmap_buffer_args *)buf); + (struct nvgpu_as_unmap_buffer_args *)buf); break; default: dev_dbg(dev_from_gk20a(g), "unrecognized as ioctl: 0x%x", cmd); diff --git a/drivers/gpu/nvgpu/gk20a/as_gk20a.h b/drivers/gpu/nvgpu/gk20a/as_gk20a.h index be0e9707..457678ce 100644 --- a/drivers/gpu/nvgpu/gk20a/as_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/as_gk20a.h @@ -1,7 +1,5 @@ /* - * drivers/video/tegra/host/gk20a/as_gk20a.h - * - * GK20A Address Space + * GK20A Address Spaces * * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. * @@ -14,15 +12,13 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. */ -#ifndef __GK20A_AS_H -#define __GK20A_AS_H +#ifndef AS_GK20A_H +#define AS_GK20A_H #include #include #include -#include - struct gk20a_as; struct gk20a_as_share; struct vm_gk20a; diff --git a/drivers/gpu/nvgpu/gk20a/cde_gk20a.c b/drivers/gpu/nvgpu/gk20a/cde_gk20a.c index c2e2cc98..4c33ea8d 100644 --- a/drivers/gpu/nvgpu/gk20a/cde_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/cde_gk20a.c @@ -16,7 +16,6 @@ * along with this program. If not, see . */ -#include #include #include #include @@ -30,6 +29,7 @@ #include "fence_gk20a.h" #include "gr_gk20a.h" #include "debug_gk20a.h" +#include "semaphore_gk20a.h" #include "hw_ccsr_gk20a.h" #include "hw_pbdma_gk20a.h" @@ -65,7 +65,7 @@ static void gk20a_deinit_cde_img(struct gk20a_cde_ctx *cde_ctx) for (i = 0; i < cde_ctx->num_obj_ids; i++) gk20a_free_obj_ctx(cde_ctx->ch, - &(struct nvhost_free_obj_ctx_args) + &(struct nvgpu_free_obj_ctx_args) { cde_ctx->obj_ids[i] }); kfree(cde_ctx->init_cmd); @@ -400,7 +400,7 @@ static int gk20a_init_cde_required_class(struct gk20a_cde_ctx *cde_ctx, const struct firmware *img, u32 required_class) { - struct nvhost_alloc_obj_ctx_args alloc_obj_ctx; + struct nvgpu_alloc_obj_ctx_args alloc_obj_ctx; int err; if (cde_ctx->num_obj_ids >= MAX_CDE_OBJ_IDS) { @@ -430,7 +430,7 @@ static int gk20a_init_cde_command(struct gk20a_cde_ctx *cde_ctx, struct gk20a_cde_cmd_elem *cmd_elem, u32 num_elems) { - struct nvhost_gpfifo **gpfifo, *gpfifo_elem; + struct nvgpu_gpfifo **gpfifo, *gpfifo_elem; u32 *num_entries; int i; @@ -448,7 +448,7 @@ static int gk20a_init_cde_command(struct gk20a_cde_ctx *cde_ctx, } /* allocate gpfifo entries to be pushed */ - *gpfifo = kzalloc(sizeof(struct nvhost_gpfifo) * num_elems, + *gpfifo = kzalloc(sizeof(struct nvgpu_gpfifo) * num_elems, GFP_KERNEL); if (!*gpfifo) { gk20a_warn(&cde_ctx->pdev->dev, "cde: could not allocate memory for gpfifo entries"); @@ -574,10 +574,10 @@ deinit_image: } static int gk20a_cde_execute_buffer(struct gk20a_cde_ctx *cde_ctx, - u32 op, struct nvhost_fence *fence, + u32 op, struct nvgpu_fence *fence, u32 flags, struct gk20a_fence **fence_out) { - struct nvhost_gpfifo *gpfifo = NULL; + struct nvgpu_gpfifo *gpfifo = NULL; int num_entries = 0; /* check command type */ @@ -604,7 +604,7 @@ static int gk20a_cde_execute_buffer(struct gk20a_cde_ctx *cde_ctx, int gk20a_cde_convert(struct gk20a *g, struct dma_buf *src, struct dma_buf *dst, s32 dst_kind, u64 dst_byte_offset, - u32 dst_size, struct nvhost_fence *fence, + u32 dst_size, struct nvgpu_fence *fence, u32 __flags, struct gk20a_cde_param *params, int num_params, struct gk20a_fence **fence_out) { @@ -637,7 +637,7 @@ int gk20a_cde_convert(struct gk20a *g, struct dma_buf *src, /* map the destination buffer */ get_dma_buf(dst); /* a ref for gk20a_vm_map */ dst_vaddr = gk20a_vm_map(g->cde_app.vm, dst, 0, - NVHOST_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, + NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, dst_kind, NULL, true, gk20a_mem_flag_none, 0, 0); @@ -655,7 +655,7 @@ int gk20a_cde_convert(struct gk20a *g, struct dma_buf *src, /* map the source buffer to prevent premature release */ get_dma_buf(src); /* a ref for gk20a_vm_map */ src_vaddr = gk20a_vm_map(g->cde_app.vm, src, 0, - NVHOST_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, + NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, dst_kind, NULL, true, gk20a_mem_flag_none, 0, 0); @@ -736,7 +736,7 @@ int gk20a_cde_convert(struct gk20a *g, struct dma_buf *src, /* take always the postfence as it is needed for protecting the * cde context */ - flags = __flags | NVHOST_SUBMIT_GPFIFO_FLAGS_FENCE_GET; + flags = __flags | NVGPU_SUBMIT_GPFIFO_FLAGS_FENCE_GET; /* execute the conversion buffer */ err = gk20a_cde_execute_buffer(cde_ctx, TYPE_BUF_COMMAND_CONVERT, @@ -788,7 +788,7 @@ int gk20a_cde_load(struct gk20a_cde_ctx *cde_ctx) /* allocate gpfifo (1024 should be more than enough) */ err = gk20a_alloc_channel_gpfifo(ch, - &(struct nvhost_alloc_gpfifo_args){1024, 0}); + &(struct nvgpu_alloc_gpfifo_args){1024, 0}); if (err) { gk20a_warn(&cde_ctx->pdev->dev, "cde: unable to allocate gpfifo"); goto err_alloc_gpfifo; @@ -797,7 +797,7 @@ int gk20a_cde_load(struct gk20a_cde_ctx *cde_ctx) /* map backing store to gpu virtual space */ vaddr = gk20a_gmmu_map(ch->vm, &gr->compbit_store.sgt, g->gr.compbit_store.size, - NVHOST_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, + NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, gk20a_mem_flag_read_only); if (!vaddr) { @@ -986,7 +986,7 @@ static int gk20a_buffer_convert_gpu_to_cde( struct gk20a *g, struct dma_buf *dmabuf, u32 consumer, u64 offset, u64 compbits_offset, u32 width, u32 height, u32 block_height_log2, - u32 submit_flags, struct nvhost_fence *fence_in, + u32 submit_flags, struct nvgpu_fence *fence_in, struct gk20a_fence **fence_out) { struct gk20a_cde_param params[NUM_CDE_LAUNCH_PATCHES]; @@ -994,7 +994,7 @@ static int gk20a_buffer_convert_gpu_to_cde( int err = 0; /* Compute per launch parameters */ - const bool transpose = (consumer == NVHOST_GPU_COMPBITS_CDEV); + const bool transpose = (consumer == NVGPU_GPU_COMPBITS_CDEV); const int transposed_width = transpose ? height : width; const int transposed_height = transpose ? width : height; const int xtiles = (transposed_width + 7) >> 3; @@ -1069,7 +1069,7 @@ int gk20a_prepare_compressible_read( struct gk20a *g, u32 buffer_fd, u32 request, u64 offset, u64 compbits_hoffset, u64 compbits_voffset, u32 width, u32 height, u32 block_height_log2, - u32 submit_flags, struct nvhost_fence *fence, + u32 submit_flags, struct nvgpu_fence *fence, u32 *valid_compbits, u32 *zbc_color, struct gk20a_fence **fence_out) { @@ -1092,7 +1092,7 @@ int gk20a_prepare_compressible_read( mutex_lock(&state->lock); - if (state->valid_compbits && request == NVHOST_GPU_COMPBITS_NONE) { + if (state->valid_compbits && request == NVGPU_GPU_COMPBITS_NONE) { gk20a_fence_put(state->fence); state->fence = NULL; @@ -1102,11 +1102,11 @@ int gk20a_prepare_compressible_read( goto out; } else if (missing_bits) { struct gk20a_fence *new_fence = NULL; - if ((state->valid_compbits & NVHOST_GPU_COMPBITS_GPU) && - (missing_bits & NVHOST_GPU_COMPBITS_CDEH)) { + if ((state->valid_compbits & NVGPU_GPU_COMPBITS_GPU) && + (missing_bits & NVGPU_GPU_COMPBITS_CDEH)) { err = gk20a_buffer_convert_gpu_to_cde( g, dmabuf, - NVHOST_GPU_COMPBITS_CDEH, + NVGPU_GPU_COMPBITS_CDEH, offset, compbits_hoffset, width, height, block_height_log2, submit_flags, fence, @@ -1117,13 +1117,13 @@ int gk20a_prepare_compressible_read( /* CDEH bits generated, update state & fence */ gk20a_fence_put(state->fence); state->fence = new_fence; - state->valid_compbits |= NVHOST_GPU_COMPBITS_CDEH; + state->valid_compbits |= NVGPU_GPU_COMPBITS_CDEH; } - if ((state->valid_compbits & NVHOST_GPU_COMPBITS_GPU) && - (missing_bits & NVHOST_GPU_COMPBITS_CDEV)) { + if ((state->valid_compbits & NVGPU_GPU_COMPBITS_GPU) && + (missing_bits & NVGPU_GPU_COMPBITS_CDEV)) { err = gk20a_buffer_convert_gpu_to_cde( g, dmabuf, - NVHOST_GPU_COMPBITS_CDEV, + NVGPU_GPU_COMPBITS_CDEV, offset, compbits_voffset, width, height, block_height_log2, submit_flags, fence, @@ -1134,7 +1134,7 @@ int gk20a_prepare_compressible_read( /* CDEH bits generated, update state & fence */ gk20a_fence_put(state->fence); state->fence = new_fence; - state->valid_compbits |= NVHOST_GPU_COMPBITS_CDEV; + state->valid_compbits |= NVGPU_GPU_COMPBITS_CDEV; } } diff --git a/drivers/gpu/nvgpu/gk20a/cde_gk20a.h b/drivers/gpu/nvgpu/gk20a/cde_gk20a.h index 92757271..c427d4db 100644 --- a/drivers/gpu/nvgpu/gk20a/cde_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/cde_gk20a.h @@ -233,10 +233,10 @@ struct gk20a_cde_ctx { u64 backing_store_vaddr; - struct nvhost_gpfifo *init_cmd; + struct nvgpu_gpfifo *init_cmd; int init_cmd_num_entries; - struct nvhost_gpfifo *convert_cmd; + struct nvgpu_gpfifo *convert_cmd; int convert_cmd_num_entries; struct kobj_attribute attr; @@ -260,7 +260,7 @@ int gk20a_init_cde_support(struct gk20a *g); int gk20a_cde_reload(struct gk20a *g); int gk20a_cde_convert(struct gk20a *g, struct dma_buf *src, struct dma_buf *dst, s32 dst_kind, u64 dst_word_offset, - u32 dst_size, struct nvhost_fence *fence, + u32 dst_size, struct nvgpu_fence *fence, u32 __flags, struct gk20a_cde_param *params, int num_params, struct gk20a_fence **fence_out); void gk20a_cde_debugfs_init(struct platform_device *dev); @@ -269,7 +269,7 @@ int gk20a_prepare_compressible_read( struct gk20a *g, u32 buffer_fd, u32 request, u64 offset, u64 compbits_hoffset, u64 compbits_voffset, u32 width, u32 height, u32 block_height_log2, - u32 submit_flags, struct nvhost_fence *fence, + u32 submit_flags, struct nvgpu_fence *fence, u32 *valid_compbits, u32 *zbc_color, struct gk20a_fence **fence_out); int gk20a_mark_compressible_write( diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index 34c95483..0e8eb497 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c @@ -1,6 +1,4 @@ /* - * drivers/video/tegra/host/gk20a/channel_gk20a.c - * * GK20A Graphics channel * * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. @@ -14,9 +12,8 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . */ #include @@ -497,15 +494,15 @@ static void gk20a_free_cycle_stats_buffer(struct channel_gk20a *ch) } static int gk20a_channel_cycle_stats(struct channel_gk20a *ch, - struct nvhost_cycle_stats_args *args) + struct nvgpu_cycle_stats_args *args) { struct dma_buf *dmabuf; void *virtual_address; - if (args->nvmap_handle && !ch->cyclestate.cyclestate_buffer_handler) { + if (args->dmabuf_fd && !ch->cyclestate.cyclestate_buffer_handler) { /* set up new cyclestats buffer */ - dmabuf = dma_buf_get(args->nvmap_handle); + dmabuf = dma_buf_get(args->dmabuf_fd); if (IS_ERR(dmabuf)) return PTR_ERR(dmabuf); virtual_address = dma_buf_vmap(dmabuf); @@ -517,12 +514,12 @@ static int gk20a_channel_cycle_stats(struct channel_gk20a *ch, ch->cyclestate.cyclestate_buffer_size = dmabuf->size; return 0; - } else if (!args->nvmap_handle && + } else if (!args->dmabuf_fd && ch->cyclestate.cyclestate_buffer_handler) { gk20a_free_cycle_stats_buffer(ch); return 0; - } else if (!args->nvmap_handle && + } else if (!args->dmabuf_fd && !ch->cyclestate.cyclestate_buffer_handler) { /* no requst from GL */ return 0; @@ -535,7 +532,7 @@ static int gk20a_channel_cycle_stats(struct channel_gk20a *ch, #endif static int gk20a_init_error_notifier(struct channel_gk20a *ch, - struct nvhost_set_error_notifier *args) { + struct nvgpu_set_error_notifier *args) { void *va; struct dma_buf *dmabuf; @@ -566,7 +563,7 @@ static int gk20a_init_error_notifier(struct channel_gk20a *ch, ch->error_notifier_ref = dmabuf; ch->error_notifier = va + args->offset; ch->error_notifier_va = va; - memset(ch->error_notifier, 0, sizeof(struct nvhost_notification)); + memset(ch->error_notifier, 0, sizeof(struct nvgpu_notification)); return 0; } @@ -1104,8 +1101,9 @@ static void recycle_priv_cmdbuf(struct channel_gk20a *c) gk20a_dbg_fn("done"); } + int gk20a_alloc_channel_gpfifo(struct channel_gk20a *c, - struct nvhost_alloc_gpfifo_args *args) + struct nvgpu_alloc_gpfifo_args *args) { struct gk20a *g = c->g; struct device *d = dev_from_gk20a(g); @@ -1119,7 +1117,7 @@ int gk20a_alloc_channel_gpfifo(struct channel_gk20a *c, and another one after, for internal usage. Triple the requested size. */ gpfifo_size = roundup_pow_of_two(args->num_entries * 3); - if (args->flags & NVHOST_ALLOC_GPFIFO_FLAGS_VPR_ENABLED) + if (args->flags & NVGPU_ALLOC_GPFIFO_FLAGS_VPR_ENABLED) c->vpr = true; /* an address space needs to have been bound at this point. */ @@ -1496,10 +1494,10 @@ void add_wait_cmd(u32 *ptr, u32 id, u32 thresh) } int gk20a_submit_channel_gpfifo(struct channel_gk20a *c, - struct nvhost_gpfifo *gpfifo, + struct nvgpu_gpfifo *gpfifo, u32 num_entries, u32 flags, - struct nvhost_fence *fence, + struct nvgpu_fence *fence, struct gk20a_fence **fence_out) { struct gk20a *g = c->g; @@ -1514,13 +1512,13 @@ int gk20a_submit_channel_gpfifo(struct channel_gk20a *c, /* we might need two extra gpfifo entries - one for pre fence * and one for post fence. */ const int extra_entries = 2; - bool need_wfi = !(flags & NVHOST_SUBMIT_GPFIFO_FLAGS_SUPPRESS_WFI); + bool need_wfi = !(flags & NVGPU_SUBMIT_GPFIFO_FLAGS_SUPPRESS_WFI); if (c->has_timedout) return -ETIMEDOUT; - if ((flags & (NVHOST_SUBMIT_GPFIFO_FLAGS_FENCE_WAIT | - NVHOST_SUBMIT_GPFIFO_FLAGS_FENCE_GET)) && + if ((flags & (NVGPU_SUBMIT_GPFIFO_FLAGS_FENCE_WAIT | + NVGPU_SUBMIT_GPFIFO_FLAGS_FENCE_GET)) && !fence) return -EINVAL; @@ -1551,7 +1549,7 @@ int gk20a_submit_channel_gpfifo(struct channel_gk20a *c, c->hw_chid, num_entries, flags, - fence ? fence->syncpt_id : 0, + fence ? fence->id : 0, fence ? fence->value : 0); check_gp_put(g, c); update_gp_get(g, c); @@ -1603,13 +1601,13 @@ int gk20a_submit_channel_gpfifo(struct channel_gk20a *c, * the only reason this isn't being unceremoniously killed is to * keep running some tests which trigger this condition */ - if (flags & NVHOST_SUBMIT_GPFIFO_FLAGS_FENCE_WAIT) { - if (flags & NVHOST_SUBMIT_GPFIFO_FLAGS_SYNC_FENCE) { - wait_fence_fd = fence->syncpt_id; + if (flags & NVGPU_SUBMIT_GPFIFO_FLAGS_FENCE_WAIT) { + if (flags & NVGPU_SUBMIT_GPFIFO_FLAGS_SYNC_FENCE) { + wait_fence_fd = fence->id; err = c->sync->wait_fd(c->sync, wait_fence_fd, &wait_cmd, &pre_fence); } else { - err = c->sync->wait_syncpt(c->sync, fence->syncpt_id, + err = c->sync->wait_syncpt(c->sync, fence->id, fence->value, &wait_cmd, &pre_fence); } } @@ -1621,7 +1619,7 @@ int gk20a_submit_channel_gpfifo(struct channel_gk20a *c, /* always insert syncpt increment at end of gpfifo submission to keep track of method completion for idle railgating */ - if (flags & NVHOST_SUBMIT_GPFIFO_FLAGS_FENCE_GET) + if (flags & NVGPU_SUBMIT_GPFIFO_FLAGS_FENCE_GET) err = c->sync->incr_user(c->sync, wait_fence_fd, &incr_cmd, &post_fence, need_wfi); else @@ -1822,7 +1820,7 @@ cleanup_put: } static int gk20a_channel_wait(struct channel_gk20a *ch, - struct nvhost_wait_args *args) + struct nvgpu_wait_args *args) { struct device *d = dev_from_gk20a(ch->g); struct dma_buf *dmabuf; @@ -1839,14 +1837,14 @@ static int gk20a_channel_wait(struct channel_gk20a *ch, if (ch->has_timedout) return -ETIMEDOUT; - if (args->timeout == NVHOST_NO_TIMEOUT) + if (args->timeout == NVGPU_NO_TIMEOUT) timeout = MAX_SCHEDULE_TIMEOUT; else timeout = (u32)msecs_to_jiffies(args->timeout); switch (args->type) { - case NVHOST_WAIT_TYPE_NOTIFIER: - id = args->condition.notifier.nvmap_handle; + case NVGPU_WAIT_TYPE_NOTIFIER: + id = args->condition.notifier.dmabuf_fd; offset = args->condition.notifier.offset; dmabuf = dma_buf_get(id); @@ -1891,9 +1889,9 @@ notif_clean_up: dma_buf_vunmap(dmabuf, notif); return ret; - case NVHOST_WAIT_TYPE_SEMAPHORE: + case NVGPU_WAIT_TYPE_SEMAPHORE: ret = gk20a_channel_wait_semaphore(ch, - args->condition.semaphore.nvmap_handle, + args->condition.semaphore.dmabuf_fd, args->condition.semaphore.offset, args->condition.semaphore.payload, timeout); @@ -1948,7 +1946,7 @@ static void gk20a_channel_events_clear(struct channel_gk20a_poll_events *ev) } static int gk20a_channel_events_ctrl(struct channel_gk20a *ch, - struct nvhost_channel_events_ctrl_args *args) + struct nvgpu_channel_events_ctrl_args *args) { int ret = 0; @@ -1956,15 +1954,15 @@ static int gk20a_channel_events_ctrl(struct channel_gk20a *ch, "channel events ctrl cmd %d", args->cmd); switch (args->cmd) { - case NVHOST_IOCTL_CHANNEL_EVENTS_CTRL_CMD_ENABLE: + case NVGPU_IOCTL_CHANNEL_EVENTS_CTRL_CMD_ENABLE: gk20a_channel_events_enable(&ch->poll_events); break; - case NVHOST_IOCTL_CHANNEL_EVENTS_CTRL_CMD_DISABLE: + case NVGPU_IOCTL_CHANNEL_EVENTS_CTRL_CMD_DISABLE: gk20a_channel_events_disable(&ch->poll_events); break; - case NVHOST_IOCTL_CHANNEL_EVENTS_CTRL_CMD_CLEAR: + case NVGPU_IOCTL_CHANNEL_EVENTS_CTRL_CMD_CLEAR: gk20a_channel_events_clear(&ch->poll_events); break; @@ -2027,15 +2025,15 @@ static int gk20a_channel_set_priority(struct channel_gk20a *ch, u32 timeslice_timeout; /* set priority of graphics channel */ switch (priority) { - case NVHOST_PRIORITY_LOW: + case NVGPU_PRIORITY_LOW: /* 64 << 3 = 512us */ timeslice_timeout = 64; break; - case NVHOST_PRIORITY_MEDIUM: + case NVGPU_PRIORITY_MEDIUM: /* 128 << 3 = 1024us */ timeslice_timeout = 128; break; - case NVHOST_PRIORITY_HIGH: + case NVGPU_PRIORITY_HIGH: /* 255 << 3 = 2048us */ timeslice_timeout = 255; break; @@ -2049,7 +2047,7 @@ static int gk20a_channel_set_priority(struct channel_gk20a *ch, } static int gk20a_channel_zcull_bind(struct channel_gk20a *ch, - struct nvhost_zcull_bind_args *args) + struct nvgpu_zcull_bind_args *args) { struct gk20a *g = ch->g; struct gr_gk20a *gr = &g->gr; @@ -2145,7 +2143,7 @@ void gk20a_channel_semaphore_wakeup(struct gk20a *g) static int gk20a_ioctl_channel_submit_gpfifo( struct channel_gk20a *ch, - struct nvhost_submit_gpfifo_args *args) + struct nvgpu_submit_gpfifo_args *args) { struct gk20a_fence *fence_out; void *gpfifo; @@ -2157,7 +2155,7 @@ static int gk20a_ioctl_channel_submit_gpfifo( if (ch->has_timedout) return -ETIMEDOUT; - size = args->num_entries * sizeof(struct nvhost_gpfifo); + size = args->num_entries * sizeof(struct nvgpu_gpfifo); gpfifo = kzalloc(size, GFP_KERNEL); if (!gpfifo) @@ -2177,15 +2175,15 @@ static int gk20a_ioctl_channel_submit_gpfifo( goto clean_up; /* Convert fence_out to something we can pass back to user space. */ - if (args->flags & NVHOST_SUBMIT_GPFIFO_FLAGS_FENCE_GET) { - if (args->flags & NVHOST_SUBMIT_GPFIFO_FLAGS_SYNC_FENCE) { + if (args->flags & NVGPU_SUBMIT_GPFIFO_FLAGS_FENCE_GET) { + if (args->flags & NVGPU_SUBMIT_GPFIFO_FLAGS_SYNC_FENCE) { int fd = gk20a_fence_install_fd(fence_out); if (fd < 0) ret = fd; else - args->fence.syncpt_id = fd; + args->fence.id = fd; } else { - args->fence.syncpt_id = fence_out->syncpt_id; + args->fence.id = fence_out->syncpt_id; args->fence.value = fence_out->syncpt_value; } } @@ -2211,15 +2209,15 @@ long gk20a_channel_ioctl(struct file *filp, { struct channel_gk20a *ch = filp->private_data; struct platform_device *dev = ch->g->dev; - u8 buf[NVHOST_IOCTL_CHANNEL_MAX_ARG_SIZE]; + u8 buf[NVGPU_IOCTL_CHANNEL_MAX_ARG_SIZE]; int err = 0; gk20a_dbg_fn("start %d", _IOC_NR(cmd)); - if ((_IOC_TYPE(cmd) != NVHOST_IOCTL_MAGIC) || + if ((_IOC_TYPE(cmd) != NVGPU_IOCTL_MAGIC) || (_IOC_NR(cmd) == 0) || - (_IOC_NR(cmd) > NVHOST_IOCTL_CHANNEL_LAST) || - (_IOC_SIZE(cmd) > NVHOST_IOCTL_CHANNEL_MAX_ARG_SIZE)) + (_IOC_NR(cmd) > NVGPU_IOCTL_CHANNEL_LAST) || + (_IOC_SIZE(cmd) > NVGPU_IOCTL_CHANNEL_MAX_ARG_SIZE)) return -EINVAL; if (_IOC_DIR(cmd) & _IOC_WRITE) { @@ -2228,7 +2226,7 @@ long gk20a_channel_ioctl(struct file *filp, } switch (cmd) { - case NVHOST_IOCTL_CHANNEL_OPEN: + case NVGPU_IOCTL_CHANNEL_OPEN: { int fd; struct file *file; @@ -2263,12 +2261,12 @@ long gk20a_channel_ioctl(struct file *filp, break; } - ((struct nvhost_channel_open_args *)buf)->channel_fd = fd; + ((struct nvgpu_channel_open_args *)buf)->channel_fd = fd; break; } - case NVHOST_IOCTL_CHANNEL_SET_NVMAP_FD: + case NVGPU_IOCTL_CHANNEL_SET_NVMAP_FD: break; - case NVHOST_IOCTL_CHANNEL_ALLOC_OBJ_CTX: + case NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX: err = gk20a_busy(dev); if (err) { dev_err(&dev->dev, @@ -2277,10 +2275,10 @@ long gk20a_channel_ioctl(struct file *filp, return err; } err = ch->g->ops.gr.alloc_obj_ctx(ch, - (struct nvhost_alloc_obj_ctx_args *)buf); + (struct nvgpu_alloc_obj_ctx_args *)buf); gk20a_idle(dev); break; - case NVHOST_IOCTL_CHANNEL_FREE_OBJ_CTX: + case NVGPU_IOCTL_CHANNEL_FREE_OBJ_CTX: err = gk20a_busy(dev); if (err) { dev_err(&dev->dev, @@ -2289,10 +2287,10 @@ long gk20a_channel_ioctl(struct file *filp, return err; } err = ch->g->ops.gr.free_obj_ctx(ch, - (struct nvhost_free_obj_ctx_args *)buf); + (struct nvgpu_free_obj_ctx_args *)buf); gk20a_idle(dev); break; - case NVHOST_IOCTL_CHANNEL_ALLOC_GPFIFO: + case NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO: err = gk20a_busy(dev); if (err) { dev_err(&dev->dev, @@ -2301,14 +2299,14 @@ long gk20a_channel_ioctl(struct file *filp, return err; } err = gk20a_alloc_channel_gpfifo(ch, - (struct nvhost_alloc_gpfifo_args *)buf); + (struct nvgpu_alloc_gpfifo_args *)buf); gk20a_idle(dev); break; - case NVHOST_IOCTL_CHANNEL_SUBMIT_GPFIFO: + case NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO: err = gk20a_ioctl_channel_submit_gpfifo(ch, - (struct nvhost_submit_gpfifo_args *)buf); + (struct nvgpu_submit_gpfifo_args *)buf); break; - case NVHOST_IOCTL_CHANNEL_WAIT: + case NVGPU_IOCTL_CHANNEL_WAIT: err = gk20a_busy(dev); if (err) { dev_err(&dev->dev, @@ -2317,10 +2315,10 @@ long gk20a_channel_ioctl(struct file *filp, return err; } err = gk20a_channel_wait(ch, - (struct nvhost_wait_args *)buf); + (struct nvgpu_wait_args *)buf); gk20a_idle(dev); break; - case NVHOST_IOCTL_CHANNEL_ZCULL_BIND: + case NVGPU_IOCTL_CHANNEL_ZCULL_BIND: err = gk20a_busy(dev); if (err) { dev_err(&dev->dev, @@ -2329,10 +2327,10 @@ long gk20a_channel_ioctl(struct file *filp, return err; } err = gk20a_channel_zcull_bind(ch, - (struct nvhost_zcull_bind_args *)buf); + (struct nvgpu_zcull_bind_args *)buf); gk20a_idle(dev); break; - case NVHOST_IOCTL_CHANNEL_SET_ERROR_NOTIFIER: + case NVGPU_IOCTL_CHANNEL_SET_ERROR_NOTIFIER: err = gk20a_busy(dev); if (err) { dev_err(&dev->dev, @@ -2341,11 +2339,11 @@ long gk20a_channel_ioctl(struct file *filp, return err; } err = gk20a_init_error_notifier(ch, - (struct nvhost_set_error_notifier *)buf); + (struct nvgpu_set_error_notifier *)buf); gk20a_idle(dev); break; #ifdef CONFIG_GK20A_CYCLE_STATS - case NVHOST_IOCTL_CHANNEL_CYCLE_STATS: + case NVGPU_IOCTL_CHANNEL_CYCLE_STATS: err = gk20a_busy(dev); if (err) { dev_err(&dev->dev, @@ -2354,37 +2352,37 @@ long gk20a_channel_ioctl(struct file *filp, return err; } err = gk20a_channel_cycle_stats(ch, - (struct nvhost_cycle_stats_args *)buf); + (struct nvgpu_cycle_stats_args *)buf); gk20a_idle(dev); break; #endif - case NVHOST_IOCTL_CHANNEL_SET_TIMEOUT: + case NVGPU_IOCTL_CHANNEL_SET_TIMEOUT: { u32 timeout = - (u32)((struct nvhost_set_timeout_args *)buf)->timeout; + (u32)((struct nvgpu_set_timeout_args *)buf)->timeout; gk20a_dbg(gpu_dbg_gpu_dbg, "setting timeout (%d ms) for chid %d", timeout, ch->hw_chid); ch->timeout_ms_max = timeout; break; } - case NVHOST_IOCTL_CHANNEL_SET_TIMEOUT_EX: + case NVGPU_IOCTL_CHANNEL_SET_TIMEOUT_EX: { u32 timeout = - (u32)((struct nvhost_set_timeout_args *)buf)->timeout; + (u32)((struct nvgpu_set_timeout_args *)buf)->timeout; bool timeout_debug_dump = !((u32) - ((struct nvhost_set_timeout_ex_args *)buf)->flags & - (1 << NVHOST_TIMEOUT_FLAG_DISABLE_DUMP)); + ((struct nvgpu_set_timeout_ex_args *)buf)->flags & + (1 << NVGPU_TIMEOUT_FLAG_DISABLE_DUMP)); gk20a_dbg(gpu_dbg_gpu_dbg, "setting timeout (%d ms) for chid %d", timeout, ch->hw_chid); ch->timeout_ms_max = timeout; ch->timeout_debug_dump = timeout_debug_dump; break; } - case NVHOST_IOCTL_CHANNEL_GET_TIMEDOUT: - ((struct nvhost_get_param_args *)buf)->value = + case NVGPU_IOCTL_CHANNEL_GET_TIMEDOUT: + ((struct nvgpu_get_param_args *)buf)->value = ch->has_timedout; break; - case NVHOST_IOCTL_CHANNEL_SET_PRIORITY: + case NVGPU_IOCTL_CHANNEL_SET_PRIORITY: err = gk20a_busy(dev); if (err) { dev_err(&dev->dev, @@ -2393,10 +2391,10 @@ long gk20a_channel_ioctl(struct file *filp, return err; } gk20a_channel_set_priority(ch, - ((struct nvhost_set_priority_args *)buf)->priority); + ((struct nvgpu_set_priority_args *)buf)->priority); gk20a_idle(dev); break; - case NVHOST_IOCTL_CHANNEL_ENABLE: + case NVGPU_IOCTL_CHANNEL_ENABLE: err = gk20a_busy(dev); if (err) { dev_err(&dev->dev, @@ -2410,7 +2408,7 @@ long gk20a_channel_ioctl(struct file *filp, ccsr_channel_enable_set_true_f()); gk20a_idle(dev); break; - case NVHOST_IOCTL_CHANNEL_DISABLE: + case NVGPU_IOCTL_CHANNEL_DISABLE: err = gk20a_busy(dev); if (err) { dev_err(&dev->dev, @@ -2424,7 +2422,7 @@ long gk20a_channel_ioctl(struct file *filp, ccsr_channel_enable_clr_true_f()); gk20a_idle(dev); break; - case NVHOST_IOCTL_CHANNEL_PREEMPT: + case NVGPU_IOCTL_CHANNEL_PREEMPT: err = gk20a_busy(dev); if (err) { dev_err(&dev->dev, @@ -2435,7 +2433,7 @@ long gk20a_channel_ioctl(struct file *filp, err = gk20a_fifo_preempt(ch->g, ch); gk20a_idle(dev); break; - case NVHOST_IOCTL_CHANNEL_FORCE_RESET: + case NVGPU_IOCTL_CHANNEL_FORCE_RESET: err = gk20a_busy(dev); if (err) { dev_err(&dev->dev, @@ -2446,9 +2444,9 @@ long gk20a_channel_ioctl(struct file *filp, err = gk20a_fifo_force_reset_ch(ch, true); gk20a_idle(dev); break; - case NVHOST_IOCTL_CHANNEL_EVENTS_CTRL: + case NVGPU_IOCTL_CHANNEL_EVENTS_CTRL: err = gk20a_channel_events_ctrl(ch, - (struct nvhost_channel_events_ctrl_args *)buf); + (struct nvgpu_channel_events_ctrl_args *)buf); break; default: dev_dbg(&dev->dev, "unrecognized ioctl cmd: 0x%x", cmd); diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h index bb9f314c..ff056140 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h @@ -1,6 +1,4 @@ /* - * drivers/video/tegra/host/gk20a/channel_gk20a.h - * * GK20A graphics channel * * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. @@ -14,12 +12,11 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . */ -#ifndef __CHANNEL_GK20A_H__ -#define __CHANNEL_GK20A_H__ +#ifndef CHANNEL_GK20A_H +#define CHANNEL_GK20A_H #include #include @@ -37,6 +34,7 @@ struct gk20a_fence; #include "mm_gk20a.h" #include "gr_gk20a.h" +#include "fence_gk20a.h" struct gpfifo { u32 entry0; @@ -148,7 +146,7 @@ struct channel_gk20a { bool timeout_debug_dump; struct dma_buf *error_notifier_ref; - struct nvhost_notification *error_notifier; + struct nvgpu_notification *error_notifier; void *error_notifier_va; struct gk20a_channel_sync *sync; @@ -201,14 +199,14 @@ struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g); void channel_gk20a_unbind(struct channel_gk20a *ch_gk20a); int gk20a_submit_channel_gpfifo(struct channel_gk20a *c, - struct nvhost_gpfifo *gpfifo, + struct nvgpu_gpfifo *gpfifo, u32 num_entries, u32 flags, - struct nvhost_fence *fence, + struct nvgpu_fence *fence, struct gk20a_fence **fence_out); int gk20a_alloc_channel_gpfifo(struct channel_gk20a *c, - struct nvhost_alloc_gpfifo_args *args); + struct nvgpu_alloc_gpfifo_args *args); void channel_gk20a_unbind(struct channel_gk20a *ch_gk20a); void channel_gk20a_disable(struct channel_gk20a *ch); @@ -217,4 +215,4 @@ void channel_gk20a_free_inst(struct gk20a *g, struct channel_gk20a *ch); int channel_gk20a_setup_ramfc(struct channel_gk20a *c, u64 gpfifo_base, u32 gpfifo_entries); -#endif /*__CHANNEL_GK20A_H__*/ +#endif /* CHANNEL_GK20A_H */ diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h index ed54ba7a..255c1a7c 100644 --- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h @@ -1,8 +1,4 @@ /* - * drivers/video/tegra/host/gk20a/clk_gk20a.h - * - * GK20A Graphics - * * Copyright (c) 2011 - 2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it @@ -14,12 +10,11 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . */ -#ifndef _NVHOST_CLK_GK20A_H_ -#define _NVHOST_CLK_GK20A_H_ +#ifndef CLK_GK20A_H +#define CLK_GK20A_H #include @@ -102,4 +97,4 @@ static inline unsigned long rate_gpu_to_gpc2clk(unsigned long rate) return (rate * 2) / KHZ; } -#endif /* _NVHOST_CLK_GK20A_H_ */ +#endif /* CLK_GK20A_H */ diff --git a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c index d1560cad..0feb92a5 100644 --- a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c @@ -1,6 +1,4 @@ /* - * GK20A Ctrl - * * Copyright (c) 2011-2014, NVIDIA Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it @@ -57,9 +55,9 @@ int gk20a_ctrl_dev_release(struct inode *inode, struct file *filp) static long gk20a_ctrl_ioctl_gpu_characteristics( struct gk20a *g, - struct nvhost_gpu_get_characteristics *request) + struct nvgpu_gpu_get_characteristics *request) { - struct nvhost_gpu_characteristics *pgpu = &g->gpu_characteristics; + struct nvgpu_gpu_characteristics *pgpu = &g->gpu_characteristics; long err = 0; if (request->gpu_characteristics_buf_size > 0) { @@ -81,14 +79,14 @@ gk20a_ctrl_ioctl_gpu_characteristics( static int gk20a_ctrl_prepare_compressible_read( struct gk20a *g, - struct nvhost_gpu_prepare_compressible_read_args *args) + struct nvgpu_gpu_prepare_compressible_read_args *args) { - struct nvhost_fence fence; + struct nvgpu_fence fence; struct gk20a_fence *fence_out = NULL; int ret = 0; int flags = args->submit_flags; - fence.syncpt_id = args->fence.syncpt_id; + fence.id = args->fence.syncpt_id; fence.value = args->fence.syncpt_value; ret = gk20a_busy(g->dev); @@ -107,8 +105,8 @@ static int gk20a_ctrl_prepare_compressible_read( return ret; /* Convert fence_out to something we can pass back to user space. */ - if (flags & NVHOST_SUBMIT_GPFIFO_FLAGS_FENCE_GET) { - if (flags & NVHOST_SUBMIT_GPFIFO_FLAGS_SYNC_FENCE) { + if (flags & NVGPU_SUBMIT_GPFIFO_FLAGS_FENCE_GET) { + if (flags & NVGPU_SUBMIT_GPFIFO_FLAGS_SYNC_FENCE) { if (fence_out) { int fd = gk20a_fence_install_fd(fence_out); if (fd < 0) @@ -136,7 +134,7 @@ static int gk20a_ctrl_prepare_compressible_read( static int gk20a_ctrl_mark_compressible_write( struct gk20a *g, - struct nvhost_gpu_mark_compressible_write_args *args) + struct nvgpu_gpu_mark_compressible_write_args *args) { int ret = 0; @@ -154,11 +152,11 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg { struct platform_device *dev = filp->private_data; struct gk20a *g = get_gk20a(dev); - struct nvhost_gpu_zcull_get_ctx_size_args *get_ctx_size_args; - struct nvhost_gpu_zcull_get_info_args *get_info_args; - struct nvhost_gpu_zbc_set_table_args *set_table_args; - struct nvhost_gpu_zbc_query_table_args *query_table_args; - u8 buf[NVHOST_GPU_IOCTL_MAX_ARG_SIZE]; + struct nvgpu_gpu_zcull_get_ctx_size_args *get_ctx_size_args; + struct nvgpu_gpu_zcull_get_info_args *get_info_args; + struct nvgpu_gpu_zbc_set_table_args *set_table_args; + struct nvgpu_gpu_zbc_query_table_args *query_table_args; + u8 buf[NVGPU_GPU_IOCTL_MAX_ARG_SIZE]; struct gr_zcull_info *zcull_info; struct zbc_entry *zbc_val; struct zbc_query_params *zbc_tbl; @@ -169,12 +167,12 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg gk20a_dbg_fn(""); - if ((_IOC_TYPE(cmd) != NVHOST_GPU_IOCTL_MAGIC) || + if ((_IOC_TYPE(cmd) != NVGPU_GPU_IOCTL_MAGIC) || (_IOC_NR(cmd) == 0) || - (_IOC_NR(cmd) > NVHOST_GPU_IOCTL_LAST)) + (_IOC_NR(cmd) > NVGPU_GPU_IOCTL_LAST)) return -EINVAL; - BUG_ON(_IOC_SIZE(cmd) > NVHOST_GPU_IOCTL_MAX_ARG_SIZE); + BUG_ON(_IOC_SIZE(cmd) > NVGPU_GPU_IOCTL_MAX_ARG_SIZE); if (_IOC_DIR(cmd) & _IOC_WRITE) { if (copy_from_user(buf, (void __user *)arg, _IOC_SIZE(cmd))) @@ -190,16 +188,16 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg } switch (cmd) { - case NVHOST_GPU_IOCTL_ZCULL_GET_CTX_SIZE: - get_ctx_size_args = (struct nvhost_gpu_zcull_get_ctx_size_args *)buf; + case NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE: + get_ctx_size_args = (struct nvgpu_gpu_zcull_get_ctx_size_args *)buf; get_ctx_size_args->size = gr_gk20a_get_ctxsw_zcull_size(g, &g->gr); break; - case NVHOST_GPU_IOCTL_ZCULL_GET_INFO: - get_info_args = (struct nvhost_gpu_zcull_get_info_args *)buf; + case NVGPU_GPU_IOCTL_ZCULL_GET_INFO: + get_info_args = (struct nvgpu_gpu_zcull_get_info_args *)buf; - memset(get_info_args, 0, sizeof(struct nvhost_gpu_zcull_get_info_args)); + memset(get_info_args, 0, sizeof(struct nvgpu_gpu_zcull_get_info_args)); zcull_info = kzalloc(sizeof(struct gr_zcull_info), GFP_KERNEL); if (zcull_info == NULL) @@ -224,8 +222,8 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg kfree(zcull_info); break; - case NVHOST_GPU_IOCTL_ZBC_SET_TABLE: - set_table_args = (struct nvhost_gpu_zbc_set_table_args *)buf; + case NVGPU_GPU_IOCTL_ZBC_SET_TABLE: + set_table_args = (struct nvgpu_gpu_zbc_set_table_args *)buf; #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION if (platform->virtual_dev) @@ -264,8 +262,8 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg if (zbc_val) kfree(zbc_val); break; - case NVHOST_GPU_IOCTL_ZBC_QUERY_TABLE: - query_table_args = (struct nvhost_gpu_zbc_query_table_args *)buf; + case NVGPU_GPU_IOCTL_ZBC_QUERY_TABLE: + query_table_args = (struct nvgpu_gpu_zbc_query_table_args *)buf; zbc_tbl = kzalloc(sizeof(struct zbc_query_params), GFP_KERNEL); if (zbc_tbl == NULL) @@ -303,17 +301,17 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg kfree(zbc_tbl); break; - case NVHOST_GPU_IOCTL_GET_CHARACTERISTICS: + case NVGPU_GPU_IOCTL_GET_CHARACTERISTICS: err = gk20a_ctrl_ioctl_gpu_characteristics( - g, (struct nvhost_gpu_get_characteristics *)buf); + g, (struct nvgpu_gpu_get_characteristics *)buf); break; - case NVHOST_GPU_IOCTL_PREPARE_COMPRESSIBLE_READ: + case NVGPU_GPU_IOCTL_PREPARE_COMPRESSIBLE_READ: err = gk20a_ctrl_prepare_compressible_read(g, - (struct nvhost_gpu_prepare_compressible_read_args *)buf); + (struct nvgpu_gpu_prepare_compressible_read_args *)buf); break; - case NVHOST_GPU_IOCTL_MARK_COMPRESSIBLE_WRITE: + case NVGPU_GPU_IOCTL_MARK_COMPRESSIBLE_WRITE: err = gk20a_ctrl_mark_compressible_write(g, - (struct nvhost_gpu_mark_compressible_write_args *)buf); + (struct nvgpu_gpu_mark_compressible_write_args *)buf); break; default: dev_dbg(dev_from_gk20a(g), "unrecognized gpu ioctl cmd: 0x%x", cmd); diff --git a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.h b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.h index ac9c253e..26ca4e20 100644 --- a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.h @@ -1,8 +1,4 @@ /* - * drivers/video/tegra/host/gk20a/gk20a_ctrl.h - * - * GK20A Ctrl - * * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it @@ -14,15 +10,14 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . */ -#ifndef _NVHOST_GK20A_CTRL_H_ -#define _NVHOST_GK20A_CTRL_H_ +#ifndef CTRL_GK20A_H +#define CTRL_GK20A_H int gk20a_ctrl_dev_open(struct inode *inode, struct file *filp); int gk20a_ctrl_dev_release(struct inode *inode, struct file *filp); long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg); -#endif /* _NVHOST_GK20A_CTRL_H_ */ +#endif /* CTRL_GK20A_H */ diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c index 1fefb659..2f1a08d8 100644 --- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c @@ -154,7 +154,7 @@ static void gk20a_dbg_gpu_events_clear(struct dbg_session_gk20a *dbg_s) } static int gk20a_dbg_gpu_events_ctrl(struct dbg_session_gk20a *dbg_s, - struct nvhost_dbg_gpu_events_ctrl_args *args) + struct nvgpu_dbg_gpu_events_ctrl_args *args) { int ret = 0; @@ -167,15 +167,15 @@ static int gk20a_dbg_gpu_events_ctrl(struct dbg_session_gk20a *dbg_s, } switch (args->cmd) { - case NVHOST_DBG_GPU_EVENTS_CTRL_CMD_ENABLE: + case NVGPU_DBG_GPU_EVENTS_CTRL_CMD_ENABLE: gk20a_dbg_gpu_events_enable(dbg_s); break; - case NVHOST_DBG_GPU_EVENTS_CTRL_CMD_DISABLE: + case NVGPU_DBG_GPU_EVENTS_CTRL_CMD_DISABLE: gk20a_dbg_gpu_events_disable(dbg_s); break; - case NVHOST_DBG_GPU_EVENTS_CTRL_CMD_CLEAR: + case NVGPU_DBG_GPU_EVENTS_CTRL_CMD_CLEAR: gk20a_dbg_gpu_events_clear(dbg_s); break; @@ -278,7 +278,7 @@ static int dbg_unbind_channel_gk20a(struct dbg_session_gk20a *dbg_s) * which called powergate disable ioctl, to be killed without calling * powergate enable ioctl */ - dbg_set_powergate(dbg_s, NVHOST_DBG_GPU_POWERGATE_MODE_ENABLE); + dbg_set_powergate(dbg_s, NVGPU_DBG_GPU_POWERGATE_MODE_ENABLE); dbg_s->ch = NULL; fput(dbg_s->ch_f); @@ -307,7 +307,7 @@ int gk20a_dbg_gpu_dev_release(struct inode *inode, struct file *filp) } static int dbg_bind_channel_gk20a(struct dbg_session_gk20a *dbg_s, - struct nvhost_dbg_gpu_bind_channel_args *args) + struct nvgpu_dbg_gpu_bind_channel_args *args) { struct file *f; struct gk20a *g; @@ -350,31 +350,31 @@ static int dbg_bind_channel_gk20a(struct dbg_session_gk20a *dbg_s, return 0; } -static int nvhost_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s, - struct nvhost_dbg_gpu_exec_reg_ops_args *args); +static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s, + struct nvgpu_dbg_gpu_exec_reg_ops_args *args); -static int nvhost_ioctl_powergate_gk20a(struct dbg_session_gk20a *dbg_s, - struct nvhost_dbg_gpu_powergate_args *args); +static int nvgpu_ioctl_powergate_gk20a(struct dbg_session_gk20a *dbg_s, + struct nvgpu_dbg_gpu_powergate_args *args); -static int nvhost_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s, - struct nvhost_dbg_gpu_smpc_ctxsw_mode_args *args); +static int nvgpu_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s, + struct nvgpu_dbg_gpu_smpc_ctxsw_mode_args *args); long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) { struct dbg_session_gk20a *dbg_s = filp->private_data; struct gk20a *g = get_gk20a(dbg_s->pdev); - u8 buf[NVHOST_DBG_GPU_IOCTL_MAX_ARG_SIZE]; + u8 buf[NVGPU_DBG_GPU_IOCTL_MAX_ARG_SIZE]; int err = 0; gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, ""); - if ((_IOC_TYPE(cmd) != NVHOST_DBG_GPU_IOCTL_MAGIC) || + if ((_IOC_TYPE(cmd) != NVGPU_DBG_GPU_IOCTL_MAGIC) || (_IOC_NR(cmd) == 0) || - (_IOC_NR(cmd) > NVHOST_DBG_GPU_IOCTL_LAST)) + (_IOC_NR(cmd) > NVGPU_DBG_GPU_IOCTL_LAST)) return -EINVAL; - BUG_ON(_IOC_SIZE(cmd) > NVHOST_DBG_GPU_IOCTL_MAX_ARG_SIZE); + BUG_ON(_IOC_SIZE(cmd) > NVGPU_DBG_GPU_IOCTL_MAX_ARG_SIZE); if (_IOC_DIR(cmd) & _IOC_WRITE) { if (copy_from_user(buf, (void __user *)arg, _IOC_SIZE(cmd))) @@ -390,32 +390,32 @@ long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd, } switch (cmd) { - case NVHOST_DBG_GPU_IOCTL_BIND_CHANNEL: + case NVGPU_DBG_GPU_IOCTL_BIND_CHANNEL: err = dbg_bind_channel_gk20a(dbg_s, - (struct nvhost_dbg_gpu_bind_channel_args *)buf); + (struct nvgpu_dbg_gpu_bind_channel_args *)buf); gk20a_dbg(gpu_dbg_gpu_dbg, "ret=%d", err); break; - case NVHOST_DBG_GPU_IOCTL_REG_OPS: - err = nvhost_ioctl_channel_reg_ops(dbg_s, - (struct nvhost_dbg_gpu_exec_reg_ops_args *)buf); + case NVGPU_DBG_GPU_IOCTL_REG_OPS: + err = nvgpu_ioctl_channel_reg_ops(dbg_s, + (struct nvgpu_dbg_gpu_exec_reg_ops_args *)buf); gk20a_dbg(gpu_dbg_gpu_dbg, "ret=%d", err); break; - case NVHOST_DBG_GPU_IOCTL_POWERGATE: - err = nvhost_ioctl_powergate_gk20a(dbg_s, - (struct nvhost_dbg_gpu_powergate_args *)buf); + case NVGPU_DBG_GPU_IOCTL_POWERGATE: + err = nvgpu_ioctl_powergate_gk20a(dbg_s, + (struct nvgpu_dbg_gpu_powergate_args *)buf); gk20a_dbg(gpu_dbg_gpu_dbg, "ret=%d", err); break; - case NVHOST_DBG_GPU_IOCTL_EVENTS_CTRL: + case NVGPU_DBG_GPU_IOCTL_EVENTS_CTRL: err = gk20a_dbg_gpu_events_ctrl(dbg_s, - (struct nvhost_dbg_gpu_events_ctrl_args *)buf); + (struct nvgpu_dbg_gpu_events_ctrl_args *)buf); break; - case NVHOST_DBG_GPU_IOCTL_SMPC_CTXSW_MODE: - err = nvhost_dbg_gpu_ioctl_smpc_ctxsw_mode(dbg_s, - (struct nvhost_dbg_gpu_smpc_ctxsw_mode_args *)buf); + case NVGPU_DBG_GPU_IOCTL_SMPC_CTXSW_MODE: + err = nvgpu_dbg_gpu_ioctl_smpc_ctxsw_mode(dbg_s, + (struct nvgpu_dbg_gpu_smpc_ctxsw_mode_args *)buf); break; default: @@ -456,15 +456,15 @@ static bool gr_context_info_available(struct dbg_session_gk20a *dbg_s, } -static int nvhost_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s, - struct nvhost_dbg_gpu_exec_reg_ops_args *args) +static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s, + struct nvgpu_dbg_gpu_exec_reg_ops_args *args) { int err = 0, powergate_err = 0; bool is_pg_disabled = false; struct device *dev = dbg_s->dev; struct gk20a *g = get_gk20a(dbg_s->pdev); - struct nvhost_dbg_gpu_reg_op *ops; + struct nvgpu_dbg_gpu_reg_op *ops; u64 ops_size = sizeof(ops[0]) * args->num_ops; gk20a_dbg_fn("%d ops, total size %llu", args->num_ops, ops_size); @@ -506,7 +506,7 @@ static int nvhost_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s, if (!dbg_s->is_pg_disabled) { powergate_err = dbg_set_powergate(dbg_s, - NVHOST_DBG_GPU_POWERGATE_MODE_DISABLE); + NVGPU_DBG_GPU_POWERGATE_MODE_DISABLE); is_pg_disabled = true; } @@ -515,7 +515,7 @@ static int nvhost_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s, /* enable powergate, if previously disabled */ if (is_pg_disabled) { powergate_err = dbg_set_powergate(dbg_s, - NVHOST_DBG_GPU_POWERGATE_MODE_ENABLE); + NVGPU_DBG_GPU_POWERGATE_MODE_ENABLE); } } @@ -554,7 +554,7 @@ static int dbg_set_powergate(struct dbg_session_gk20a *dbg_s, dev_name(dbg_s->dev), powermode); switch (powermode) { - case NVHOST_DBG_GPU_POWERGATE_MODE_DISABLE: + case NVGPU_DBG_GPU_POWERGATE_MODE_DISABLE: /* save off current powergate, clk state. * set gpu module's can_powergate = 0. * set gpu module's clk to max. @@ -595,7 +595,7 @@ static int dbg_set_powergate(struct dbg_session_gk20a *dbg_s, dbg_s->is_pg_disabled = true; break; - case NVHOST_DBG_GPU_POWERGATE_MODE_ENABLE: + case NVGPU_DBG_GPU_POWERGATE_MODE_ENABLE: /* restore (can) powergate, clk state */ /* release pending exceptions to fault/be handled as usual */ /*TBD: ordering of these? */ @@ -640,8 +640,8 @@ static int dbg_set_powergate(struct dbg_session_gk20a *dbg_s, return err; } -static int nvhost_ioctl_powergate_gk20a(struct dbg_session_gk20a *dbg_s, - struct nvhost_dbg_gpu_powergate_args *args) +static int nvgpu_ioctl_powergate_gk20a(struct dbg_session_gk20a *dbg_s, + struct nvgpu_dbg_gpu_powergate_args *args) { int err; struct gk20a *g = get_gk20a(dbg_s->pdev); @@ -654,8 +654,8 @@ static int nvhost_ioctl_powergate_gk20a(struct dbg_session_gk20a *dbg_s, return err; } -static int nvhost_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s, - struct nvhost_dbg_gpu_smpc_ctxsw_mode_args *args) +static int nvgpu_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s, + struct nvgpu_dbg_gpu_smpc_ctxsw_mode_args *args) { int err; struct gk20a *g = get_gk20a(dbg_s->pdev); @@ -677,7 +677,7 @@ static int nvhost_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s, } err = gr_gk20a_update_smpc_ctxsw_mode(g, ch_gk20a, - args->mode == NVHOST_DBG_GPU_SMPC_CTXSW_MODE_CTXSW); + args->mode == NVGPU_DBG_GPU_SMPC_CTXSW_MODE_CTXSW); if (err) { gk20a_err(dev_from_gk20a(dbg_s->g), "error (%d) during smpc ctxsw mode update\n", err); @@ -688,12 +688,12 @@ static int nvhost_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s, * it was already swapped out in/out once or not, etc. */ { - struct nvhost_dbg_gpu_reg_op ops[4]; + struct nvgpu_dbg_gpu_reg_op ops[4]; int i; for (i = 0; i < ARRAY_SIZE(ops); i++) { - ops[i].op = NVHOST_DBG_GPU_REG_OP_WRITE_32; - ops[i].type = NVHOST_DBG_GPU_REG_OP_TYPE_GR_CTX; - ops[i].status = NVHOST_DBG_GPU_REG_OP_STATUS_SUCCESS; + ops[i].op = NVGPU_DBG_GPU_REG_OP_WRITE_32; + ops[i].type = NVGPU_DBG_GPU_REG_OP_TYPE_GR_CTX; + ops[i].status = NVGPU_DBG_GPU_REG_OP_STATUS_SUCCESS; ops[i].value_hi = 0; ops[i].and_n_mask_lo = 0; ops[i].and_n_mask_hi = 0; diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.h b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.h index 49827608..27084c0d 100644 --- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.h @@ -15,8 +15,8 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ -#ifndef __DBG_GPU_GK20A_H_ -#define __DBG_GPU_GK20A_H_ +#ifndef DBG_GPU_GK20A_H +#define DBG_GPU_GK20A_H #include /* module debug driver interface */ @@ -33,7 +33,7 @@ void gk20a_dbg_gpu_post_events(struct channel_gk20a *fault_ch); struct dbg_gpu_session_ops { int (*exec_reg_ops)(struct dbg_session_gk20a *dbg_s, - struct nvhost_dbg_gpu_reg_op *ops, + struct nvgpu_dbg_gpu_reg_op *ops, u64 num_ops); }; @@ -80,4 +80,4 @@ struct dbg_session_gk20a { extern struct dbg_gpu_session_ops dbg_gpu_session_ops_gk20a; -#endif /* __DBG_GPU_GK20A_H_ */ +#endif /* DBG_GPU_GK20A_H */ diff --git a/drivers/gpu/nvgpu/gk20a/debug_gk20a.c b/drivers/gpu/nvgpu/gk20a/debug_gk20a.c index f5e0b73d..f41d883f 100644 --- a/drivers/gpu/nvgpu/gk20a/debug_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/debug_gk20a.c @@ -14,7 +14,10 @@ * */ +#ifdef CONFIG_TEGRA_GK20A #include +#endif + #include #include @@ -141,6 +144,7 @@ static void gk20a_debug_show_channel(struct gk20a *g, gk20a_mem_rd32(inst_ptr, ram_fc_semaphorec_w()), gk20a_mem_rd32(inst_ptr, ram_fc_semaphored_w())); +#ifdef CONFIG_TEGRA_GK20A if ((pbdma_syncpointb_op_v(syncpointb) == pbdma_syncpointb_op_wait_v()) && (pbdma_syncpointb_wait_switch_v(syncpointb) == pbdma_syncpointb_wait_switch_en_v())) @@ -150,6 +154,7 @@ static void gk20a_debug_show_channel(struct gk20a *g, nvhost_syncpt_get_name(g->host1x_dev, pbdma_syncpointb_syncpt_index_v(syncpointb)), pbdma_syncpointa_payload_v(syncpointa)); +#endif gk20a_debug_output(o, "\n"); } diff --git a/drivers/gpu/nvgpu/gk20a/debug_gk20a.h b/drivers/gpu/nvgpu/gk20a/debug_gk20a.h index cd2e09c3..c70b19d9 100644 --- a/drivers/gpu/nvgpu/gk20a/debug_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/debug_gk20a.h @@ -17,6 +17,8 @@ #ifndef _DEBUG_GK20A_H_ #define _DEBUG_GK20A_H_ +struct platform_device; + extern unsigned int gk20a_debug_trace_cmdbuf; void gk20a_debug_dump(struct platform_device *pdev); diff --git a/drivers/gpu/nvgpu/gk20a/fb_gk20a.h b/drivers/gpu/nvgpu/gk20a/fb_gk20a.h index 34c21c9b..49dd5fd7 100644 --- a/drivers/gpu/nvgpu/gk20a/fb_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fb_gk20a.h @@ -1,6 +1,4 @@ /* - * GK20A FB - * * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it @@ -13,8 +11,8 @@ * more details. */ -#ifndef _NVHOST_GK20A_FB -#define _NVHOST_GK20A_FB +#ifndef FB_GK20A_H +#define FB_GK20A_H struct gk20a; void gk20a_init_fb(struct gpu_ops *gops); diff --git a/drivers/gpu/nvgpu/gk20a/fence_gk20a.c b/drivers/gpu/nvgpu/gk20a/fence_gk20a.c index 4b98a4e7..32c66037 100644 --- a/drivers/gpu/nvgpu/gk20a/fence_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fence_gk20a.c @@ -1,8 +1,4 @@ /* - * drivers/video/tegra/host/gk20a/fence_gk20a.c - * - * GK20A Fences - * * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it @@ -31,6 +27,7 @@ #ifdef CONFIG_TEGRA_GK20A #include +#include #endif struct gk20a_fence_ops { diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 0c8bc6f4..05377c3d 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -1,6 +1,4 @@ /* - * drivers/video/tegra/host/gk20a/fifo_gk20a.c - * * GK20A Graphics FIFO (gr host) * * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. @@ -27,6 +25,7 @@ #include "gk20a.h" #include "debug_gk20a.h" +#include "semaphore_gk20a.h" #include "hw_fifo_gk20a.h" #include "hw_pbdma_gk20a.h" #include "hw_ccsr_gk20a.h" @@ -917,11 +916,11 @@ static bool gk20a_fifo_set_ctx_mmu_error(struct gk20a *g, * error condition. * Don't overwrite error flag. */ /* Fifo timeout debug spew is controlled by user */ - if (err == NVHOST_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT) + if (err == NVGPU_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT) verbose = ch->timeout_debug_dump; } else { gk20a_set_error_notifier(ch, - NVHOST_CHANNEL_FIFO_ERROR_MMU_ERR_FLT); + NVGPU_CHANNEL_FIFO_ERROR_MMU_ERR_FLT); } } /* mark channel as faulted */ @@ -1294,13 +1293,13 @@ int gk20a_fifo_force_reset_ch(struct channel_gk20a *ch, bool verbose) mutex_lock(&tsg->ch_list_lock); list_for_each_entry(ch_tsg, &tsg->ch_list, ch_entry) { gk20a_set_error_notifier(ch_tsg, - NVHOST_CHANNEL_RESETCHANNEL_VERIF_ERROR); + NVGPU_CHANNEL_RESETCHANNEL_VERIF_ERROR); } mutex_unlock(&tsg->ch_list_lock); gk20a_fifo_recover_tsg(ch->g, ch->tsgid, verbose); } else { gk20a_set_error_notifier(ch, - NVHOST_CHANNEL_RESETCHANNEL_VERIF_ERROR); + NVGPU_CHANNEL_RESETCHANNEL_VERIF_ERROR); gk20a_fifo_recover_ch(ch->g, ch->hw_chid, verbose); } @@ -1364,7 +1363,7 @@ static bool gk20a_fifo_handle_sched_error(struct gk20a *g) if (gk20a_channel_update_and_check_timeout(ch, GRFIFO_TIMEOUT_CHECK_PERIOD_US / 1000)) { gk20a_set_error_notifier(ch, - NVHOST_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT); + NVGPU_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT); gk20a_err(dev_from_gk20a(g), "fifo sched ctxsw timeout error:" "engine = %u, ch = %d", engine_id, id); @@ -1504,7 +1503,7 @@ static u32 gk20a_fifo_handle_pbdma_intr(struct device *dev, struct channel_gk20a *ch = &f->channel[id]; gk20a_set_error_notifier(ch, - NVHOST_CHANNEL_PBDMA_ERROR); + NVGPU_CHANNEL_PBDMA_ERROR); gk20a_fifo_recover_ch(g, id, true); } else if (fifo_pbdma_status_id_type_v(status) == fifo_pbdma_status_id_type_tsgid_v()) { @@ -1514,7 +1513,7 @@ static u32 gk20a_fifo_handle_pbdma_intr(struct device *dev, mutex_lock(&tsg->ch_list_lock); list_for_each_entry(ch, &tsg->ch_list, ch_entry) { gk20a_set_error_notifier(ch, - NVHOST_CHANNEL_PBDMA_ERROR); + NVGPU_CHANNEL_PBDMA_ERROR); } mutex_unlock(&tsg->ch_list_lock); gk20a_fifo_recover_tsg(g, id, true); @@ -1644,7 +1643,7 @@ static int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg) mutex_lock(&tsg->ch_list_lock); list_for_each_entry(ch, &tsg->ch_list, ch_entry) { gk20a_set_error_notifier(ch, - NVHOST_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT); + NVGPU_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT); } mutex_unlock(&tsg->ch_list_lock); gk20a_fifo_recover_tsg(g, id, true); @@ -1655,7 +1654,7 @@ static int __locked_fifo_preempt(struct gk20a *g, u32 id, bool is_tsg) "preempt channel %d timeout\n", id); gk20a_set_error_notifier(ch, - NVHOST_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT); + NVGPU_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT); gk20a_fifo_recover_ch(g, id, true); } } diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index acae38aa..ae108875 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c @@ -1,6 +1,4 @@ /* - * drivers/video/tegra/host/gk20a/gk20a.c - * * GK20A Graphics * * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. @@ -45,6 +43,10 @@ #include #include +#ifdef CONFIG_TEGRA_GK20A +#include +#endif + #include "gk20a.h" #include "debug_gk20a.h" #include "ctrl_gk20a.h" @@ -57,7 +59,6 @@ #include "gk20a_scale.h" #include "dbg_gpu_gk20a.h" #include "hal.h" -#include "nvhost_acm.h" #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION #include "vgpu/vgpu.h" #endif @@ -850,11 +851,11 @@ static int gk20a_pm_prepare_poweroff(struct device *dev) static void gk20a_detect_chip(struct gk20a *g) { - struct nvhost_gpu_characteristics *gpu = &g->gpu_characteristics; + struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics; u32 mc_boot_0_value = gk20a_readl(g, mc_boot_0_r()); gpu->arch = mc_boot_0_architecture_v(mc_boot_0_value) << - NVHOST_GPU_ARCHITECTURE_SHIFT; + NVGPU_GPU_ARCHITECTURE_SHIFT; gpu->impl = mc_boot_0_implementation_v(mc_boot_0_value); gpu->rev = (mc_boot_0_major_revision_v(mc_boot_0_value) << 4) | @@ -1622,7 +1623,7 @@ static int __exit gk20a_remove(struct platform_device *dev) pm_runtime_put(&dev->dev); pm_runtime_disable(&dev->dev); #else - nvhost_module_disable_clk(&dev->dev); + gk20a_pm_disable_clk(&dev->dev); #endif return 0; @@ -1894,7 +1895,7 @@ int gk20a_do_unidle(void) int gk20a_init_gpu_characteristics(struct gk20a *g) { - struct nvhost_gpu_characteristics *gpu = &g->gpu_characteristics; + struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics; gpu->L2_cache_size = g->ops.ltc.determine_L2_size_bytes(g); gpu->on_board_video_memory_size = 0; /* integrated GPU */ @@ -1902,18 +1903,18 @@ int gk20a_init_gpu_characteristics(struct gk20a *g) gpu->num_gpc = g->gr.gpc_count; gpu->num_tpc_per_gpc = g->gr.max_tpc_per_gpc_count; - gpu->bus_type = NVHOST_GPU_BUS_TYPE_AXI; /* always AXI for now */ + gpu->bus_type = NVGPU_GPU_BUS_TYPE_AXI; /* always AXI for now */ gpu->big_page_size = g->mm.big_page_size; gpu->compression_page_size = g->mm.compression_page_size; gpu->pde_coverage_bit_count = g->mm.pde_stride_shift; - gpu->flags = NVHOST_GPU_FLAGS_SUPPORT_PARTIAL_MAPPINGS - | NVHOST_GPU_FLAGS_SUPPORT_SPARSE_ALLOCS; + gpu->flags = NVGPU_GPU_FLAGS_SUPPORT_PARTIAL_MAPPINGS + | NVGPU_GPU_FLAGS_SUPPORT_SPARSE_ALLOCS; if (IS_ENABLED(CONFIG_TEGRA_GK20A) && gk20a_platform_has_syncpoints(g->dev)) - gpu->flags |= NVHOST_GPU_FLAGS_HAS_SYNCPOINTS; + gpu->flags |= NVGPU_GPU_FLAGS_HAS_SYNCPOINTS; gpu->reserved = 0; diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index ae640277..5429a570 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -1,6 +1,4 @@ /* - * drivers/video/tegra/host/gk20a/gk20a.h - * * GK20A Graphics * * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. @@ -14,12 +12,11 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . */ -#ifndef _NVHOST_GK20A_H_ -#define _NVHOST_GK20A_H_ +#ifndef GK20A_H +#define GK20A_H struct gk20a; @@ -133,9 +130,9 @@ struct gpu_ops { u32 (*get_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index); void (*free_channel_ctx)(struct channel_gk20a *c); int (*alloc_obj_ctx)(struct channel_gk20a *c, - struct nvhost_alloc_obj_ctx_args *args); + struct nvgpu_alloc_obj_ctx_args *args); int (*free_obj_ctx)(struct channel_gk20a *c, - struct nvhost_free_obj_ctx_args *args); + struct nvgpu_free_obj_ctx_args *args); int (*bind_ctxsw_zcull)(struct gk20a *g, struct gr_gk20a *gr, struct channel_gk20a *c, u64 zcull_va, u32 mode); @@ -405,7 +402,7 @@ struct gk20a { spinlock_t mc_enable_lock; - struct nvhost_gpu_characteristics gpu_characteristics; + struct nvgpu_gpu_characteristics gpu_characteristics; struct { struct cdev cdev; @@ -504,11 +501,11 @@ struct gk20a_cyclestate_buffer_elem { #ifdef CONFIG_DEBUG_FS /* debug info, default is compiled-in but effectively disabled (0 mask) */ #define GK20A_DEBUG - /*e.g: echo 1 > /d/tegra_host/dbg_mask */ + /*e.g: echo 1 > /d/gk20a.0/dbg_mask */ #define GK20A_DEFAULT_DBG_MASK 0 #else /* manually enable and turn it on the mask */ - /*#define NVHOST_DEBUG*/ + /*#define NVGPU_DEBUG*/ #define GK20A_DEFAULT_DBG_MASK (dbg_info) #endif @@ -719,21 +716,21 @@ int __gk20a_do_unidle(struct platform_device *pdev); const struct firmware * gk20a_request_firmware(struct gk20a *g, const char *fw_name); -#define NVHOST_GPU_ARCHITECTURE_SHIFT 4 +#define NVGPU_GPU_ARCHITECTURE_SHIFT 4 -/* constructs unique and compact GPUID from nvhost_gpu_characteristics +/* constructs unique and compact GPUID from nvgpu_gpu_characteristics * arch/impl fields */ #define GK20A_GPUID(arch, impl) ((u32) ((arch) | (impl))) #define GK20A_GPUID_GK20A \ - GK20A_GPUID(NVHOST_GPU_ARCH_GK100, NVHOST_GPU_IMPL_GK20A) + GK20A_GPUID(NVGPU_GPU_ARCH_GK100, NVGPU_GPU_IMPL_GK20A) #define GK20A_GPUID_GM20B \ - GK20A_GPUID(NVHOST_GPU_ARCH_GM200, NVHOST_GPU_IMPL_GM20B) + GK20A_GPUID(NVGPU_GPU_ARCH_GM200, NVGPU_GPU_IMPL_GM20B) int gk20a_init_gpu_characteristics(struct gk20a *g); int gk20a_user_init(struct platform_device *dev); void gk20a_user_deinit(struct platform_device *dev); -#endif /* _NVHOST_GK20A_H_ */ +#endif /* GK20A_H */ diff --git a/drivers/gpu/nvgpu/gk20a/gk20a_allocator.h b/drivers/gpu/nvgpu/gk20a/gk20a_allocator.h index cd72ec9c..5621800e 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a_allocator.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a_allocator.h @@ -1,6 +1,4 @@ /* - * gk20a allocator - * * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it @@ -16,8 +14,8 @@ * along with this program. If not, see . */ -#ifndef __NVHOST_ALLOCATOR_H__ -#define __NVHOST_ALLOCATOR_H__ +#ifndef GK20A_ALLOCATOR_H +#define GK20A_ALLOCATOR_H #include #include @@ -112,4 +110,4 @@ do { \ #endif /* ALLOCATOR_DEBUG */ -#endif /*__NVHOST_ALLOCATOR_H__ */ +#endif /* GK20A_ALLOCATOR_H */ diff --git a/drivers/gpu/nvgpu/gk20a/gk20a_scale.h b/drivers/gpu/nvgpu/gk20a/gk20a_scale.h index e76b1662..561ecaed 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a_scale.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a_scale.h @@ -19,7 +19,6 @@ #ifndef GK20A_SCALE_H #define GK20A_SCALE_H -#include #include struct platform_device; diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 90838c64..11bca5bb 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -51,6 +51,7 @@ #include "gr_pri_gk20a.h" #include "regops_gk20a.h" #include "dbg_gpu_gk20a.h" +#include "semaphore_gk20a.h" #define BLK_SIZE (256) @@ -2174,8 +2175,8 @@ int gr_gk20a_load_ctxsw_ucode(struct gk20a *g) * In case bootloader is not supported, revert to the old way of * loading gr ucode, without the faster bootstrap routine. */ - if (g->gpu_characteristics.arch != NVHOST_GPU_ARCH_GK100 && - g->gpu_characteristics.arch != NVHOST_GPU_ARCH_GM200) { + if (g->gpu_characteristics.arch != NVGPU_GPU_ARCH_GK100 && + g->gpu_characteristics.arch != NVGPU_GPU_ARCH_GM200) { gr_gk20a_load_falcon_dmem(g); gr_gk20a_load_falcon_imem(g); gr_gk20a_start_falcon_ucode(g); @@ -2437,7 +2438,7 @@ static int gr_gk20a_map_global_ctx_buffers(struct gk20a *g, } gpu_va = gk20a_gmmu_map(ch_vm, &sgt, size, - NVHOST_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, + NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, gk20a_mem_flag_none); if (!gpu_va) goto clean_up; @@ -2454,7 +2455,7 @@ static int gr_gk20a_map_global_ctx_buffers(struct gk20a *g, } gpu_va = gk20a_gmmu_map(ch_vm, &sgt, size, - NVHOST_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, + NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, gk20a_mem_flag_none); if (!gpu_va) goto clean_up; @@ -2471,7 +2472,7 @@ static int gr_gk20a_map_global_ctx_buffers(struct gk20a *g, } gpu_va = gk20a_gmmu_map(ch_vm, &sgt, size, - NVHOST_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, + NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, gk20a_mem_flag_none); if (!gpu_va) goto clean_up; @@ -2574,7 +2575,7 @@ static int __gr_gk20a_alloc_gr_ctx(struct gk20a *g, goto err_free; gr_ctx->gpu_va = gk20a_gmmu_map(vm, &sgt, gr_ctx->size, - NVHOST_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, + NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, gk20a_mem_flag_none); if (!gr_ctx->gpu_va) goto err_free_sgt; @@ -2780,7 +2781,7 @@ static bool gr_gk20a_is_valid_class(struct gk20a *g, u32 class_num) } int gk20a_alloc_obj_ctx(struct channel_gk20a *c, - struct nvhost_alloc_obj_ctx_args *args) + struct nvgpu_alloc_obj_ctx_args *args) { struct gk20a *g = c->g; struct fifo_gk20a *f = &g->fifo; @@ -2943,7 +2944,7 @@ out: } int gk20a_free_obj_ctx(struct channel_gk20a *c, - struct nvhost_free_obj_ctx_args *args) + struct nvgpu_free_obj_ctx_args *args) { unsigned long timeout = gk20a_get_gr_idle_timeout(c->g); @@ -4956,7 +4957,7 @@ static int gk20a_gr_handle_semaphore_timeout_pending(struct gk20a *g, struct channel_gk20a *ch = &f->channel[isr_data->chid]; gk20a_dbg_fn(""); gk20a_set_error_notifier(ch, - NVHOST_CHANNEL_GR_SEMAPHORE_TIMEOUT); + NVGPU_CHANNEL_GR_SEMAPHORE_TIMEOUT); gk20a_err(dev_from_gk20a(g), "gr semaphore timeout\n"); return -EINVAL; @@ -4969,7 +4970,7 @@ static int gk20a_gr_intr_illegal_notify_pending(struct gk20a *g, struct channel_gk20a *ch = &f->channel[isr_data->chid]; gk20a_dbg_fn(""); gk20a_set_error_notifier(ch, - NVHOST_CHANNEL_GR_ILLEGAL_NOTIFY); + NVGPU_CHANNEL_GR_ILLEGAL_NOTIFY); /* This is an unrecoverable error, reset is needed */ gk20a_err(dev_from_gk20a(g), "gr semaphore timeout\n"); @@ -4997,7 +4998,7 @@ static int gk20a_gr_handle_illegal_class(struct gk20a *g, struct channel_gk20a *ch = &f->channel[isr_data->chid]; gk20a_dbg_fn(""); gk20a_set_error_notifier(ch, - NVHOST_CHANNEL_GR_ERROR_SW_NOTIFY); + NVGPU_CHANNEL_GR_ERROR_SW_NOTIFY); gk20a_err(dev_from_gk20a(g), "invalid class 0x%08x, offset 0x%08x", isr_data->class_num, isr_data->offset); @@ -5037,7 +5038,7 @@ static int gk20a_gr_handle_class_error(struct gk20a *g, gk20a_dbg_fn(""); gk20a_set_error_notifier(ch, - NVHOST_CHANNEL_GR_ERROR_SW_NOTIFY); + NVGPU_CHANNEL_GR_ERROR_SW_NOTIFY); gk20a_err(dev_from_gk20a(g), "class error 0x%08x, offset 0x%08x, unhandled intr 0x%08x for channel %u\n", isr_data->class_num, isr_data->offset, @@ -5054,7 +5055,7 @@ static int gk20a_gr_handle_firmware_method(struct gk20a *g, gk20a_dbg_fn(""); gk20a_set_error_notifier(ch, - NVHOST_CHANNEL_GR_ERROR_SW_NOTIFY); + NVGPU_CHANNEL_GR_ERROR_SW_NOTIFY); gk20a_err(dev_from_gk20a(g), "firmware method 0x%08x, offset 0x%08x for channel %u\n", isr_data->class_num, isr_data->offset, @@ -5674,7 +5675,7 @@ int gk20a_gr_isr(struct gk20a *g) if (need_reset) gk20a_set_error_notifier(ch, - NVHOST_CHANNEL_GR_ERROR_SW_NOTIFY); + NVGPU_CHANNEL_GR_ERROR_SW_NOTIFY); } gk20a_writel(g, gr_intr_r(), gr_intr_exception_reset_f()); @@ -6774,7 +6775,7 @@ static int gr_gk20a_find_priv_offset_in_buffer(struct gk20a *g, int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, - struct nvhost_dbg_gpu_reg_op *ctx_ops, u32 num_ops, + struct nvgpu_dbg_gpu_reg_op *ctx_ops, u32 num_ops, u32 num_ctx_wr_ops, u32 num_ctx_rd_ops) { struct gk20a *g = ch->g; @@ -6921,7 +6922,7 @@ int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, "ctx op invalid offset: offset=0x%x", ctx_ops[i].offset); ctx_ops[i].status = - NVHOST_DBG_GPU_REG_OP_STATUS_INVALID_OFFSET; + NVGPU_DBG_GPU_REG_OP_STATUS_INVALID_OFFSET; continue; } diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index f60afd58..e9bf4505 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h @@ -15,8 +15,8 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ -#ifndef __GR_GK20A_H__ -#define __GR_GK20A_H__ +#ifndef GR_GK20A_H +#define GR_GK20A_H #include @@ -330,13 +330,13 @@ int gk20a_init_gr_channel(struct channel_gk20a *ch_gk20a); int gr_gk20a_init_ctx_vars(struct gk20a *g, struct gr_gk20a *gr); -struct nvhost_alloc_obj_ctx_args; -struct nvhost_free_obj_ctx_args; +struct nvgpu_alloc_obj_ctx_args; +struct nvgpu_free_obj_ctx_args; int gk20a_alloc_obj_ctx(struct channel_gk20a *c, - struct nvhost_alloc_obj_ctx_args *args); + struct nvgpu_alloc_obj_ctx_args *args); int gk20a_free_obj_ctx(struct channel_gk20a *c, - struct nvhost_free_obj_ctx_args *args); + struct nvgpu_free_obj_ctx_args *args); void gk20a_free_channel_ctx(struct channel_gk20a *c); int gk20a_gr_isr(struct gk20a *g); @@ -384,9 +384,9 @@ bool gk20a_gr_sm_debugger_attached(struct gk20a *g); int gk20a_gr_suspend(struct gk20a *g); -struct nvhost_dbg_gpu_reg_op; +struct nvgpu_dbg_gpu_reg_op; int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, - struct nvhost_dbg_gpu_reg_op *ctx_ops, u32 num_ops, + struct nvgpu_dbg_gpu_reg_op *ctx_ops, u32 num_ops, u32 num_ctx_wr_ops, u32 num_ctx_rd_ops); int gr_gk20a_get_ctx_buffer_offsets(struct gk20a *g, u32 addr, @@ -424,4 +424,4 @@ int gr_gk20a_load_ctxsw_ucode(struct gk20a *g); void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g); void gr_gk20a_free_tsg_gr_ctx(struct tsg_gk20a *c); -#endif /*__GR_GK20A_H__*/ +#endif /* GR_GK20A_H */ diff --git a/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h index a82a1ee7..9e1a1cb8 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h @@ -15,8 +15,8 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ -#ifndef _NVHOST_GR_PRI_GK20A_H_ -#define _NVHOST_GR_PRI_GK20A_H_ +#ifndef GR_PRI_GK20A_H +#define GR_PRI_GK20A_H /* * These convenience macros are generally for use in the management/modificaiton @@ -176,4 +176,4 @@ enum ctxsw_addr_type { #define PRI_BROADCAST_FLAGS_BE BIT(2) #define PRI_BROADCAST_FLAGS_PPC BIT(3) -#endif /*_NVHOST_GR_PRI_GK20A_H_ */ +#endif /* GR_PRI_GK20A_H */ diff --git a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.h b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.h index 208811b2..df7dc9e4 100644 --- a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.h @@ -13,8 +13,8 @@ * more details. */ -#ifndef _NVHOST_GK20A_LTC -#define _NVHOST_GK20A_LTC +#ifndef LTC_GK20A_H +#define LTC_GK20A_H struct gk20a; void gk20a_init_ltc(struct gpu_ops *gops); diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index 7660c949..37813ad3 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c @@ -1,6 +1,4 @@ /* - * drivers/video/tegra/host/gk20a/mm_gk20a.c - * * GK20A memory management * * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. @@ -14,9 +12,8 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . */ #include @@ -29,6 +26,7 @@ #include #include #include +#include #include "gk20a.h" #include "mm_gk20a.h" @@ -42,6 +40,7 @@ #include "hw_ltc_gk20a.h" #include "kind_gk20a.h" +#include "semaphore_gk20a.h" /* * GPU mapping life cycle @@ -819,7 +818,7 @@ static void gk20a_vm_unmap_user(struct vm_gk20a *vm, u64 offset) return; } - if (mapped_buffer->flags & NVHOST_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET) { + if (mapped_buffer->flags & NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET) { mutex_unlock(&vm->update_gmmu_lock); if (tegra_platform_is_silicon()) @@ -1175,7 +1174,7 @@ u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm, kind_v, ctag_offset, flags & - NVHOST_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, + NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, rw_flag); if (err) { gk20a_err(d, "failed to update ptes on map"); @@ -1256,7 +1255,7 @@ static u64 gk20a_vm_map_duplicate_locked(struct vm_gk20a *vm, if (mapped_buffer->flags != flags) return 0; - if (flags & NVHOST_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET && + if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET && mapped_buffer->addr != offset_align) return 0; @@ -1303,7 +1302,7 @@ static u64 gk20a_vm_map_duplicate_locked(struct vm_gk20a *vm, u64 gk20a_vm_map(struct vm_gk20a *vm, struct dma_buf *dmabuf, u64 offset_align, - u32 flags /*NVHOST_AS_MAP_BUFFER_FLAGS_*/, + u32 flags /*NVGPU_AS_MAP_BUFFER_FLAGS_*/, int kind, struct sg_table **sgt, bool user_mapped, @@ -1364,7 +1363,7 @@ u64 gk20a_vm_map(struct vm_gk20a *vm, /* If FIX_OFFSET is set, pgsz is determined. Otherwise, select * page size according to memory alignment */ - if (flags & NVHOST_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET) { + if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET) { bfr.pgsz_idx = NV_GMMU_VA_IS_UPPER(offset_align) ? gmmu_page_size_big : gmmu_page_size_small; } else { @@ -1390,7 +1389,7 @@ u64 gk20a_vm_map(struct vm_gk20a *vm, /* Check if we should use a fixed offset for mapping this buffer */ - if (flags & NVHOST_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET) { + if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_FIXED_OFFSET) { err = validate_fixed_buffer(vm, &bfr, offset_align, mapping_size); if (err) @@ -1996,7 +1995,7 @@ static int gk20a_vm_put_empty(struct vm_gk20a *vm, u64 vaddr, for (i = 0; i < num_pages; i++) { u64 page_vaddr = g->ops.mm.gmmu_map(vm, vaddr, vm->zero_page_sgt, 0, pgsz, pgsz_idx, 0, 0, - NVHOST_AS_ALLOC_SPACE_FLAGS_FIXED_OFFSET, + NVGPU_AS_ALLOC_SPACE_FLAGS_FIXED_OFFSET, gk20a_mem_flag_none, false); if (!page_vaddr) { @@ -2322,7 +2321,7 @@ int gk20a_vm_release_share(struct gk20a_as_share *as_share) int gk20a_vm_alloc_space(struct gk20a_as_share *as_share, - struct nvhost_as_alloc_space_args *args) + struct nvgpu_as_alloc_space_args *args) { int err = -ENOMEM; int pgsz_idx; @@ -2356,7 +2355,7 @@ int gk20a_vm_alloc_space(struct gk20a_as_share *as_share, goto clean_up; } - if (args->flags & NVHOST_AS_ALLOC_SPACE_FLAGS_SPARSE && + if (args->flags & NVGPU_AS_ALLOC_SPACE_FLAGS_SPARSE && pgsz_idx != gmmu_page_size_big) { err = -ENOSYS; kfree(va_node); @@ -2364,7 +2363,7 @@ int gk20a_vm_alloc_space(struct gk20a_as_share *as_share, } start_page_nr = 0; - if (args->flags & NVHOST_AS_ALLOC_SPACE_FLAGS_FIXED_OFFSET) + if (args->flags & NVGPU_AS_ALLOC_SPACE_FLAGS_FIXED_OFFSET) start_page_nr = (u32)(args->o_a.offset >> gmmu_page_shifts[pgsz_idx]); @@ -2386,7 +2385,7 @@ int gk20a_vm_alloc_space(struct gk20a_as_share *as_share, mutex_lock(&vm->update_gmmu_lock); /* mark that we need to use sparse mappings here */ - if (args->flags & NVHOST_AS_ALLOC_SPACE_FLAGS_SPARSE) { + if (args->flags & NVGPU_AS_ALLOC_SPACE_FLAGS_SPARSE) { err = g->ops.mm.set_sparse(vm, vaddr_start, args->pages, pgsz_idx, true); if (err) { @@ -2409,7 +2408,7 @@ clean_up: } int gk20a_vm_free_space(struct gk20a_as_share *as_share, - struct nvhost_as_free_space_args *args) + struct nvgpu_as_free_space_args *args) { int err = -ENOMEM; int pgsz_idx; @@ -2580,7 +2579,7 @@ static int gk20a_dmabuf_get_kind(struct dma_buf *dmabuf) int gk20a_vm_map_buffer(struct gk20a_as_share *as_share, int dmabuf_fd, u64 *offset_align, - u32 flags, /*NVHOST_AS_MAP_BUFFER_FLAGS_*/ + u32 flags, /*NVGPU_AS_MAP_BUFFER_FLAGS_*/ int kind, u64 buffer_offset, u64 mapping_size) @@ -3147,7 +3146,7 @@ bool gk20a_mm_mmu_debug_mode_enabled(struct gk20a *g) void gk20a_init_mm(struct gpu_ops *gops) { - /* remember to remove NVHOST_GPU_FLAGS_SUPPORT_SPARSE_ALLOCS in + /* remember to remove NVGPU_GPU_FLAGS_SUPPORT_SPARSE_ALLOCS in * characteristics flags if sparse support is removed */ gops->mm.set_sparse = gk20a_vm_put_sparse; gops->mm.put_empty = gk20a_vm_put_empty; diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h index 89a2108b..6c46e113 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h @@ -1,6 +1,4 @@ /* - * drivers/video/tegra/host/gk20a/mm_gk20a.h - * * GK20A memory management * * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. @@ -14,12 +12,11 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . */ -#ifndef __MM_GK20A_H__ -#define __MM_GK20A_H__ +#ifndef MM_GK20A_H +#define MM_GK20A_H #include #include @@ -210,14 +207,6 @@ struct page_table_gk20a { size_t size; }; -#ifndef _NVHOST_MEM_MGR_H -enum gk20a_mem_rw_flag { - gk20a_mem_flag_none = 0, - gk20a_mem_flag_read_only = 1, - gk20a_mem_flag_write_only = 2, -}; -#endif - enum gmmu_pgsz_gk20a { gmmu_page_size_small = 0, gmmu_page_size_big = 1, @@ -476,7 +465,7 @@ void gk20a_mm_unpin(struct device *dev, struct dma_buf *dmabuf, u64 gk20a_vm_map(struct vm_gk20a *vm, struct dma_buf *dmabuf, u64 offset_align, - u32 flags /*NVHOST_AS_MAP_BUFFER_FLAGS_*/, + u32 flags /*NVGPU_AS_MAP_BUFFER_FLAGS_*/, int kind, struct sg_table **sgt, bool user_mapped, @@ -521,20 +510,20 @@ int gk20a_vm_free_va(struct vm_gk20a *vm, enum gmmu_pgsz_gk20a pgsz_idx); /* vm-as interface */ -struct nvhost_as_alloc_space_args; -struct nvhost_as_free_space_args; +struct nvgpu_as_alloc_space_args; +struct nvgpu_as_free_space_args; int gk20a_vm_alloc_share(struct gk20a_as_share *as_share); int gk20a_vm_release_share(struct gk20a_as_share *as_share); int gk20a_vm_alloc_space(struct gk20a_as_share *as_share, - struct nvhost_as_alloc_space_args *args); + struct nvgpu_as_alloc_space_args *args); int gk20a_vm_free_space(struct gk20a_as_share *as_share, - struct nvhost_as_free_space_args *args); + struct nvgpu_as_free_space_args *args); int gk20a_vm_bind_channel(struct gk20a_as_share *as_share, struct channel_gk20a *ch); int gk20a_vm_map_buffer(struct gk20a_as_share *as_share, int dmabuf_fd, u64 *offset_align, - u32 flags, /*NVHOST_AS_MAP_BUFFER_FLAGS_*/ + u32 flags, /* NVGPU_AS_MAP_BUFFER_FLAGS_ */ int kind, u64 buffer_offset, u64 mapping_size); @@ -570,4 +559,4 @@ void update_gmmu_pde_locked(struct vm_gk20a *vm, u32 i); struct gpu_ops; void gk20a_init_mm(struct gpu_ops *gops); -#endif /*_MM_GK20A_H_ */ +#endif /* MM_GK20A_H */ diff --git a/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c b/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c index bbbbccb4..d8a30d9a 100644 --- a/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c +++ b/drivers/gpu/nvgpu/gk20a/platform_gk20a_tegra.c @@ -16,6 +16,7 @@ */ #include +#include #include #include #include diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index f0ce3c9a..eb79fe17 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c @@ -1,6 +1,4 @@ /* - * drivers/video/tegra/host/gk20a/pmu_gk20a.c - * * GK20A PMU (aka. gPMU outside gk20a context) * * Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved. @@ -14,9 +12,8 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . */ #include /* for mdelay */ @@ -29,6 +26,7 @@ #include "gk20a.h" #include "gr_gk20a.h" +#include "semaphore_gk20a.h" #include "hw_mc_gk20a.h" #include "hw_pwr_gk20a.h" #include "hw_top_gk20a.h" diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c index 628b12ef..0e1081b9 100644 --- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c @@ -1,5 +1,4 @@ /* - * * Tegra GK20A GPU Debugger Driver Register Ops * * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. @@ -372,12 +371,12 @@ static const u32 gk20a_qctl_whitelist_ranges_count = static bool validate_reg_ops(struct dbg_session_gk20a *dbg_s, u32 *ctx_rd_count, u32 *ctx_wr_count, - struct nvhost_dbg_gpu_reg_op *ops, + struct nvgpu_dbg_gpu_reg_op *ops, u32 op_count); int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s, - struct nvhost_dbg_gpu_reg_op *ops, + struct nvgpu_dbg_gpu_reg_op *ops, u64 num_ops) { int err = 0, i; @@ -502,7 +501,7 @@ int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s, static int validate_reg_op_info(struct dbg_session_gk20a *dbg_s, - struct nvhost_dbg_gpu_reg_op *op) + struct nvgpu_dbg_gpu_reg_op *op) { int err = 0; @@ -531,7 +530,7 @@ static int validate_reg_op_info(struct dbg_session_gk20a *dbg_s, case REGOP(TYPE_GR_CTX_QUAD): break; /* - case NVHOST_DBG_GPU_REG_OP_TYPE_FB: + case NVGPU_DBG_GPU_REG_OP_TYPE_FB: */ default: op->status |= REGOP(STATUS_INVALID_TYPE); @@ -544,7 +543,7 @@ static int validate_reg_op_info(struct dbg_session_gk20a *dbg_s, } static bool check_whitelists(struct dbg_session_gk20a *dbg_s, - struct nvhost_dbg_gpu_reg_op *op, u32 offset) + struct nvgpu_dbg_gpu_reg_op *op, u32 offset) { struct gk20a *g = dbg_s->g; bool valid = false; @@ -606,7 +605,7 @@ static bool check_whitelists(struct dbg_session_gk20a *dbg_s, /* note: the op here has already been through validate_reg_op_info */ static int validate_reg_op_offset(struct dbg_session_gk20a *dbg_s, - struct nvhost_dbg_gpu_reg_op *op) + struct nvgpu_dbg_gpu_reg_op *op) { int err; u32 buf_offset_lo, buf_offset_addr, num_offsets, offset; @@ -656,7 +655,7 @@ static int validate_reg_op_offset(struct dbg_session_gk20a *dbg_s, static bool validate_reg_ops(struct dbg_session_gk20a *dbg_s, u32 *ctx_rd_count, u32 *ctx_wr_count, - struct nvhost_dbg_gpu_reg_op *ops, + struct nvgpu_dbg_gpu_reg_op *ops, u32 op_count) { u32 i; diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.h b/drivers/gpu/nvgpu/gk20a/regops_gk20a.h index 808e8bbe..0c244f58 100644 --- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.h @@ -1,5 +1,4 @@ /* - * * Tegra GK20A GPU Debugger Driver Register Ops * * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. @@ -16,8 +15,8 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ -#ifndef __REGOPS_GK20A_H_ -#define __REGOPS_GK20A_H_ +#ifndef REGOPS_GK20A_H +#define REGOPS_GK20A_H #include @@ -27,11 +26,11 @@ struct regop_offset_range { }; int exec_regops_gk20a(struct dbg_session_gk20a *dbg_s, - struct nvhost_dbg_gpu_reg_op *ops, + struct nvgpu_dbg_gpu_reg_op *ops, u64 num_ops); /* turn seriously unwieldy names -> something shorter */ -#define REGOP(x) NVHOST_DBG_GPU_REG_OP_##x +#define REGOP(x) NVGPU_DBG_GPU_REG_OP_##x static inline bool reg_op_is_gr_ctx(u8 type) { @@ -51,4 +50,4 @@ static inline bool reg_op_is_read(u8 op) bool is_bar0_global_offset_whitelisted_gk20a(struct gk20a *g, u32 offset); void gk20a_init_regops(struct gpu_ops *gops); -#endif /* __REGOPS_GK20A_H_ */ +#endif /* REGOPS_GK20A_H */ diff --git a/drivers/gpu/nvgpu/gk20a/semaphore_gk20a.h b/drivers/gpu/nvgpu/gk20a/semaphore_gk20a.h index 214db398..6ffe1fd2 100644 --- a/drivers/gpu/nvgpu/gk20a/semaphore_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/semaphore_gk20a.h @@ -1,8 +1,4 @@ /* - * drivers/video/tegra/host/gk20a/semaphore_gk20a.h - * - * GK20A Semaphores - * * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it @@ -15,8 +11,8 @@ * more details. */ -#ifndef _GK20A_SEMAPHORE_H_ -#define _GK20A_SEMAPHORE_H_ +#ifndef SEMAPHORE_GK20A_H +#define SEMAPHORE_GK20A_H #include #include "gk20a_allocator.h" @@ -35,6 +31,12 @@ struct gk20a_semaphore_pool { struct gk20a_allocator alloc; }; +enum gk20a_mem_rw_flag { + gk20a_mem_flag_none = 0, + gk20a_mem_flag_read_only = 1, + gk20a_mem_flag_write_only = 2, +}; + /* A semaphore pool can be mapped to multiple GPU address spaces. */ struct gk20a_semaphore_pool_map { u64 gpu_va; diff --git a/drivers/gpu/nvgpu/gk20a/sync_gk20a.c b/drivers/gpu/nvgpu/gk20a/sync_gk20a.c index da9a0f5e..abbf6aa8 100644 --- a/drivers/gpu/nvgpu/gk20a/sync_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/sync_gk20a.c @@ -1,6 +1,4 @@ /* - * drivers/video/tegra/host/gk20a/sync_gk20a.h - * * GK20A Sync Framework Integration * * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. diff --git a/drivers/gpu/nvgpu/gk20a/therm_gk20a.h b/drivers/gpu/nvgpu/gk20a/therm_gk20a.h index 3f67ee12..e670ec0e 100644 --- a/drivers/gpu/nvgpu/gk20a/therm_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/therm_gk20a.h @@ -1,9 +1,5 @@ /* - * drivers/video/tegra/host/gk20a/therm_gk20a.h - * - * GK20A Therm - * - * Copyright (c) 2011 - 2012, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011 - 2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -14,12 +10,11 @@ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . */ -#ifndef _NVHOST_THERM_GK20A_H_ -#define _NVHOST_THERM_GK20A_H_ +#ifndef THERM_GK20A_H +#define THERM_GK20A_H /* priority for EXT_THERM_0 event set to highest */ #define NV_THERM_EVT_EXT_THERM_0_INIT 0x3000100 @@ -30,4 +25,4 @@ int gk20a_init_therm_support(struct gk20a *g); -#endif /* _NVHOST_THERM_GK20A_H_ */ +#endif /* THERM_GK20A_H */ diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index 7e70d5a4..73c690fd 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c @@ -1,8 +1,6 @@ /* - * GM20B ACR - * * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. -* + * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. @@ -24,6 +22,7 @@ #include "gk20a/gk20a.h" #include "gk20a/pmu_gk20a.h" +#include "gk20a/semaphore_gk20a.h" #include "hw_pwr_gm20b.h" #include "mc_carveout_reg.h" diff --git a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c index e0f1fc0b..6c77f8d2 100644 --- a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c @@ -1,5 +1,4 @@ /* - * * Tegra GK20A GPU Debugger Driver Register Ops * * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved. -- cgit v1.2.2