From 6f5bdfd0916b139389e5dcccb1783b5da1c79953 Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Fri, 27 May 2016 09:25:04 -0700 Subject: gpu: nvgpu: fix timeout on FECS trace flush When resetting GR engine flush FECS trace before halting the pipeline. Otherwise FECS remains in sideband method processing loop, and we get a timeout on FECS trace flush Bug 200193891 Change-Id: I137ea20eb1fb4ef6d618cd01cd3c096471eb8fb0 Signed-off-by: Thomas Fleury Reviewed-on: http://git-master/r/1155240 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 2f7cb888..f8382afe 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -834,14 +834,14 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id) if (engine_id == ENGINE_GR_GK20A) { if (support_gk20a_pmu(g->dev) && g->elpg_enabled) gk20a_pmu_disable_elpg(g); - /*HALT_PIPELINE method, halt GR engine*/ - if (gr_gk20a_halt_pipe(g)) - gk20a_err(dev_from_gk20a(g), "failed to HALT gr pipe"); /* resetting engine will alter read/write index. * need to flush circular buffer before re-enabling FECS. */ if (g->ops.fecs_trace.reset) g->ops.fecs_trace.reset(g); + /*HALT_PIPELINE method, halt GR engine*/ + if (gr_gk20a_halt_pipe(g)) + gk20a_err(dev_from_gk20a(g), "failed to HALT gr pipe"); /* resetting engine using mc_enable_r() is not enough, we do full init sequence */ gk20a_gr_reset(g); -- cgit v1.2.2