From 6675c03603669c667c6ffec34567eaf101a2d09d Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 5 Apr 2016 15:03:20 -0700 Subject: gpu: nvgpu: Sync with register generator Use re-generated register definitions. This synchronizes kernel with the register generator. Change-Id: I85a00f8f5c7bdfbc56cf4df909e5ae892d86f062 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1120812 --- drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | 20 ++++++---- drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h | 2 +- drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | 53 +++++++++++---------------- 3 files changed, 35 insertions(+), 40 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h index b9d083e3..a3ae664f 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h @@ -918,6 +918,10 @@ static inline u32 gr_fecs_host_int_status_r(void) { return 0x00409c18; } +static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) +{ + return (v & 0x1) << 16; +} static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) { return (v & 0x1) << 17; @@ -3114,6 +3118,14 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void) { return 0x0; } +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void) +{ + return 0x00000000; +} static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) { return 0x00504614; @@ -3130,14 +3142,6 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) { return 0x00419e24; } -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_warp_disable_v(void) -{ - return 0x00000000; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_sm_disable_v(void) -{ - return 0x00000000; -} static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) { return 0x0050460c; diff --git a/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h index d01667bc..a44eac16 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h index 6357b372..abe1d6a6 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h @@ -930,6 +930,10 @@ static inline u32 gr_fecs_host_int_status_r(void) { return 0x00409c18; } +static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v) +{ + return (v & 0x1) << 16; +} static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) { return (v & 0x1) << 17; @@ -3146,41 +3150,41 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void) { return 0x0; } -static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_0_r(void) +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void) { - return 0x00504614; + return 0x00000000; } -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_0_r(void) +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void) { - return 0x00504624; + return 0x00000000; } -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_0_r(void) +static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) { - return 0x00504634; + return 0x00504614; } -static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) +static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_2_r(void) { - return 0x00419e24; + return 0x0050461c; } -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_warp_disable_v(void) +static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) { - return 0x00000000; + return 0x00504624; } -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_sm_disable_v(void) +static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_2_r(void) { - return 0x00000000; + return 0x00504750; } -static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_2_r(void) +static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) { - return 0x0050461c; + return 0x00504634; } -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_2_r(void) +static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_2_r(void) { - return 0x00504750; + return 0x00504758; } -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_2_r(void) +static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) { - return 0x00504758; + return 0x00419e24; } static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) { @@ -3566,7 +3570,6 @@ static inline u32 gr_gpcs_pri_mmu_ctrl_use_full_comp_tag_line_m(void) { return 0x1 << 12; } - static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) { return 0x1 << 1; @@ -3671,18 +3674,6 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) { return 0x0; } -static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) -{ - return 0x00504614; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) -{ - return 0x00504624; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) -{ - return 0x00504634; -} static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) { return 0x1 << 30; -- cgit v1.2.2