From 27908cf4a980cb56daa530641cf1817d4e3f9faa Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Fri, 23 Mar 2018 14:45:25 -0700 Subject: gpu: nvgpu: gv100: handle_tpc_sm_ecc_exception set to NULL This is to fix *SM_ICACHE_ECC* priv errors for sm suspend resume test. gv100 has significantly less ECC protected SRAMs. gv11b ECC hals will not work for gv100. Bug 1998067 Change-Id: I437a7981ed1832c2070185f3ad8f802c7454e8c9 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1681270 Reviewed-by: svc-mobile-coverity Reviewed-by: Sandarbh Jain Tested-by: Sandarbh Jain Reviewed-by: Deepak Nibade GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index cfac8e0e..cb7bca3f 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -421,8 +421,6 @@ static const struct gpu_ops gv100_ops = { .add_zbc_s = gr_gv11b_add_zbc_stencil, .handle_gcc_exception = gr_gv11b_handle_gcc_exception, .init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle, - .handle_tpc_sm_ecc_exception = - gr_gv11b_handle_tpc_sm_ecc_exception, .decode_egpc_addr = gv11b_gr_decode_egpc_addr, .fecs_host_int_enable = gr_gv11b_fecs_host_int_enable, .handle_ssync_hww = gr_gv11b_handle_ssync_hww, -- cgit v1.2.2