From 27694ca572c4d7698b107c6713f0f0604b41c186 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 25 May 2018 10:27:10 -0700 Subject: gpu: nvgpu: Implement bus HAL for bar2 bind Implement BAR2 bind as a bus HAL and remove the corresponding MM HAL. BAR2 bind HW API is in bus. JIRA NVGPU-588 Change-Id: I3a8391b00f1ba65f9ed28b633f1d52bf7c984230 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1730896 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/common/bus/bus_gp10b.c | 64 +++++++++++++++++++++++++++ drivers/gpu/nvgpu/common/bus/bus_gp10b.h | 33 ++++++++++++++ drivers/gpu/nvgpu/gk20a/gk20a.h | 2 +- drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 5 +-- drivers/gpu/nvgpu/gp106/hal_gp106.c | 3 +- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 3 +- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 28 +----------- drivers/gpu/nvgpu/gp10b/mm_gp10b.h | 1 - drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c | 1 - drivers/gpu/nvgpu/gv100/hal_gv100.c | 3 +- drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 2 +- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 +- drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 54 +--------------------- drivers/gpu/nvgpu/gv11b/mm_gv11b.h | 1 - drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 4 +- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 2 +- 17 files changed, 116 insertions(+), 94 deletions(-) create mode 100644 drivers/gpu/nvgpu/common/bus/bus_gp10b.c create mode 100644 drivers/gpu/nvgpu/common/bus/bus_gp10b.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 67a9c7f1..3cbe5b96 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_GK20A) := nvgpu.o nvgpu-y += common/bus/bus_gk20a.o \ common/bus/bus_gm20b.o \ + common/bus/bus_gp10b.o \ common/ptimer/ptimer.o \ common/ptimer/ptimer_gk20a.o diff --git a/drivers/gpu/nvgpu/common/bus/bus_gp10b.c b/drivers/gpu/nvgpu/common/bus/bus_gp10b.c new file mode 100644 index 00000000..01e81069 --- /dev/null +++ b/drivers/gpu/nvgpu/common/bus/bus_gp10b.c @@ -0,0 +1,64 @@ +/* + * GM20B MMU + * + * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +#include "bus_gp10b.h" +#include "gk20a/gk20a.h" + +#include + +int gp10b_bus_bar2_bind(struct gk20a *g, struct nvgpu_mem *bar2_inst) +{ + struct nvgpu_timeout timeout; + int err = 0; + u64 iova = nvgpu_inst_block_addr(g, bar2_inst); + u32 ptr_v = (u32)(iova >> bus_bar2_block_ptr_shift_v()); + + nvgpu_log_info(g, "bar2 inst block ptr: 0x%08x", ptr_v); + + gk20a_writel(g, bus_bar2_block_r(), + nvgpu_aperture_mask(g, bar2_inst, + bus_bar2_block_target_sys_mem_ncoh_f(), + bus_bar2_block_target_sys_mem_coh_f(), + bus_bar2_block_target_vid_mem_f()) | + bus_bar2_block_mode_virtual_f() | + bus_bar2_block_ptr_f(ptr_v)); + nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER); + do { + u32 val = gk20a_readl(g, bus_bind_status_r()); + u32 pending = bus_bind_status_bar2_pending_v(val); + u32 outstanding = bus_bind_status_bar2_outstanding_v(val); + if (!pending && !outstanding) + break; + + nvgpu_udelay(5); + } while (!nvgpu_timeout_expired(&timeout)); + + if (nvgpu_timeout_peek_expired(&timeout)) + err = -EINVAL; + + return err; +} diff --git a/drivers/gpu/nvgpu/common/bus/bus_gp10b.h b/drivers/gpu/nvgpu/common/bus/bus_gp10b.h new file mode 100644 index 00000000..0a356f15 --- /dev/null +++ b/drivers/gpu/nvgpu/common/bus/bus_gp10b.h @@ -0,0 +1,33 @@ +/* + * GM20B BUS + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _NVGPU_GP10B_BUS +#define _NVGPU_GP10B_BUS + +struct gk20a; +struct nvgpu_mem; + +int gp10b_bus_bar2_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst); + +#endif diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 08a1fc10..d8941cdf 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -895,7 +895,6 @@ struct gpu_ops { int (*init_mm_setup_hw)(struct gk20a *g); bool (*is_bar1_supported)(struct gk20a *g); int (*init_bar2_vm)(struct gk20a *g); - int (*init_bar2_mm_hw_setup)(struct gk20a *g); void (*remove_bar2_vm)(struct gk20a *g); const struct gk20a_mmu_level * (*get_mmu_levels)(struct gk20a *g, u32 big_page_size); @@ -1121,6 +1120,7 @@ struct gpu_ops { void (*init_hw)(struct gk20a *g); void (*isr)(struct gk20a *g); int (*bar1_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst); + int (*bar2_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst); u32 (*set_bar0_window)(struct gk20a *g, struct nvgpu_mem *mem, struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl, u32 w); diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index 9429fe2e..40d9e5b1 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c @@ -50,7 +50,6 @@ #include #include #include -#include #include #include @@ -103,8 +102,8 @@ int gk20a_init_mm_setup_hw(struct gk20a *g) if (g->ops.bus.bar1_bind) g->ops.bus.bar1_bind(g, &mm->bar1.inst_block); - if (g->ops.mm.init_bar2_mm_hw_setup) { - err = g->ops.mm.init_bar2_mm_hw_setup(g); + if (g->ops.bus.bar2_bind) { + err = g->ops.bus.bar2_bind(g, &mm->bar2.inst_block); if (err) return err; } diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index eec0f917..f35abac7 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -26,6 +26,7 @@ #include "common/clock_gating/gp106_gating_reglist.h" #include "common/ptimer/ptimer_gk20a.h" #include "common/bus/bus_gm20b.h" +#include "common/bus/bus_gp10b.h" #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" @@ -583,7 +584,6 @@ static const struct gpu_ops gp106_ops = { .init_inst_block = gk20a_init_inst_block, .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, .init_bar2_vm = gp10b_init_bar2_vm, - .init_bar2_mm_hw_setup = gp10b_init_bar2_mm_hw_setup, .remove_bar2_vm = gp10b_remove_bar2_vm, .get_vidmem_size = gp106_mm_get_vidmem_size, .get_kind_invalid = gm20b_get_kind_invalid, @@ -723,6 +723,7 @@ static const struct gpu_ops gp106_ops = { .init_hw = gk20a_bus_init_hw, .isr = gk20a_bus_isr, .bar1_bind = gm20b_bus_bar1_bind, + .bar2_bind = gp10b_bus_bar2_bind, .set_bar0_window = gk20a_bus_set_bar0_window, }, .ptimer = { diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 934ddb9a..8cd2a582 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -26,6 +26,7 @@ #include "common/clock_gating/gp10b_gating_reglist.h" #include "common/ptimer/ptimer_gk20a.h" #include "common/bus/bus_gm20b.h" +#include "common/bus/bus_gp10b.h" #include "gk20a/gk20a.h" #include "gk20a/fifo_gk20a.h" @@ -554,7 +555,6 @@ static const struct gpu_ops gp10b_ops = { .init_inst_block = gk20a_init_inst_block, .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, .init_bar2_vm = gp10b_init_bar2_vm, - .init_bar2_mm_hw_setup = gp10b_init_bar2_mm_hw_setup, .remove_bar2_vm = gp10b_remove_bar2_vm, .get_kind_invalid = gm20b_get_kind_invalid, .get_kind_pitch = gm20b_get_kind_pitch, @@ -653,6 +653,7 @@ static const struct gpu_ops gp10b_ops = { .init_hw = gk20a_bus_init_hw, .isr = gk20a_bus_isr, .bar1_bind = gm20b_bus_bar1_bind, + .bar2_bind = gp10b_bus_bar2_bind, .set_bar0_window = gk20a_bus_set_bar0_window, }, .ptimer = { diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index acd42dd8..50c96f36 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -34,7 +34,6 @@ #include #include -#include #include u32 gp10b_mm_get_default_big_page_size(void) @@ -62,8 +61,8 @@ int gp10b_init_mm_setup_hw(struct gk20a *g) g->ops.bus.bar1_bind(g, inst_block); - if (g->ops.mm.init_bar2_mm_hw_setup) { - err = g->ops.mm.init_bar2_mm_hw_setup(g); + if (g->ops.bus.bar2_bind) { + err = g->ops.bus.bar2_bind(g, &g->mm.bar2.inst_block); if (err) return err; } @@ -109,29 +108,6 @@ clean_up_va: return err; } -int gp10b_init_bar2_mm_hw_setup(struct gk20a *g) -{ - struct mm_gk20a *mm = &g->mm; - struct nvgpu_mem *inst_block = &mm->bar2.inst_block; - u64 inst_pa = nvgpu_inst_block_addr(g, inst_block); - - nvgpu_log_fn(g, " "); - - inst_pa = (u32)(inst_pa >> bus_bar2_block_ptr_shift_v()); - nvgpu_log_info(g, "bar2 inst block ptr: 0x%08x", (u32)inst_pa); - - gk20a_writel(g, bus_bar2_block_r(), - nvgpu_aperture_mask(g, inst_block, - bus_bar2_block_target_sys_mem_ncoh_f(), - bus_bar2_block_target_sys_mem_coh_f(), - bus_bar2_block_target_vid_mem_f()) | - bus_bar2_block_mode_virtual_f() | - bus_bar2_block_ptr_f(inst_pa)); - - nvgpu_log_fn(g, "done"); - return 0; -} - static void update_gmmu_pde3_locked(struct vm_gk20a *vm, const struct gk20a_mmu_level *l, struct nvgpu_gmmu_pd *pd, diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h index 5522d02e..4f37aae6 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h @@ -32,7 +32,6 @@ u32 gp10b_mm_get_default_big_page_size(void); u32 gp10b_mm_get_iommu_bit(struct gk20a *g); int gp10b_init_mm_setup_hw(struct gk20a *g); int gp10b_init_bar2_vm(struct gk20a *g); -int gp10b_init_bar2_mm_hw_setup(struct gk20a *g); const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g, u32 big_page_size); void gp10b_mm_init_pdb(struct gk20a *g, struct nvgpu_mem *inst_block, diff --git a/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c b/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c index 3f089545..7a714441 100644 --- a/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c @@ -30,7 +30,6 @@ #include #include -#include #include int gp10b_replayable_pagefault_buffer_init(struct gk20a *g) diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index dd3a5398..13e0c1a3 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -23,6 +23,7 @@ */ #include "common/bus/bus_gk20a.h" +#include "common/bus/bus_gp10b.h" #include "common/clock_gating/gv100_gating_reglist.h" #include "common/ptimer/ptimer_gk20a.h" @@ -653,7 +654,6 @@ static const struct gpu_ops gv100_ops = { .get_kind_invalid = gm20b_get_kind_invalid, .get_kind_pitch = gm20b_get_kind_pitch, .init_bar2_vm = gp10b_init_bar2_vm, - .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, .remove_bar2_vm = gv11b_mm_remove_bar2_vm, .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, .get_flush_retries = gv100_mm_get_flush_retries, @@ -792,6 +792,7 @@ static const struct gpu_ops gv100_ops = { .init_hw = gk20a_bus_init_hw, .isr = gk20a_bus_isr, .bar1_bind = NULL, + .bar2_bind = gp10b_bus_bar2_bind, .set_bar0_window = gk20a_bus_set_bar0_window, }, .ptimer = { diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index bba47471..9fd6c857 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c @@ -1229,7 +1229,7 @@ static void gv11b_fb_handle_bar2_fault(struct gk20a *g, } gv11b_ce_mthd_buffer_fault_in_bar2_fault(g); - g->ops.mm.init_bar2_mm_hw_setup(g); + g->ops.bus.bar2_bind(g, &g->mm.bar2.inst_block); if (mmfault->refch) { gk20a_channel_put(mmfault->refch); diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 7b552723..58912a30 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -23,6 +23,7 @@ */ #include "common/bus/bus_gk20a.h" +#include "common/bus/bus_gp10b.h" #include "common/clock_gating/gv11b_gating_reglist.h" #include "common/ptimer/ptimer_gk20a.h" @@ -621,7 +622,6 @@ static const struct gpu_ops gv11b_ops = { .get_kind_invalid = gm20b_get_kind_invalid, .get_kind_pitch = gm20b_get_kind_pitch, .init_bar2_vm = gp10b_init_bar2_vm, - .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, .remove_bar2_vm = gv11b_mm_remove_bar2_vm, .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, }, @@ -724,6 +724,7 @@ static const struct gpu_ops gv11b_ops = { .init_hw = gk20a_bus_init_hw, .isr = gk20a_bus_isr, .bar1_bind = NULL, + .bar2_bind = gp10b_bus_bar2_bind, .set_bar0_window = gk20a_bus_set_bar0_window, }, .ptimer = { diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 357b15d7..6c38365c 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c @@ -40,7 +40,6 @@ #include #include -#include #define NVGPU_L3_ALLOC_BIT BIT(36) @@ -236,7 +235,7 @@ int gv11b_init_mm_setup_hw(struct gk20a *g) g->ops.fb.set_mmu_page_size(g); g->ops.fb.init_hw(g); - err = g->ops.mm.init_bar2_mm_hw_setup(g); + err = g->ops.bus.bar2_bind(g, &g->mm.bar2.inst_block); if (err) return err; @@ -274,54 +273,3 @@ u64 gv11b_gpu_phys_addr(struct gk20a *g, return phys; } - -int gv11b_init_bar2_mm_hw_setup(struct gk20a *g) -{ - struct mm_gk20a *mm = &g->mm; - struct nvgpu_mem *inst_block = &mm->bar2.inst_block; - u64 inst_pa = nvgpu_inst_block_addr(g, inst_block); - u32 reg_val; - struct nvgpu_timeout timeout; - u32 delay = GR_IDLE_CHECK_DEFAULT; - - nvgpu_log_fn(g, " "); - - g->ops.fb.set_mmu_page_size(g); - - inst_pa = (u32)(inst_pa >> bus_bar2_block_ptr_shift_v()); - nvgpu_log_info(g, "bar2 inst block ptr: 0x%08x", (u32)inst_pa); - - gk20a_writel(g, bus_bar2_block_r(), - nvgpu_aperture_mask(g, inst_block, - bus_bar2_block_target_sys_mem_ncoh_f(), - bus_bar2_block_target_sys_mem_coh_f(), - bus_bar2_block_target_vid_mem_f()) | - bus_bar2_block_mode_virtual_f() | - bus_bar2_block_ptr_f(inst_pa)); - - /* This is needed as BAR1 support is removed and there is no way - * to know if gpu successfully accessed memory. - * To avoid deadlocks and non-deterministic virtual address translation - * behavior, after writing BAR2_BLOCK to bind BAR2 to a virtual address - * space, SW must ensure that the bind has completed prior to issuing - * any further BAR2 requests by polling for both - * BUS_BIND_STATUS_BAR2_PENDING to return to EMPTY and - * BUS_BIND_STATUS_BAR2_OUTSTANDING to return to FALSE - */ - nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), - NVGPU_TIMER_CPU_TIMER); - nvgpu_log_info(g, "check bar2 bind status"); - do { - reg_val = gk20a_readl(g, bus_bind_status_r()); - - if (!((reg_val & bus_bind_status_bar2_pending_busy_f()) || - (reg_val & bus_bind_status_bar2_outstanding_true_f()))) - return 0; - - nvgpu_usleep_range(delay, delay * 2); - delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); - } while (!nvgpu_timeout_expired_msg(&timeout, "bar2 bind timedout")); - - nvgpu_err(g, "bar2 bind failed. gpu unable to access memory"); - return -EBUSY; -} diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.h b/drivers/gpu/nvgpu/gv11b/mm_gv11b.h index 2b3ebf4e..f5f89d94 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.h @@ -34,7 +34,6 @@ void gv11b_init_inst_block(struct nvgpu_mem *inst_block, bool gv11b_mm_mmu_fault_pending(struct gk20a *g); void gv11b_mm_remove_bar2_vm(struct gk20a *g); int gv11b_init_mm_setup_hw(struct gk20a *g); -int gv11b_init_bar2_mm_hw_setup(struct gk20a *g); void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate); u64 gv11b_gpu_phys_addr(struct gk20a *g, struct nvgpu_gmmu_attrs *attrs, u64 phys); diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index c4ffe126..8c2b613f 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c @@ -427,7 +427,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { .init_inst_block = gk20a_init_inst_block, .mmu_fault_pending = gk20a_fifo_mmu_fault_pending, .init_bar2_vm = gp10b_init_bar2_vm, - .init_bar2_mm_hw_setup = gp10b_init_bar2_mm_hw_setup, .remove_bar2_vm = gp10b_remove_bar2_vm, .get_kind_invalid = gm20b_get_kind_invalid, .get_kind_pitch = gm20b_get_kind_pitch, @@ -524,7 +523,8 @@ static const struct gpu_ops vgpu_gp10b_ops = { .bus = { .init_hw = gk20a_bus_init_hw, .isr = gk20a_bus_isr, - .bar1_bind = gm20b_bus_bar1_bind, + .bar1_bind = NULL, + .bar2_bind = NULL, .set_bar0_window = gk20a_bus_set_bar0_window, }, .ptimer = { diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index d6b305d4..450c9c87 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -476,7 +476,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { .get_kind_invalid = gm20b_get_kind_invalid, .get_kind_pitch = gm20b_get_kind_pitch, .init_bar2_vm = gp10b_init_bar2_vm, - .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, .remove_bar2_vm = gv11b_mm_remove_bar2_vm, .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, }, @@ -575,6 +574,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .init_hw = gk20a_bus_init_hw, .isr = gk20a_bus_isr, .bar1_bind = NULL, + .bar2_bind = NULL, .set_bar0_window = gk20a_bus_set_bar0_window, }, .ptimer = { -- cgit v1.2.2