From 02d0e8d57449ed6a2c60dd2ec9450aafe3b8bc7a Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Fri, 29 Aug 2014 18:19:54 -0700 Subject: gpu: nvgpu: Add GM20b pll registers error dump Change-Id: I67fe2c4cbab1d43670131d95bbea732e932c0910 Signed-off-by: Alex Frid Reviewed-on: http://git-master/r/494164 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy --- drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index c7c2e8af..71e21d58 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c @@ -46,6 +46,26 @@ static struct pll_parms gpc_pll_params = { static int clk_gm20b_debugfs_init(struct gk20a *g); #endif +#define DUMP_REG(addr_func) \ +do { \ + addr = trim_sys_##addr_func##_r(); \ + data = gk20a_readl(g, addr); \ + pr_info(#addr_func "[0x%x] = 0x%x\n", addr, data); \ +} while (0) + +static void dump_gpc_pll(struct gk20a *g, struct pll *gpll, u32 last_cfg) +{ + u32 addr, data; + + pr_info("**** GPCPLL DUMP ****"); + pr_info("gpcpll s/w M=%u N=%u P=%u\n", gpll->M, gpll->N, gpll->PL); + pr_info("gpcpll_cfg_last = 0x%x\n", last_cfg); + DUMP_REG(gpcpll_cfg); + DUMP_REG(gpcpll_coeff); + DUMP_REG(sel_vco); + pr_info("\n"); +} + /* 1:1 match between post divider settings and divisor value */ static inline u32 pl_to_div(u32 pl) { @@ -344,6 +364,7 @@ static int clk_lock_gpc_pll_under_bypass(struct gk20a *g, struct pll *gpll) } while (--timeout > 0); /* PLL is messed up. What can we do here? */ + dump_gpc_pll(g, gpll, cfg); BUG(); return -EBUSY; -- cgit v1.2.2