From f30a685f48768b784fb92652d945f43a289e13c4 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Fri, 21 Apr 2017 16:49:12 +0530 Subject: gpu: nvgpu: interface layer for falcon - struct nvgpu_falcon to hold properties of falcon controller - falcon controller interface layer which establish access to required falcon controller HAL based on struct nvgpu_falcon member flcn_id & flcn_base parameter. - each falcon nvgpu_falcon struct initialized during init with id, base-address along with other properties at HAL. - Added defines related to flacon controller. Change-Id: Ia7777c01ecc542150ddd72f8603b7b4475522b58 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1467523 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile.nvgpu | 1 + drivers/gpu/nvgpu/common/falcon/falcon.c | 51 +++++++++ drivers/gpu/nvgpu/gk20a/gk20a.h | 8 ++ drivers/gpu/nvgpu/include/nvgpu/falcon.h | 190 +++++++++++++++++++++++++++++++ 4 files changed, 250 insertions(+) create mode 100644 drivers/gpu/nvgpu/common/falcon/falcon.c create mode 100644 drivers/gpu/nvgpu/include/nvgpu/falcon.h (limited to 'drivers/gpu/nvgpu') diff --git a/drivers/gpu/nvgpu/Makefile.nvgpu b/drivers/gpu/nvgpu/Makefile.nvgpu index 6bac840f..5400b10d 100644 --- a/drivers/gpu/nvgpu/Makefile.nvgpu +++ b/drivers/gpu/nvgpu/Makefile.nvgpu @@ -47,6 +47,7 @@ nvgpu-y := \ common/as.o \ common/rbtree.o \ common/vbios/bios.o \ + common/falcon/falcon.o \ gk20a/gk20a.o \ gk20a/bus_gk20a.o \ gk20a/pramin_gk20a.o \ diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c new file mode 100644 index 00000000..ac1b390f --- /dev/null +++ b/drivers/gpu/nvgpu/common/falcon/falcon.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#include +#include +#include + +#include "gk20a/gk20a.h" + +void nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id) +{ + struct nvgpu_falcon *flcn = NULL; + struct gpu_ops *gops = &g->ops; + + switch (flcn_id) { + case FALCON_ID_PMU: + flcn = &g->pmu_flcn; + flcn->flcn_id = flcn_id; + break; + case FALCON_ID_SEC2: + flcn = &g->sec2_flcn; + flcn->flcn_id = flcn_id; + break; + case FALCON_ID_FECS: + flcn = &g->fecs_flcn; + flcn->flcn_id = flcn_id; + break; + case FALCON_ID_GPCCS: + flcn = &g->gpccs_flcn; + flcn->flcn_id = flcn_id; + break; + default: + nvgpu_err(g, "Invalid/Unsupported falcon ID %x", flcn->flcn_id); + break; + }; + + /* call to HAL method to assign flcn base & ops to selected falcon */ + if (flcn) { + flcn->g = g; + gops->falcon.falcon_hal_sw_init(flcn); + } +} diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 71ff8d3e..74e2c688 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -46,6 +46,7 @@ struct dbg_profiler_object_data; #include #include #include +#include #include "clk_gk20a.h" #include "ce2_gk20a.h" @@ -869,6 +870,9 @@ struct gpu_ops { void (*enable_shadow_rom)(struct gk20a *g); void (*disable_shadow_rom)(struct gk20a *g); } xve; + struct { + void (*falcon_hal_sw_init)(struct nvgpu_falcon *flcn); + } falcon; }; struct nvgpu_bios_ucode { @@ -944,6 +948,10 @@ struct gk20a { struct rw_semaphore busy_lock; + struct nvgpu_falcon pmu_flcn; + struct nvgpu_falcon sec2_flcn; + struct nvgpu_falcon fecs_flcn; + struct nvgpu_falcon gpccs_flcn; struct clk_gk20a clk; struct fifo_gk20a fifo; struct gr_gk20a gr; diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h new file mode 100644 index 00000000..17b811dd --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h @@ -0,0 +1,190 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __FALCON_H__ +#define __FALCON_H__ + +/* + * Falcon Id Defines + */ +#define FALCON_ID_PMU (0) +#define FALCON_ID_FECS (2) +#define FALCON_ID_GPCCS (3) +#define FALCON_ID_SEC2 (7) + +/* + * Falcon Base address Defines + */ +#define FALCON_PWR_BASE 0x0010a000 +#define FALCON_SEC_BASE 0x00087000 +#define FALCON_FECS_BASE 0x00409000 +#define FALCON_GPCCS_BASE 0x0041a000 + +/* Falcon Register index */ +#define FALCON_REG_R0 (0) +#define FALCON_REG_R1 (1) +#define FALCON_REG_R2 (2) +#define FALCON_REG_R3 (3) +#define FALCON_REG_R4 (4) +#define FALCON_REG_R5 (5) +#define FALCON_REG_R6 (6) +#define FALCON_REG_R7 (7) +#define FALCON_REG_R8 (8) +#define FALCON_REG_R9 (9) +#define FALCON_REG_R10 (10) +#define FALCON_REG_R11 (11) +#define FALCON_REG_R12 (12) +#define FALCON_REG_R13 (13) +#define FALCON_REG_R14 (14) +#define FALCON_REG_R15 (15) +#define FALCON_REG_IV0 (16) +#define FALCON_REG_IV1 (17) +#define FALCON_REG_UNDEFINED (18) +#define FALCON_REG_EV (19) +#define FALCON_REG_SP (20) +#define FALCON_REG_PC (21) +#define FALCON_REG_IMB (22) +#define FALCON_REG_DMB (23) +#define FALCON_REG_CSW (24) +#define FALCON_REG_CCR (25) +#define FALCON_REG_SEC (26) +#define FALCON_REG_CTX (27) +#define FALCON_REG_EXCI (28) +#define FALCON_REG_RSVD0 (29) +#define FALCON_REG_RSVD1 (30) +#define FALCON_REG_RSVD2 (31) +#define FALCON_REG_SIZE (32) + +/* + * Falcon HWCFG request read types defines + */ +enum flcn_hwcfg_read { + FALCON_IMEM_SIZE = 0, + FALCON_DMEM_SIZE, + FALCON_CORE_REV, + FALCON_SECURITY_MODEL, + FLACON_MAILBOX_COUNT +}; + +/* + * Falcon HWCFG request write types defines + */ +enum flcn_hwcfg_write { + FALCON_STARTCPU = 0, + FALCON_STARTCPU_SECURE, + FALCON_BOOTVEC, + FALCON_ITF_EN +}; + +/* + * Falcon sub unit Id Defines + */ +enum flcn_unit_status { + IS_FALCON_IN_RESET = 0x0, + IS_FALCON_CPU_HALTED, + IS_FALCON_IDLE, + IS_FALCON_MEM_SURBBING_DONE +}; + +#define FALCON_MEM_SCRUBBING_TIMEOUT_MAX 1000 +#define FALCON_MEM_SCRUBBING_TIMEOUT_DEFAULT 10 + +enum flcn_dma_dir { + DMA_TO_FB = 0, + DMA_FROM_FB +}; + +enum flcn_mem_type { + MEM_DMEM = 0, + MEM_IMEM +}; + +struct nvgpu_falcon_dma_info { + u32 fb_base; + u32 fb_off; + u32 flcn_mem_off; + u32 size_in_bytes; + enum flcn_dma_dir dir; + u32 ctx_dma; + enum flcn_mem_type flcn_mem; + u32 is_wait_complete; +}; + +struct gk20a; +struct nvgpu_falcon; + +struct nvgpu_falcon_version_ops { + void (*start_cpu_secure)(struct nvgpu_falcon *flcn); + void (*write_dmatrfbase)(struct nvgpu_falcon *flcn, u32 addr); +}; + +struct nvgpu_falcon_ops { + void (*reset)(struct nvgpu_falcon *flcn, bool enable); + void (*enable_irq)(struct nvgpu_falcon *flcn, bool enable); + void (*fbif_transcfg)(struct nvgpu_falcon *flcn); + u32 (*read_hwcfg)(struct nvgpu_falcon *flcn, + enum flcn_hwcfg_read cfg_type); + void (*write_hwcfg)(struct nvgpu_falcon *flcn, + enum flcn_hwcfg_write cfg_type, u32 cfg_data); + bool (*get_unit_status)(struct nvgpu_falcon *flcn, + enum flcn_unit_status unit_id); + int (*copy_from_dmem)(struct nvgpu_falcon *flcn, u32 src, u8 *dst, + u32 size, u8 port); + int (*copy_to_dmem)(struct nvgpu_falcon *flcn, u32 dst, u8 *src, + u32 size, u8 port); + int (*copy_from_imem)(struct nvgpu_falcon *flcn, u32 src, u8 *dst, + u32 size, u8 port); + int (*copy_to_imem)(struct nvgpu_falcon *flcn, u32 dst, u8 *src, + u32 size, u8 port); + int (*dma_copy)(struct nvgpu_falcon *flcn, + struct nvgpu_falcon_dma_info *dma_info); + u32 (*mailbox_read)(struct nvgpu_falcon *flcn, u32 mailbox_index); + void (*mailbox_write)(struct nvgpu_falcon *flcn, u32 mailbox_index, + u32 data); + void (*dump_falcon_stats)(struct nvgpu_falcon *flcn); +}; + +struct nvgpu_falcon { + struct gk20a *g; + u32 flcn_id; + u32 flcn_base; + u32 flcn_core_rev; + bool isr_enabled; + struct nvgpu_mutex isr_mutex; + struct nvgpu_mutex copy_lock; + struct nvgpu_falcon_ops flcn_ops; + struct nvgpu_falcon_version_ops flcn_vops; +}; + +int nvgpu_flcn_wait_idle(struct nvgpu_falcon *flcn); +int nvgpu_flcn_enable_hw(struct nvgpu_falcon *flcn, bool enable); +int nvgpu_flcn_reset(struct nvgpu_falcon *flcn); +void nvgpu_flcn_enable_irq(struct nvgpu_falcon *flcn, bool enable); +void nvgpu_flcn_fbif_transcfg(struct nvgpu_falcon *flcn); +bool nvgpu_flcn_get_unit_status(struct nvgpu_falcon *flcn, + enum flcn_unit_status unit_id); +int nvgpu_flcn_copy_from_mem(struct nvgpu_falcon *flcn, + enum flcn_mem_type mem_type, u32 src, u8 *dst, u32 size, u8 port); +int nvgpu_flcn_copy_to_mem(struct nvgpu_falcon *flcn, + enum flcn_mem_type mem_type, u32 dst, u8 *src, u32 size, u8 port); +int nvgpu_flcn_dma_copy(struct nvgpu_falcon *flcn, + struct nvgpu_falcon_dma_info *dma_info); +u32 nvgpu_flcn_mailbox_read(struct nvgpu_falcon *flcn, u32 mailbox_index); +void nvgpu_flcn_mailbox_write(struct nvgpu_falcon *flcn, u32 mailbox_index, + u32 data); +void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn); + +void nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id); + + +#endif /* __FALCON_H__ */ -- cgit v1.2.2