From ec964208c14e29ea46ea22f44a3ae718f36e17fa Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Wed, 17 May 2017 15:03:48 +0530 Subject: gpu: nvgpu: use common fuse APIs in clk_gm20b.c Use common fuse APIs in clk_gm20b.c Include in clk_gm20b.c and remove tegra specific include Jira NVGPU-49 Jira NVGPU-75 Change-Id: I3e89ee7fc20d67fc26ee289e35a68560ff442ada Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1483861 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/nvgpu') diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index 44ac4dd0..c4e65767 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c @@ -20,13 +20,13 @@ #include #include #endif -#include #include "gk20a/gk20a.h" #include "gk20a/platform_gk20a.h" #include "clk_gm20b.h" #include +#include #include #include @@ -280,12 +280,12 @@ static inline int fuse_get_gpcpll_adc_intercept_uv(u32 val) return ((val >> 4) & 0x3ff) * 1000 + ((val >> 0) & 0xf) * 100; } -static int tegra_fuse_calib_gpcpll_get_adc(int *slope_uv, int *intercept_uv) +static int nvgpu_fuse_calib_gpcpll_get_adc(int *slope_uv, int *intercept_uv) { u32 val; int ret; - ret = tegra_fuse_readl(FUSE_RESERVED_CALIB, &val); + ret = nvgpu_tegra_fuse_read(FUSE_RESERVED_CALIB, &val); if (ret) return ret; @@ -298,9 +298,9 @@ static int tegra_fuse_calib_gpcpll_get_adc(int *slope_uv, int *intercept_uv) } #ifdef CONFIG_TEGRA_USE_NA_GPCPLL -static bool tegra_fuse_can_use_na_gpcpll(void) +static bool nvgpu_fuse_can_use_na_gpcpll(void) { - return tegra_sku_info.gpu_speedo_id; + return nvgpu_tegra_get_gpu_speedo_id(); } #endif @@ -313,7 +313,7 @@ static int clk_config_calibration_params(struct gk20a *g) int slope, offs; struct pll_parms *p = &gpc_pll_params; - if (!tegra_fuse_calib_gpcpll_get_adc(&slope, &offs)) { + if (!nvgpu_fuse_calib_gpcpll_get_adc(&slope, &offs)) { p->uvdet_slope = slope; p->uvdet_offs = offs; } @@ -1182,7 +1182,7 @@ int gm20b_init_clk_setup_sw(struct gk20a *g) */ clk_config_calibration_params(g); #ifdef CONFIG_TEGRA_USE_NA_GPCPLL - if (tegra_fuse_can_use_na_gpcpll()) { + if (nvgpu_fuse_can_use_na_gpcpll()) { /* NA mode is supported only at max update rate 38.4 MHz */ BUG_ON(clk->gpc_pll.clk_in != gpc_pll_params.max_u); clk->gpc_pll.mode = GPC_PLL_MODE_DVFS; -- cgit v1.2.2