From dc281d6a9ebadaeb66dab092b40b7d6f4559ee39 Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Tue, 30 Apr 2019 17:19:51 -0700 Subject: gpu: nvgpu: add SET_CTX_MMU_DEBUG_MODE ioctl Added NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE ioctl to set MMU debug mode for a given context. Added gr.set_mmu_debug_mode HAL to change NV_PGPC_PRI_MMU_DEBUG_CTRL for a given channel. HAL implementation for native case is gm20b_gr_set_mmu_debug_mode. It internally uses regops, which directly writes to the register if the context is resident, or writes to gr context otherwise. Added NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE to enable the feature. NV_PGPC_PRI_MMU_DEBUG_CTRL has to be context switched in FECS ucode, so the feature is only enabled on TU104 for now. Bug 2515097 But 2713590 Change-Id: Ib4efaf06fc47a8539b4474f94c68c20ce225263f Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/2110720 (cherry-picked from commit af2ccb811d3de06f052b1dee39bd9ffa863ac8ce) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208767 Reviewed-by: Kajetan Dutka Reviewed-by: Alex Waterman Reviewed-by: Winnie Hsu Reviewed-by: mobile promotions GVS: Gerrit_Virtual_Submit Tested-by: Kajetan Dutka Tested-by: mobile promotions --- drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 23 ++++++++++- drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 4 +- drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 4 +- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 4 +- drivers/gpu/nvgpu/gv100/hal_gv100.c | 4 +- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 + drivers/gpu/nvgpu/include/nvgpu/enabled.h | 5 ++- drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 2 + drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c | 4 +- drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | 56 ++++++++++++++++++++++++++- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 3 +- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c | 1 + drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 3 +- drivers/gpu/nvgpu/vgpu/vgpu.c | 3 +- 14 files changed, 107 insertions(+), 11 deletions(-) (limited to 'drivers/gpu/nvgpu') diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index c67f7870..d00181af 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -1,7 +1,7 @@ /* * GM20B GPC MMU * - * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -33,6 +33,7 @@ #include #include "gk20a/gr_gk20a.h" +#include "gk20a/regops_gk20a.h" #include "gr_gm20b.h" #include "pmu_gm20b.h" @@ -1455,6 +1456,26 @@ u32 gr_gm20b_get_pmm_per_chiplet_offset(void) return (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + 1); } +int gm20b_gr_set_mmu_debug_mode(struct gk20a *g, + struct channel_gk20a *ch, bool enable) +{ + struct nvgpu_dbg_reg_op ctx_ops = { + .op = REGOP(WRITE_32), + .type = REGOP(TYPE_GR_CTX), + .offset = gr_gpcs_pri_mmu_debug_ctrl_r(), + .value_lo = enable ? + gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f() : + gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(), + }; + int err; + + err = gr_gk20a_exec_ctx_ops(ch, &ctx_ops, 1, 1, 0, NULL); + if (err != 0) { + nvgpu_err(g, "Failed to access register"); + } + return err; +} + void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable) { u32 reg_val, gpc_debug_ctrl; diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index 084b6157..81916c05 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h @@ -1,7 +1,7 @@ /* * GM20B GPC MMU * - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -125,5 +125,7 @@ int gr_gm20b_get_preemption_mode_flags(struct gk20a *g, void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, u32 global_esr); u32 gr_gm20b_get_pmm_per_chiplet_offset(void); +int gm20b_gr_set_mmu_debug_mode(struct gk20a *g, + struct channel_gk20a *ch, bool enable); void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable); #endif /* NVGPU_GM20B_GR_GM20B_H */ diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index c978f9aa..0865ace4 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -1,7 +1,7 @@ /* * GM20B Graphics * - * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -277,6 +277,7 @@ static const struct gpu_ops gm20b_ops = { .get_lrf_tex_ltc_dram_override = NULL, .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, + .set_mmu_debug_mode = gm20b_gr_set_mmu_debug_mode, .record_sm_error_state = gm20b_gr_record_sm_error_state, .clear_sm_error_state = gm20b_gr_clear_sm_error_state, .suspend_contexts = gr_gk20a_suspend_contexts, @@ -753,6 +754,7 @@ int gm20b_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false); + __nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, false); /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ if (gops->fuse.check_priv_security(g)) { diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 561d24d8..eea40d5e 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -1,7 +1,7 @@ /* * GP10B Tegra HAL interface * - * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -295,6 +295,7 @@ static const struct gpu_ops gp10b_ops = { .get_lrf_tex_ltc_dram_override = get_ecc_override_val, .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, + .set_mmu_debug_mode = NULL, .record_sm_error_state = gm20b_gr_record_sm_error_state, .clear_sm_error_state = gm20b_gr_clear_sm_error_state, .suspend_contexts = gr_gp10b_suspend_contexts, @@ -783,6 +784,7 @@ int gp10b_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, false); __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false); + __nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, false); /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ if (gops->fuse.check_priv_security(g)) { diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 9a3d2241..0e0417a0 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -1,7 +1,7 @@ /* * GV100 Tegra HAL interface * - * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -404,6 +404,7 @@ static const struct gpu_ops gv100_ops = { .get_num_hwpm_perfmon = gr_gv100_get_num_hwpm_perfmon, .set_pmm_register = gr_gv100_set_pmm_register, .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, + .set_mmu_debug_mode = NULL, .init_hwpm_pmm_register = gr_gv100_init_hwpm_pmm_register, .record_sm_error_state = gv11b_gr_record_sm_error_state, .clear_sm_error_state = gv11b_gr_clear_sm_error_state, @@ -1040,6 +1041,7 @@ int gv100_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false); __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true); __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false); + __nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, false); /* for now */ __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 68ea78a6..d80bf0f0 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -356,6 +356,7 @@ static const struct gpu_ops gv11b_ops = { .get_num_hwpm_perfmon = gr_gv100_get_num_hwpm_perfmon, .set_pmm_register = gr_gv100_set_pmm_register, .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, + .set_mmu_debug_mode = gm20b_gr_set_mmu_debug_mode, .init_hwpm_pmm_register = gr_gv100_init_hwpm_pmm_register, .record_sm_error_state = gv11b_gr_record_sm_error_state, .clear_sm_error_state = gv11b_gr_clear_sm_error_state, @@ -955,6 +956,7 @@ int gv11b_init_hal(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true); __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, true); + __nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, false); __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false); __nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, true); diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h index fc7bab90..77b54ab9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h @@ -181,10 +181,13 @@ struct gk20a; /* PLATFORM_ATOMIC support */ #define NVGPU_SUPPORT_PLATFORM_ATOMIC 71 +/* NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE is available */ +#define NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE 72 + /* * Must be greater than the largest bit offset in the above list. */ -#define NVGPU_MAX_ENABLED_BITS 72 +#define NVGPU_MAX_ENABLED_BITS 73U /** * nvgpu_is_enabled - Check if the passed flag is enabled. diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index a0af0c5c..f3a83602 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -529,6 +529,8 @@ struct gpu_ops { u32 num_ppcs, u32 reg_list_ppc_count, u32 *__offset_in_segment); void (*set_debug_mode)(struct gk20a *g, bool enable); + int (*set_mmu_debug_mode)(struct gk20a *g, + struct channel_gk20a *ch, bool enable); } gr; struct { void (*init_hw)(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c index dfa9edf3..8ad304bd 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2018, NVIDIA Corporation. All rights reserved. + * Copyright (c) 2011-2020, NVIDIA Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -224,6 +224,8 @@ static struct nvgpu_flags_mapping flags_mapping[] = { NVGPU_SUPPORT_SCG}, {NVGPU_GPU_FLAGS_SUPPORT_VPR, NVGPU_SUPPORT_VPR}, + {NVGPU_GPU_FLAGS_SUPPORT_SET_CTX_MMU_DEBUG_MODE, + NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE}, }; static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g) diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c index adf40d5d..f7a65f2b 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c @@ -1,7 +1,7 @@ /* * Tegra GK20A GPU Debugger/Profiler Driver * - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -117,6 +117,10 @@ static int nvgpu_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s, static int nvgpu_dbg_gpu_ioctl_hwpm_ctxsw_mode(struct dbg_session_gk20a *dbg_s, struct nvgpu_dbg_gpu_hwpm_ctxsw_mode_args *args); +static int nvgpu_dbg_gpu_ioctl_set_mmu_debug_mode( + struct dbg_session_gk20a *dbg_s, + struct nvgpu_dbg_gpu_set_ctx_mmu_debug_mode_args *args); + static int nvgpu_dbg_gpu_ioctl_suspend_resume_sm( struct dbg_session_gk20a *dbg_s, struct nvgpu_dbg_gpu_suspend_resume_all_sms_args *args); @@ -1072,6 +1076,51 @@ static int nvgpu_dbg_gpu_ioctl_hwpm_ctxsw_mode(struct dbg_session_gk20a *dbg_s, return err; } +static int nvgpu_dbg_gpu_ioctl_set_mmu_debug_mode( + struct dbg_session_gk20a *dbg_s, + struct nvgpu_dbg_gpu_set_ctx_mmu_debug_mode_args *args) +{ + int err; + struct gk20a *g = dbg_s->g; + struct channel_gk20a *ch; + bool enable = (args->mode == NVGPU_DBG_GPU_CTX_MMU_DEBUG_MODE_ENABLED); + + nvgpu_log_fn(g, "mode=%u", args->mode); + + if (args->reserved != 0U) { + return -EINVAL; + } + + if (g->ops.gr.set_mmu_debug_mode == NULL) { + return -ENOSYS; + } + + err = gk20a_busy(g); + if (err) { + nvgpu_err(g, "failed to poweron"); + return err; + } + + /* Take the global lock, since we'll be doing global regops */ + nvgpu_mutex_acquire(&g->dbg_sessions_lock); + + ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); + if (!ch) { + nvgpu_err(g, "no bound channel for mmu debug mode"); + goto clean_up; + } + + err = g->ops.gr.set_mmu_debug_mode(g, ch, enable); + if (err) { + nvgpu_err(g, "set mmu debug mode failed, err=%d", err); + } + +clean_up: + nvgpu_mutex_release(&g->dbg_sessions_lock); + gk20a_idle(g); + return err; +} + static int nvgpu_dbg_gpu_ioctl_suspend_resume_sm( struct dbg_session_gk20a *dbg_s, struct nvgpu_dbg_gpu_suspend_resume_all_sms_args *args) @@ -2030,6 +2079,11 @@ long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd, (struct nvgpu_dbg_gpu_set_sm_exception_type_mask_args *)buf); break; + case NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE: + err = nvgpu_dbg_gpu_ioctl_set_mmu_debug_mode(dbg_s, + (struct nvgpu_dbg_gpu_set_ctx_mmu_debug_mode_args *)buf); + break; + default: nvgpu_err(g, "unrecognized dbg gpu ioctl cmd: 0x%x", diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 7c800d5f..917ac638 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -234,6 +234,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { .get_offset_in_gpccs_segment = gr_gk20a_get_offset_in_gpccs_segment, .set_debug_mode = gm20b_gr_set_debug_mode, + .set_mmu_debug_mode = NULL, }, .fb = { .init_hw = NULL, diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c index baddae13..2190478e 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c @@ -44,6 +44,7 @@ int vgpu_gv11b_init_gpu_characteristics(struct gk20a *g) __nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true); __nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true); __nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, true); + __nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, false); return 0; } diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 78ea5643..41850c91 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -189,6 +189,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .get_hw_accessor_stream_out_mode = gr_gv100_get_hw_accessor_stream_out_mode, .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode, + .set_mmu_debug_mode = NULL, .record_sm_error_state = gv11b_gr_record_sm_error_state, .clear_sm_error_state = vgpu_gr_clear_sm_error_state, .suspend_contexts = vgpu_gr_suspend_contexts, diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.c b/drivers/gpu/nvgpu/vgpu/vgpu.c index 5a3f0046..e193ace9 100644 --- a/drivers/gpu/nvgpu/vgpu/vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/vgpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -282,6 +282,7 @@ int vgpu_init_gpu_characteristics(struct gk20a *g) /* features vgpu does not support */ __nvgpu_set_enabled(g, NVGPU_SUPPORT_RESCHEDULE_RUNLIST, false); + __nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, false); return 0; } -- cgit v1.2.2