From b817e9e207cca88698d28b6b4ab410f03d715171 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Mon, 22 May 2017 14:34:08 -0700 Subject: gpu: nvgpu: add fifo ops get_mmu_fault_info This is needed to take care of gp10b h/w header changes. gp10b changes as compared to legacy gpu chips -fault_info_fault_type field width is changed -fault_info_write field is removed -fault_info_access_type field is added -fault_info_engine_subid is removed -fault_info_client_type is added -fault_info_client field width has changed JIRA GPUT19X-7 JIRA GPUT19X-12 Change-Id: Iebf28cc6c851830524049b67a71cd72fb4a28948 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/1487319 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 47 +++++++++++++--------- drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 2 + drivers/gpu/nvgpu/gk20a/gk20a.h | 2 + drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 1 + drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | 32 +++++++++++++++ .../nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h | 6 ++- 6 files changed, 69 insertions(+), 21 deletions(-) (limited to 'drivers/gpu/nvgpu') diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index c7cd1d73..ac3a3d57 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -1165,29 +1165,12 @@ static const char * const does_not_exist[] = { "does not exist" }; -/* reads info from hardware and fills in mmu fault info record */ -static void get_exception_mmu_fault_info( - struct gk20a *g, u32 mmu_fault_id, +static void get_exception_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id, struct mmu_fault_info *mmfault) { - u32 fault_info; - u32 addr_lo, addr_hi; - - gk20a_dbg_fn("mmu_fault_id %d", mmu_fault_id); - - memset(mmfault, 0, sizeof(*mmfault)); - - fault_info = gk20a_readl(g, - fifo_intr_mmu_fault_info_r(mmu_fault_id)); - mmfault->fault_type = - fifo_intr_mmu_fault_info_type_v(fault_info); - mmfault->access_type = - fifo_intr_mmu_fault_info_write_v(fault_info); - mmfault->client_type = - fifo_intr_mmu_fault_info_engine_subid_v(fault_info); - mmfault->client_id = - fifo_intr_mmu_fault_info_client_v(fault_info); + g->ops.fifo.get_mmu_fault_info(g, mmu_fault_id, mmfault); + /* parse info */ if (mmfault->fault_type >= ARRAY_SIZE(fault_type_descs)) { WARN_ON(mmfault->fault_type >= ARRAY_SIZE(fault_type_descs)); mmfault->fault_type_desc = does_not_exist[0]; @@ -1224,6 +1207,29 @@ static void get_exception_mmu_fault_info( mmfault->client_id_desc = gpc_client_descs[mmfault->client_id]; } +} + +/* reads info from hardware and fills in mmu fault info record */ +void gk20a_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id, + struct mmu_fault_info *mmfault) +{ + u32 fault_info; + u32 addr_lo, addr_hi; + + gk20a_dbg_fn("mmu_fault_id %d", mmu_fault_id); + + memset(mmfault, 0, sizeof(*mmfault)); + + fault_info = gk20a_readl(g, + fifo_intr_mmu_fault_info_r(mmu_fault_id)); + mmfault->fault_type = + fifo_intr_mmu_fault_info_type_v(fault_info); + mmfault->access_type = + fifo_intr_mmu_fault_info_write_v(fault_info); + mmfault->client_type = + fifo_intr_mmu_fault_info_engine_subid_v(fault_info); + mmfault->client_id = + fifo_intr_mmu_fault_info_client_v(fault_info); addr_lo = gk20a_readl(g, fifo_intr_mmu_fault_lo_r(mmu_fault_id)); addr_hi = gk20a_readl(g, fifo_intr_mmu_fault_hi_r(mmu_fault_id)); @@ -4381,6 +4387,7 @@ void gk20a_init_fifo(struct gpu_ops *gops) gops->fifo.preempt_tsg = gk20a_fifo_preempt_tsg; gops->fifo.update_runlist = gk20a_fifo_update_runlist; gops->fifo.trigger_mmu_fault = gk20a_fifo_trigger_mmu_fault; + gops->fifo.get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info; gops->fifo.apply_pb_timeout = gk20a_fifo_apply_pb_timeout; gops->fifo.wait_engine_idle = gk20a_fifo_wait_engine_idle; gops->fifo.get_num_fifos = gk20a_fifo_get_num_fifos; diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index 55075f3b..6c8868a2 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h @@ -406,4 +406,6 @@ int gk20a_fifo_alloc_syncpt_buf(struct channel_gk20a *c, u32 syncpt_id, struct nvgpu_mem *syncpt_buf); #endif +void gk20a_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id, + struct mmu_fault_info *mmfault); #endif /*__GR_GK20A_H__*/ diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 1dff07fa..10417084 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -439,6 +439,8 @@ struct gpu_ops { bool wait_for_finish); void (*trigger_mmu_fault)(struct gk20a *g, unsigned long engine_ids); + void (*get_mmu_fault_info)(struct gk20a *g, u32 mmu_fault_id, + struct mmu_fault_info *mmfault); void (*apply_pb_timeout)(struct gk20a *g); int (*wait_engine_idle)(struct gk20a *g); u32 (*get_num_fifos)(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index 6fb5802b..df3015da 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c @@ -206,6 +206,7 @@ void gm20b_init_fifo(struct gpu_ops *gops) gops->fifo.preempt_tsg = gk20a_fifo_preempt_tsg; gops->fifo.update_runlist = gk20a_fifo_update_runlist; gops->fifo.trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault; + gops->fifo.get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info; gops->fifo.wait_engine_idle = gk20a_fifo_wait_engine_idle; gops->fifo.get_num_fifos = gm20b_fifo_get_num_fifos; gops->fifo.get_pbdma_signature = gk20a_fifo_get_pbdma_signature; diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c index 59e127b7..386318e7 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c @@ -277,9 +277,41 @@ static void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) pbdma_intr_0_device_pending_f(); } +static void gp10b_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id, + struct mmu_fault_info *mmfault) +{ + u32 fault_info; + u32 addr_lo, addr_hi; + + gk20a_dbg_fn("mmu_fault_id %d", mmu_fault_id); + + memset(mmfault, 0, sizeof(*mmfault)); + + fault_info = gk20a_readl(g, + fifo_intr_mmu_fault_info_r(mmu_fault_id)); + mmfault->fault_type = + fifo_intr_mmu_fault_info_type_v(fault_info); + mmfault->access_type = + fifo_intr_mmu_fault_info_access_type_v(fault_info); + mmfault->client_type = + fifo_intr_mmu_fault_info_client_type_v(fault_info); + mmfault->client_id = + fifo_intr_mmu_fault_info_client_v(fault_info); + + addr_lo = gk20a_readl(g, fifo_intr_mmu_fault_lo_r(mmu_fault_id)); + addr_hi = gk20a_readl(g, fifo_intr_mmu_fault_hi_r(mmu_fault_id)); + mmfault->fault_addr = hi32_lo32_to_u64(addr_hi, addr_lo); + /* note:ignoring aperture */ + mmfault->inst_ptr = fifo_intr_mmu_fault_inst_ptr_v( + gk20a_readl(g, fifo_intr_mmu_fault_inst_r(mmu_fault_id))); + /* note: inst_ptr is a 40b phys addr. */ + mmfault->inst_ptr <<= fifo_intr_mmu_fault_inst_ptr_align_shift_v(); +} + void gp10b_init_fifo(struct gpu_ops *gops) { gm20b_init_fifo(gops); + gops->fifo.get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info; gops->fifo.setup_ramfc = channel_gp10b_setup_ramfc; gops->fifo.get_pbdma_signature = gp10b_fifo_get_pbdma_signature; gops->fifo.resetup_ramfc = gp10b_fifo_resetup_ramfc; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h index 8370d4c6..541b4dd4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -302,6 +302,10 @@ static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r) { return (r >> 0) & 0x1f; } +static inline u32 fifo_intr_mmu_fault_info_access_type_v(u32 r) +{ + return (r >> 16) & 0x7; +} static inline u32 fifo_intr_mmu_fault_info_client_type_v(u32 r) { return (r >> 20) & 0x1; -- cgit v1.2.2