From 8a76e8b4910480efcdeb47d18cb209e247d9eda8 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 16 Aug 2018 14:05:02 -0700 Subject: gpu: nvgpu: Split HUB and GPC MMU debug mode set HUB and GPC MMU debug modes were set in the same function. This introduced a dependency from FB code to GR registers. Split setting of GPC MMU debug mode to GR HAL. Change-Id: I003446f9dfa147f526bd01d3b6130f4037d9b183 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1801420 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/fb/fb_gm20b.c | 10 ++-------- drivers/gpu/nvgpu/gk20a/gk20a.h | 1 + drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 16 ++++++++++++++++ drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 1 + drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 + drivers/gpu/nvgpu/gp106/hal_gp106.c | 1 + drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 + drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 + drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 1 + drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 1 + 11 files changed, 27 insertions(+), 8 deletions(-) (limited to 'drivers/gpu/nvgpu') diff --git a/drivers/gpu/nvgpu/common/fb/fb_gm20b.c b/drivers/gpu/nvgpu/common/fb/fb_gm20b.c index 5e78f636..56c7429a 100644 --- a/drivers/gpu/nvgpu/common/fb/fb_gm20b.c +++ b/drivers/gpu/nvgpu/common/fb/fb_gm20b.c @@ -35,7 +35,6 @@ #include #include -#include #define VPR_INFO_FETCH_WAIT (5) #define WPR_INFO_ADDR_ALIGNMENT 0x0000000c @@ -209,15 +208,13 @@ bool gm20b_fb_debug_mode_enabled(struct gk20a *g) void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable) { - u32 reg_val, fb_debug_ctrl, gpc_debug_ctrl; + u32 reg_val, fb_debug_ctrl; if (enable) { fb_debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f(); - gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f(); g->mmu_debug_ctrl = true; } else { fb_debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f(); - gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(); g->mmu_debug_ctrl = false; } @@ -226,8 +223,5 @@ void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable) fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl); gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val); - reg_val = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r()); - reg_val = set_field(reg_val, - gr_gpcs_pri_mmu_debug_ctrl_debug_m(), gpc_debug_ctrl); - gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), reg_val); + g->ops.gr.set_debug_mode(g, enable); } diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index f62dfb94..f0b0bebe 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -509,6 +509,7 @@ struct gpu_ops { enum ctxsw_addr_type addr_type, u32 num_tpcs, u32 num_ppcs, u32 reg_list_ppc_count, u32 *__offset_in_segment); + void (*set_debug_mode)(struct gk20a *g, bool enable); } gr; struct { void (*init_hw)(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 7ed36144..101f4211 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -1516,3 +1516,19 @@ u32 gr_gm20b_get_pmm_per_chiplet_offset(void) { return (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + 1); } + +void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable) +{ + u32 reg_val, gpc_debug_ctrl; + + if (enable) { + gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f(); + } else { + gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(); + } + + reg_val = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r()); + reg_val = set_field(reg_val, + gr_gpcs_pri_mmu_debug_ctrl_debug_m(), gpc_debug_ctrl); + gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), reg_val); +} diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index 7c3baa59..0f5dfe53 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h @@ -127,4 +127,5 @@ int gr_gm20b_get_preemption_mode_flags(struct gk20a *g, void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, u32 global_esr); u32 gr_gm20b_get_pmm_per_chiplet_offset(void); +void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable); #endif diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index a2b23cca..3b80ede0 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -329,6 +329,7 @@ static const struct gpu_ops gm20b_ops = { .commit_global_ctx_buffers = gr_gk20a_commit_global_ctx_buffers, .get_offset_in_gpccs_segment = gr_gk20a_get_offset_in_gpccs_segment, + .set_debug_mode = gm20b_gr_set_debug_mode, }, .fb = { .reset = fb_gk20a_reset, diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 167bfaac..42ff647c 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -403,6 +403,7 @@ static const struct gpu_ops gp106_ops = { .commit_global_ctx_buffers = gr_gk20a_commit_global_ctx_buffers, .get_offset_in_gpccs_segment = gr_gk20a_get_offset_in_gpccs_segment, + .set_debug_mode = gm20b_gr_set_debug_mode, }, .fb = { .reset = gp106_fb_reset, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index f4ae1314..9e42c6ba 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -365,6 +365,7 @@ static const struct gpu_ops gp10b_ops = { .commit_global_ctx_buffers = gr_gk20a_commit_global_ctx_buffers, .get_offset_in_gpccs_segment = gr_gk20a_get_offset_in_gpccs_segment, + .set_debug_mode = gm20b_gr_set_debug_mode, }, .fb = { .reset = fb_gk20a_reset, diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 339d7813..0529fd91 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -459,6 +459,7 @@ static const struct gpu_ops gv100_ops = { .get_nonpes_aware_tpc = gr_gv11b_get_nonpes_aware_tpc, .get_offset_in_gpccs_segment = gr_gk20a_get_offset_in_gpccs_segment, + .set_debug_mode = gm20b_gr_set_debug_mode, }, .fb = { .reset = gv100_fb_reset, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index ff9fc8c6..d87975d1 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -422,6 +422,7 @@ static const struct gpu_ops gv11b_ops = { .get_nonpes_aware_tpc = gr_gv11b_get_nonpes_aware_tpc, .get_offset_in_gpccs_segment = gr_gk20a_get_offset_in_gpccs_segment, + .set_debug_mode = gm20b_gr_set_debug_mode, }, .fb = { .reset = gv11b_fb_reset, diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 3aa9b092..fa8395eb 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c @@ -235,6 +235,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { .commit_global_ctx_buffers = gr_gk20a_commit_global_ctx_buffers, .get_offset_in_gpccs_segment = gr_gk20a_get_offset_in_gpccs_segment, + .set_debug_mode = gm20b_gr_set_debug_mode, }, .fb = { .reset = NULL, diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 44bcb123..66f25e24 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -272,6 +272,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .commit_global_ctx_buffers = gr_gk20a_commit_global_ctx_buffers, .get_offset_in_gpccs_segment = gr_gk20a_get_offset_in_gpccs_segment, + .set_debug_mode = gm20b_gr_set_debug_mode, }, .fb = { .reset = NULL, -- cgit v1.2.2