From 86691b59c6fae2b091855c0f4d44079cad8529b1 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 27 Dec 2017 13:04:17 -0800 Subject: gpu: nvgpu: Remove bare channel scheduling Remove scheduling IOCTL implementations for bare channels. Also removes code that constructs bare channels in runlist. Bug 1842197 Change-Id: I6e833b38e24a2f2c45c7993edf939d365eaf41f0 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1627326 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/linux/debug_fifo.c | 10 +-- drivers/gpu/nvgpu/common/linux/ioctl_channel.c | 55 ++----------- drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c | 55 +------------ drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.h | 1 - .../nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c | 1 - .../nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c | 1 - .../nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c | 1 - drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | 5 +- drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 40 ---------- drivers/gpu/nvgpu/gk20a/channel_gk20a.h | 6 -- drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 90 +--------------------- drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 3 - drivers/gpu/nvgpu/gk20a/gk20a.h | 4 +- drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | 2 +- drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 - drivers/gpu/nvgpu/gp106/hal_gp106.c | 1 - drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 - drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 - drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 - 19 files changed, 22 insertions(+), 257 deletions(-) (limited to 'drivers/gpu/nvgpu') diff --git a/drivers/gpu/nvgpu/common/linux/debug_fifo.c b/drivers/gpu/nvgpu/common/linux/debug_fifo.c index 94a16b70..ad157ee7 100644 --- a/drivers/gpu/nvgpu/common/linux/debug_fifo.c +++ b/drivers/gpu/nvgpu/common/linux/debug_fifo.c @@ -81,16 +81,16 @@ static int gk20a_fifo_sched_debugfs_seq_show( return ret; if (gk20a_channel_get(ch)) { - if (gk20a_is_channel_marked_as_tsg(ch)) - tsg = &f->tsg[ch->tsgid]; + tsg = tsg_gk20a_from_ch(ch); - seq_printf(s, "%-8d %-8d %-8d %-9d %-8d %-10d %-8d %-8d\n", + if (tsg) + seq_printf(s, "%-8d %-8d %-8d %-9d %-8d %-10d %-8d %-8d\n", ch->chid, ch->tsgid, ch->tgid, - tsg ? tsg->timeslice_us : ch->timeslice_us, + tsg->timeslice_us, ch->timeout_ms_max, - tsg ? tsg->interleave_level : ch->interleave_level, + tsg->interleave_level, ch->ch_ctx.gr_ctx ? ch->ch_ctx.gr_ctx->graphics_preempt_mode : U32_MAX, ch->ch_ctx.gr_ctx ? ch->ch_ctx.gr_ctx->compute_preempt_mode : U32_MAX); gk20a_channel_put(ch); diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c index 65d560c7..94501a89 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c @@ -76,11 +76,15 @@ static void gk20a_channel_trace_sched_param( const char *compute_preempt_mode), struct channel_gk20a *ch) { + struct tsg_gk20a *tsg = tsg_gk20a_from_ch(ch); + + if (!tsg) + return; + (trace)(ch->chid, ch->tsgid, ch->pid, - gk20a_is_channel_marked_as_tsg(ch) ? - tsg_gk20a_from_ch(ch)->timeslice_us : ch->timeslice_us, + tsg_gk20a_from_ch(ch)->timeslice_us, ch->timeout_ms_max, - gk20a_fifo_interleave_level_name(ch->interleave_level), + gk20a_fifo_interleave_level_name(tsg->interleave_level), gr_gk20a_graphics_preempt_mode_name(ch->ch_ctx.gr_ctx ? ch->ch_ctx.gr_ctx->graphics_preempt_mode : 0), gr_gk20a_compute_preempt_mode_name(ch->ch_ctx.gr_ctx ? @@ -795,28 +799,6 @@ u32 nvgpu_get_common_runlist_level(u32 level) return level; } -static int gk20a_ioctl_channel_set_runlist_interleave(struct channel_gk20a *ch, - u32 level) -{ - int err = 0; - - err = gk20a_busy(ch->g); - if (err) { - nvgpu_err(ch->g, "failed to power on, %d", err); - goto fail; - } - - level = nvgpu_get_common_runlist_level(level); - err = gk20a_channel_set_runlist_interleave(ch, level); - - gk20a_idle(ch->g); - gk20a_channel_trace_sched_param( - trace_gk20a_channel_set_runlist_interleave, ch); - -fail: - return err; -} - static u32 nvgpu_obj_ctx_user_flags_to_common_flags(u32 user_flags) { u32 flags = 0; @@ -1229,29 +1211,6 @@ long gk20a_channel_ioctl(struct file *filp, err = gk20a_channel_set_wdt_status(ch, (struct nvgpu_channel_wdt_args *)buf); break; - case NVGPU_IOCTL_CHANNEL_SET_RUNLIST_INTERLEAVE: - err = gk20a_ioctl_channel_set_runlist_interleave(ch, - ((struct nvgpu_runlist_interleave_args *)buf)->level); - break; - case NVGPU_IOCTL_CHANNEL_SET_TIMESLICE: - err = gk20a_busy(ch->g); - if (err) { - dev_err(dev, - "%s: failed to host gk20a for ioctl cmd: 0x%x", - __func__, cmd); - break; - } - err = ch->g->ops.fifo.channel_set_timeslice(ch, - ((struct nvgpu_timeslice_args *)buf)->timeslice_us); - - gk20a_idle(ch->g); - gk20a_channel_trace_sched_param( - trace_gk20a_channel_set_timeslice, ch); - break; - case NVGPU_IOCTL_CHANNEL_GET_TIMESLICE: - ((struct nvgpu_timeslice_args *)buf)->timeslice_us = - gk20a_channel_get_timeslice(ch); - break; case NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE: err = nvgpu_ioctl_channel_set_preemption_mode(ch, ((struct nvgpu_preemption_mode_args *)buf)->graphics_preempt_mode, diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c index e06b41da..6b8c630b 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c @@ -604,8 +604,8 @@ int vgpu_fifo_wait_engine_idle(struct gk20a *g) return 0; } -static int vgpu_fifo_tsg_set_runlist_interleave(struct gk20a *g, - u32 tsgid, +int vgpu_fifo_set_runlist_interleave(struct gk20a *g, + u32 id, u32 runlist_id, u32 new_level) { @@ -618,62 +618,13 @@ static int vgpu_fifo_tsg_set_runlist_interleave(struct gk20a *g, msg.cmd = TEGRA_VGPU_CMD_TSG_SET_RUNLIST_INTERLEAVE; msg.handle = vgpu_get_handle(g); - p->tsg_id = tsgid; - p->level = new_level; - err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); - WARN_ON(err || msg.ret); - return err ? err : msg.ret; -} - -int vgpu_fifo_set_runlist_interleave(struct gk20a *g, - u32 id, - bool is_tsg, - u32 runlist_id, - u32 new_level) -{ - struct tegra_vgpu_cmd_msg msg; - struct tegra_vgpu_channel_runlist_interleave_params *p = - &msg.params.channel_interleave; - struct channel_gk20a *ch; - int err; - - gk20a_dbg_fn(""); - - if (is_tsg) - return vgpu_fifo_tsg_set_runlist_interleave(g, id, - runlist_id, new_level); - - ch = &g->fifo.channel[id]; - msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE; - msg.handle = vgpu_get_handle(ch->g); - p->handle = ch->virt_ctx; + p->tsg_id = id; p->level = new_level; err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); WARN_ON(err || msg.ret); return err ? err : msg.ret; } -int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice) -{ - struct tegra_vgpu_cmd_msg msg; - struct tegra_vgpu_channel_timeslice_params *p = - &msg.params.channel_timeslice; - int err; - - gk20a_dbg_fn(""); - - msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE; - msg.handle = vgpu_get_handle(ch->g); - p->handle = ch->virt_ctx; - p->timeslice_us = timeslice; - err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); - err = err ? err : msg.ret; - WARN_ON(err); - if (!err) - ch->timeslice_us = p->timeslice_us; - return err; -} - int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, u32 err_code, bool verbose) { diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.h index 5aefb356..92789ddd 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.h +++ b/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.h @@ -42,7 +42,6 @@ int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id, int vgpu_fifo_wait_engine_idle(struct gk20a *g); int vgpu_fifo_set_runlist_interleave(struct gk20a *g, u32 id, - bool is_tsg, u32 runlist_id, u32 new_level); int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice); diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c index 6f50dbb8..74fa65f3 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c @@ -260,7 +260,6 @@ static const struct gpu_ops vgpu_gm20b_ops = { .alloc_inst = vgpu_channel_alloc_inst, .free_inst = vgpu_channel_free_inst, .setup_ramfc = vgpu_channel_setup_ramfc, - .channel_set_timeslice = vgpu_channel_set_timeslice, .default_timeslice_us = vgpu_fifo_default_timeslice_us, .setup_userd = gk20a_fifo_setup_userd, .userd_gp_get = gk20a_fifo_userd_gp_get, diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c index 31608200..66ef6e00 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c @@ -290,7 +290,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { .alloc_inst = vgpu_channel_alloc_inst, .free_inst = vgpu_channel_free_inst, .setup_ramfc = vgpu_channel_setup_ramfc, - .channel_set_timeslice = vgpu_channel_set_timeslice, .default_timeslice_us = vgpu_fifo_default_timeslice_us, .setup_userd = gk20a_fifo_setup_userd, .userd_gp_get = gk20a_fifo_userd_gp_get, diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c index b41d9dc3..1523c2de 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c @@ -331,7 +331,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { .alloc_inst = vgpu_channel_alloc_inst, .free_inst = vgpu_channel_free_inst, .setup_ramfc = vgpu_channel_setup_ramfc, - .channel_set_timeslice = vgpu_channel_set_timeslice, .default_timeslice_us = vgpu_fifo_default_timeslice_us, .setup_userd = gk20a_fifo_setup_userd, .userd_gp_get = gv11b_userd_gp_get, diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c index 5e2fc6b3..ec20a679 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c @@ -504,7 +504,7 @@ u32 gk20a_ce_create_context(struct gk20a *g, /* -1 means default channel timeslice value */ if (timeslice != -1) { - err = gk20a_fifo_set_timeslice(ce_ctx->ch, timeslice); + err = gk20a_fifo_tsg_set_timeslice(ce_ctx->tsg, timeslice); if (err) { nvgpu_err(g, "ce: could not set the channel timeslice value for CE context"); @@ -514,7 +514,8 @@ u32 gk20a_ce_create_context(struct gk20a *g, /* -1 means default channel runlist level */ if (runlist_level != -1) { - err = gk20a_channel_set_runlist_interleave(ce_ctx->ch, runlist_level); + err = gk20a_tsg_set_runlist_interleave(ce_ctx->tsg, + runlist_level); if (err) { nvgpu_err(g, "ce: could not set the runlist interleave for CE context"); diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index f4a49a4b..aeac490a 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c @@ -129,16 +129,6 @@ int channel_gk20a_commit_va(struct channel_gk20a *c) return 0; } -u32 gk20a_channel_get_timeslice(struct channel_gk20a *ch) -{ - struct gk20a *g = ch->g; - - if (!ch->timeslice_us) - return g->ops.fifo.default_timeslice_us(g); - - return ch->timeslice_us; -} - int gk20a_channel_get_timescale_from_timeslice(struct gk20a *g, int timeslice_period, int *__timeslice_timeout, int *__timeslice_scale) @@ -312,34 +302,6 @@ void gk20a_disable_channel(struct channel_gk20a *ch) channel_gk20a_update_runlist(ch, false); } -int gk20a_channel_set_runlist_interleave(struct channel_gk20a *ch, - u32 level) -{ - struct gk20a *g = ch->g; - int ret; - - if (gk20a_is_channel_marked_as_tsg(ch)) { - nvgpu_err(g, "invalid operation for TSG!"); - return -EINVAL; - } - - switch (level) { - case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW: - case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM: - case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH: - ret = g->ops.fifo.set_runlist_interleave(g, ch->chid, - false, 0, level); - break; - default: - ret = -EINVAL; - break; - } - - gk20a_dbg(gpu_dbg_sched, "chid=%u interleave=%u", ch->chid, level); - - return ret ? ret : g->ops.fifo.update_runlist(g, ch->runlist_id, ~0, true, true); -} - static void gk20a_wait_until_counter_is_N( struct channel_gk20a *ch, nvgpu_atomic_t *counter, int wait_value, struct nvgpu_cond *c, const char *caller, const char *counter_name) @@ -742,8 +704,6 @@ struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g, ch->has_timedout = false; ch->wdt_enabled = true; ch->obj_class = 0; - ch->interleave_level = NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW; - ch->timeslice_us = g->timeslice_low_priority_us; #ifdef CONFIG_TEGRA_19x_GPU memset(&ch->t19x, 0, sizeof(struct channel_t19x)); #endif diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h index b43c5638..596b85f3 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h @@ -247,7 +247,6 @@ struct channel_gk20a { bool has_timedout; u32 timeout_ms_max; bool timeout_debug_dump; - unsigned int timeslice_us; struct nvgpu_mutex sync_lock; struct gk20a_channel_sync *sync; @@ -256,8 +255,6 @@ struct channel_gk20a { u64 virt_ctx; #endif - u32 interleave_level; - u32 runlist_id; bool is_privileged_channel; @@ -355,12 +352,9 @@ void channel_gk20a_joblist_unlock(struct channel_gk20a *c); bool channel_gk20a_joblist_is_empty(struct channel_gk20a *c); int channel_gk20a_update_runlist(struct channel_gk20a *c, bool add); -u32 gk20a_channel_get_timeslice(struct channel_gk20a *ch); int gk20a_channel_get_timescale_from_timeslice(struct gk20a *g, int timeslice_period, int *__timeslice_timeout, int *__timeslice_scale); -int gk20a_channel_set_runlist_interleave(struct channel_gk20a *ch, - u32 level); int channel_gk20a_alloc_job(struct channel_gk20a *c, struct channel_gk20a_job **job_out); diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index fc71e907..194d5e3c 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -3075,48 +3075,11 @@ static u32 *gk20a_runlist_construct_locked(struct fifo_gk20a *f, bool last_level = cur_level == NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH; struct channel_gk20a *ch; bool skip_next = false; - u32 chid, tsgid, count = 0; + u32 tsgid, count = 0; u32 runlist_entry_words = f->runlist_entry_size / sizeof(u32); gk20a_dbg_fn(""); - /* for each bare channel, CH, on this level, insert all higher-level - channels and TSGs before inserting CH. */ - for_each_set_bit(chid, runlist->active_channels, f->num_channels) { - ch = &f->channel[chid]; - - if (ch->interleave_level != cur_level) - continue; - - if (gk20a_is_channel_marked_as_tsg(ch)) - continue; - - if (!last_level && !skip_next) { - runlist_entry = gk20a_runlist_construct_locked(f, - runlist, - cur_level + 1, - runlist_entry, - interleave_enabled, - false, - entries_left); - /* if interleaving is disabled, higher-level channels - and TSGs only need to be inserted once */ - if (!interleave_enabled) - skip_next = true; - } - - if (!(*entries_left)) - return NULL; - - gk20a_dbg_info("add channel %d to runlist", chid); - f->g->ops.fifo.get_ch_runlist_entry(ch, runlist_entry); - gk20a_dbg_info("run list count %d runlist [0] %x [1] %x\n", - count, runlist_entry[0], runlist_entry[1]); - runlist_entry += runlist_entry_words; - count++; - (*entries_left)--; - } - /* for each TSG, T, on this level, insert all higher-level channels and TSGs before inserting T. */ for_each_set_bit(tsgid, runlist->active_tsgs, f->num_channels) { @@ -3204,16 +3167,12 @@ static u32 *gk20a_runlist_construct_locked(struct fifo_gk20a *f, int gk20a_fifo_set_runlist_interleave(struct gk20a *g, u32 id, - bool is_tsg, u32 runlist_id, u32 new_level) { gk20a_dbg_fn(""); - if (is_tsg) - g->fifo.tsg[id].interleave_level = new_level; - else - g->fifo.channel[id].interleave_level = new_level; + g->fifo.tsg[id].interleave_level = new_level; return 0; } @@ -3917,51 +3876,6 @@ int gk20a_fifo_setup_ramfc(struct channel_gk20a *c, return gk20a_fifo_commit_userd(c); } -static int channel_gk20a_set_schedule_params(struct channel_gk20a *c) -{ - int shift = 0, value = 0; - - gk20a_channel_get_timescale_from_timeslice(c->g, - c->timeslice_us, &value, &shift); - - /* disable channel */ - c->g->ops.fifo.disable_channel(c); - - /* preempt the channel */ - WARN_ON(c->g->ops.fifo.preempt_channel(c->g, c->chid)); - - /* set new timeslice */ - nvgpu_mem_wr32(c->g, &c->inst_block, ram_fc_runlist_timeslice_w(), - value | (shift << 12) | - fifo_runlist_timeslice_enable_true_f()); - - /* enable channel */ - c->g->ops.fifo.enable_channel(c); - - return 0; -} - -int gk20a_fifo_set_timeslice(struct channel_gk20a *ch, u32 timeslice) -{ - struct gk20a *g = ch->g; - - if (gk20a_is_channel_marked_as_tsg(ch)) { - nvgpu_err(g, "invalid operation for TSG!"); - return -EINVAL; - } - - if (timeslice < g->min_timeslice_us || - timeslice > g->max_timeslice_us) - return -EINVAL; - - ch->timeslice_us = timeslice; - - gk20a_dbg(gpu_dbg_sched, "chid=%u timeslice=%u us", - ch->chid, timeslice); - - return channel_gk20a_set_schedule_params(ch); -} - void gk20a_fifo_setup_ramfc_for_privileged_channel(struct channel_gk20a *c) { struct gk20a *g = c->g; diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index 3587ffa8..7fdd3b6b 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h @@ -297,12 +297,10 @@ struct channel_gk20a *gk20a_fifo_channel_from_chid(struct gk20a *g, void gk20a_fifo_issue_preempt(struct gk20a *g, u32 id, bool is_tsg); int gk20a_fifo_set_runlist_interleave(struct gk20a *g, u32 id, - bool is_tsg, u32 runlist_id, u32 new_level); int gk20a_fifo_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice); - const char *gk20a_fifo_interleave_level_name(u32 interleave_level); int gk20a_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type, @@ -383,7 +381,6 @@ void __locked_fifo_preempt_timeout_rc(struct gk20a *g, u32 id, int gk20a_fifo_setup_ramfc(struct channel_gk20a *c, u64 gpfifo_base, u32 gpfifo_entries, unsigned long timeout, u32 flags); -int gk20a_fifo_set_timeslice(struct channel_gk20a *ch, unsigned int timeslice); void gk20a_fifo_setup_ramfc_for_privileged_channel(struct channel_gk20a *c); int gk20a_fifo_alloc_inst(struct gk20a *g, struct channel_gk20a *ch); void gk20a_fifo_free_inst(struct gk20a *g, struct channel_gk20a *ch); diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index ebe29bc3..6a669d88 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -535,10 +535,8 @@ struct gpu_ops { u32 (*get_num_fifos)(struct gk20a *g); u32 (*get_pbdma_signature)(struct gk20a *g); int (*set_runlist_interleave)(struct gk20a *g, u32 id, - bool is_tsg, u32 runlist_id, + u32 runlist_id, u32 new_level); - int (*channel_set_timeslice)(struct channel_gk20a *ch, - u32 timeslice); int (*tsg_set_timeslice)(struct tsg_gk20a *tsg, u32 timeslice); u32 (*default_timeslice_us)(struct gk20a *); int (*force_reset_ch)(struct channel_gk20a *ch, diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c index 64d521a0..ff700372 100644 --- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c @@ -211,7 +211,7 @@ int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level) case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM: case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH: ret = g->ops.fifo.set_runlist_interleave(g, tsg->tsgid, - true, 0, level); + 0, level); if (!ret) tsg->interleave_level = level; break; diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index d89ff2fe..c29f7267 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -387,7 +387,6 @@ static const struct gpu_ops gm20b_ops = { .alloc_inst = gk20a_fifo_alloc_inst, .free_inst = gk20a_fifo_free_inst, .setup_ramfc = gk20a_fifo_setup_ramfc, - .channel_set_timeslice = gk20a_fifo_set_timeslice, .default_timeslice_us = gk20a_fifo_default_timeslice_us, .setup_userd = gk20a_fifo_setup_userd, .userd_gp_get = gk20a_fifo_userd_gp_get, diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 2150b1ec..9052b4b2 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -442,7 +442,6 @@ static const struct gpu_ops gp106_ops = { .alloc_inst = gk20a_fifo_alloc_inst, .free_inst = gk20a_fifo_free_inst, .setup_ramfc = channel_gp10b_setup_ramfc, - .channel_set_timeslice = gk20a_fifo_set_timeslice, .default_timeslice_us = gk20a_fifo_default_timeslice_us, .setup_userd = gk20a_fifo_setup_userd, .userd_gp_get = gk20a_fifo_userd_gp_get, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 06311347..5e8e7acc 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -414,7 +414,6 @@ static const struct gpu_ops gp10b_ops = { .alloc_inst = gk20a_fifo_alloc_inst, .free_inst = gk20a_fifo_free_inst, .setup_ramfc = channel_gp10b_setup_ramfc, - .channel_set_timeslice = gk20a_fifo_set_timeslice, .default_timeslice_us = gk20a_fifo_default_timeslice_us, .setup_userd = gk20a_fifo_setup_userd, .userd_gp_get = gk20a_fifo_userd_gp_get, diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index a09d8912..d2136466 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -450,7 +450,6 @@ static const struct gpu_ops gv100_ops = { .alloc_inst = gk20a_fifo_alloc_inst, .free_inst = gk20a_fifo_free_inst, .setup_ramfc = channel_gv11b_setup_ramfc, - .channel_set_timeslice = gk20a_fifo_set_timeslice, .default_timeslice_us = gk20a_fifo_default_timeslice_us, .setup_userd = gk20a_fifo_setup_userd, .userd_gp_get = gv11b_userd_gp_get, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 83bd7612..ff26f694 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -474,7 +474,6 @@ static const struct gpu_ops gv11b_ops = { .alloc_inst = gk20a_fifo_alloc_inst, .free_inst = gk20a_fifo_free_inst, .setup_ramfc = channel_gv11b_setup_ramfc, - .channel_set_timeslice = gk20a_fifo_set_timeslice, .default_timeslice_us = gk20a_fifo_default_timeslice_us, .setup_userd = gk20a_fifo_setup_userd, .userd_gp_get = gv11b_userd_gp_get, -- cgit v1.2.2