From 7d16f7e52c0f8ce8604e992a617a3f98545fcf07 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Tue, 23 May 2017 18:01:43 +0530 Subject: gpu: nvgpu: use fuse APIs from Remove includes and include header to remove direct dependency on platform specific header Use specific APIs like below to read/write fuses nvgpu_tegra_fuse_write_bypass() nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable() Remove old code which was compiled for kernel versions less than 4.4 since we support only k4.4 and greater versions now Jira NVGPU-75 Change-Id: Iddd8e1a8da7effbce2aff217e8e25f7de04962d6 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1497518 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani --- drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 5 ----- drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 4 +--- drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 19 +++++++++---------- drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 8 -------- drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 5 ++--- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 13 ++++++------- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 5 ++--- drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c | 3 --- 8 files changed, 20 insertions(+), 42 deletions(-) (limited to 'drivers/gpu/nvgpu') diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 55d6f72c..4a1609d6 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h @@ -30,11 +30,6 @@ struct nvgpu_firmware; #define ZBC_MASK(i) (~(~(0) << ((i)+1)) & 0xfffe) -/*Fuse defines*/ -#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) -#define FUSE_GCPLEX_CONFIG_FUSE_0 0x2C8 -#endif - bool gk20a_pmu_is_interrupted(struct nvgpu_pmu *pmu); void gk20a_pmu_isr(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index ceeb457a..8dfc5636 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c @@ -240,8 +240,6 @@ found_match: /* GPCPLL NA/DVFS mode methods */ -#define FUSE_RESERVED_CALIB 0x204 - static inline int fuse_get_gpcpll_adc_rev(u32 val) { return (val >> 30) & 0x3; @@ -264,7 +262,7 @@ static int nvgpu_fuse_calib_gpcpll_get_adc(int *slope_uv, int *intercept_uv) u32 val; int ret; - ret = nvgpu_tegra_fuse_read(FUSE_RESERVED_CALIB, &val); + ret = nvgpu_tegra_fuse_read_reserved_calib(&val); if (ret) return ret; diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index c6e451e1..b7fb1ac5 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c @@ -13,14 +13,13 @@ * more details. */ -#include - #include #include #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/gr_gk20a.h" @@ -548,18 +547,18 @@ static u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) static void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) { - tegra_fuse_control_write(0x1, FUSE_FUSEBYPASS_0); - tegra_fuse_control_write(0x0, FUSE_WRITE_ACCESS_SW_0); + nvgpu_tegra_fuse_write_bypass(0x1); + nvgpu_tegra_fuse_write_access_sw(0x0); if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) { - tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0); - tegra_fuse_control_write(0x1, FUSE_OPT_GPU_TPC1_DISABLE_0); + nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x0); + nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(0x1); } else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) { - tegra_fuse_control_write(0x1, FUSE_OPT_GPU_TPC0_DISABLE_0); - tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC1_DISABLE_0); + nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x1); + nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(0x0); } else { - tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0); - tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC1_DISABLE_0); + nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x0); + nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(0x0); } } diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index b94259c5..e7dd091a 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h @@ -28,14 +28,6 @@ enum { MAXWELL_CHANNEL_GPFIFO_A= 0xB06F, }; -#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) -#define tegra_fuse_control_write tegra_fuse_writel -#define FUSE_FUSEBYPASS_0 0x24 -#define FUSE_WRITE_ACCESS_SW_0 0x30 -#define FUSE_OPT_GPU_TPC0_DISABLE_0 0x30C -#define FUSE_OPT_GPU_TPC1_DISABLE_0 0x33C -#endif - #define NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc #define NVB197_SET_CIRCULAR_BUFFER_SIZE 0x1280 #define NVB197_SET_SHADER_EXCEPTIONS 0x1528 diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index d501163f..5609a8cc 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c @@ -13,10 +13,9 @@ * more details. */ -#include - #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/pmu_gk20a.h" @@ -269,7 +268,7 @@ static void pmu_dump_security_fuses_gm20b(struct gk20a *g) gk20a_readl(g, fuse_opt_sec_debug_en_r())); nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", gk20a_readl(g, fuse_opt_priv_sec_en_r())); - tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, &val); + nvgpu_tegra_fuse_read_gcplex_config_fuse(&val); nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", val); } diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 9a30ad7c..3bddef4c 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -13,8 +13,6 @@ * more details. */ -#include - #include #include @@ -24,6 +22,7 @@ #include #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/gr_gk20a.h" @@ -1571,15 +1570,15 @@ static void gr_gp10b_init_cyclestats(struct gk20a *g) static void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) { - tegra_fuse_control_write(0x1, FUSE_FUSEBYPASS_0); - tegra_fuse_control_write(0x0, FUSE_WRITE_ACCESS_SW_0); + nvgpu_tegra_fuse_write_bypass(0x1); + nvgpu_tegra_fuse_write_access_sw(0x0); if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) - tegra_fuse_control_write(0x2, FUSE_OPT_GPU_TPC0_DISABLE_0); + nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x2); else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) - tegra_fuse_control_write(0x1, FUSE_OPT_GPU_TPC0_DISABLE_0); + nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x1); else - tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0); + nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x0); } static void gr_gp10b_get_access_map(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index cd6bf97a..2222cc17 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -13,10 +13,9 @@ * more details. */ -#include - #include #include +#include #include "gk20a/gk20a.h" #include "gk20a/pmu_gk20a.h" @@ -383,7 +382,7 @@ static void pmu_dump_security_fuses_gp10b(struct gk20a *g) gk20a_readl(g, fuse_opt_sec_debug_en_r())); nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", gk20a_readl(g, fuse_opt_priv_sec_en_r())); - tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, &val); + nvgpu_tegra_fuse_read_gcplex_config_fuse(&val); nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", val); } diff --git a/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c b/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c index f55ea6d2..3d5ea698 100644 --- a/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c +++ b/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c @@ -32,9 +32,6 @@ #if defined(CONFIG_COMMON_CLK) #include #endif -#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) -#include -#endif #ifdef CONFIG_TEGRA_BWMGR #include #endif -- cgit v1.2.2