From 7a033af6602258b2f2c738a7836d17562b17d8b8 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Fri, 28 Sep 2018 14:06:15 +0530 Subject: gpu: nvgpu: remove VPR HALs from dGPUs gops.fb.dump_vpr_wpr_info() accesses both VPR and WPR registers. Split this into two different HALs gops.fb.dump_vpr_info() and gops.fb.dump_wpr_info() Also unset HALs accessing VPR registers on dGPUs We don't support VPR on dGPUs Remove fb_mmu_vpr_info_r() register and all its accessors from dGPU headers Bug 2173122 Change-Id: I5b2712f8c5389e422a84c375a7e836add48bfd1c Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1850947 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/common/fb/fb_gm20b.c | 11 +++-- drivers/gpu/nvgpu/common/fb/fb_gm20b.h | 3 +- drivers/gpu/nvgpu/common/fb/fb_gv100.c | 3 -- drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 7 ++- drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 3 +- drivers/gpu/nvgpu/gp106/hal_gp106.c | 5 ++- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 3 +- drivers/gpu/nvgpu/gv100/hal_gv100.c | 5 ++- drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 +- drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 3 +- .../gpu/nvgpu/include/nvgpu/hw/gp106/hw_fb_gp106.h | 16 ------- .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h | 52 ---------------------- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 3 +- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 3 +- 14 files changed, 33 insertions(+), 87 deletions(-) (limited to 'drivers/gpu/nvgpu') diff --git a/drivers/gpu/nvgpu/common/fb/fb_gm20b.c b/drivers/gpu/nvgpu/common/fb/fb_gm20b.c index bf509caf..f62bf9df 100644 --- a/drivers/gpu/nvgpu/common/fb/fb_gm20b.c +++ b/drivers/gpu/nvgpu/common/fb/fb_gm20b.c @@ -206,11 +206,11 @@ u32 gm20b_fb_compression_align_mask(struct gk20a *g) return SZ_64K - 1; } -void gm20b_fb_dump_vpr_wpr_info(struct gk20a *g) +void gm20b_fb_dump_vpr_info(struct gk20a *g) { u32 val; - /* print vpr and wpr info */ + /* print vpr info */ val = gk20a_readl(g, fb_mmu_vpr_info_r()); val &= ~0x3; val |= fb_mmu_vpr_info_index_addr_lo_v(); @@ -220,7 +220,13 @@ void gm20b_fb_dump_vpr_wpr_info(struct gk20a *g) gk20a_readl(g, fb_mmu_vpr_info_r()), gk20a_readl(g, fb_mmu_vpr_info_r()), gk20a_readl(g, fb_mmu_vpr_info_r())); +} +void gm20b_fb_dump_wpr_info(struct gk20a *g) +{ + u32 val; + + /* print wpr info */ val = gk20a_readl(g, fb_mmu_wpr_info_r()); val &= ~0xf; val |= (fb_mmu_wpr_info_index_allow_read_v()); @@ -232,7 +238,6 @@ void gm20b_fb_dump_vpr_wpr_info(struct gk20a *g) gk20a_readl(g, fb_mmu_wpr_info_r()), gk20a_readl(g, fb_mmu_wpr_info_r()), gk20a_readl(g, fb_mmu_wpr_info_r())); - } static int gm20b_fb_vpr_info_fetch_wait(struct gk20a *g, diff --git a/drivers/gpu/nvgpu/common/fb/fb_gm20b.h b/drivers/gpu/nvgpu/common/fb/fb_gm20b.h index cb5b5d9a..d69f8618 100644 --- a/drivers/gpu/nvgpu/common/fb/fb_gm20b.h +++ b/drivers/gpu/nvgpu/common/fb/fb_gm20b.h @@ -43,7 +43,8 @@ u32 gm20b_fb_mmu_debug_rd(struct gk20a *g); unsigned int gm20b_fb_compression_page_size(struct gk20a *g); unsigned int gm20b_fb_compressible_page_size(struct gk20a *g); u32 gm20b_fb_compression_align_mask(struct gk20a *g); -void gm20b_fb_dump_vpr_wpr_info(struct gk20a *g); +void gm20b_fb_dump_vpr_info(struct gk20a *g); +void gm20b_fb_dump_wpr_info(struct gk20a *g); void gm20b_fb_read_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf); int gm20b_fb_vpr_info_fetch(struct gk20a *g); bool gm20b_fb_debug_mode_enabled(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/common/fb/fb_gv100.c b/drivers/gpu/nvgpu/common/fb/fb_gv100.c index 1088ca90..193cf2f0 100644 --- a/drivers/gpu/nvgpu/common/fb/fb_gv100.c +++ b/drivers/gpu/nvgpu/common/fb/fb_gv100.c @@ -141,9 +141,6 @@ int gv100_fb_memory_unlock(struct gk20a *g) nvgpu_log_fn(g, " "); - nvgpu_log_info(g, "fb_mmu_vpr_info = 0x%08x", - gk20a_readl(g, fb_mmu_vpr_info_r())); - /* * mem_unlock.bin should be written to install * traps even if VPR isn’t actually supported diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index b642075e..644531f1 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c @@ -468,8 +468,11 @@ int gk20a_mm_fb_flush(struct gk20a *g) } while (!nvgpu_timeout_expired(&timeout)); if (nvgpu_timeout_peek_expired(&timeout)) { - if (g->ops.fb.dump_vpr_wpr_info) { - g->ops.fb.dump_vpr_wpr_info(g); + if (g->ops.fb.dump_vpr_info) { + g->ops.fb.dump_vpr_info(g); + } + if (g->ops.fb.dump_wpr_info) { + g->ops.fb.dump_wpr_info(g); } ret = -EBUSY; } diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index e4f1984a..7eaf6bff 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -343,7 +343,8 @@ static const struct gpu_ops gm20b_ops = { .compressible_page_size = gm20b_fb_compressible_page_size, .compression_align_mask = gm20b_fb_compression_align_mask, .vpr_info_fetch = gm20b_fb_vpr_info_fetch, - .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, + .dump_vpr_info = gm20b_fb_dump_vpr_info, + .dump_wpr_info = gm20b_fb_dump_wpr_info, .read_wpr_info = gm20b_fb_read_wpr_info, .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, .set_debug_mode = gm20b_fb_set_debug_mode, diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index c1ec87eb..86892d23 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -418,8 +418,9 @@ static const struct gpu_ops gp106_ops = { .compression_page_size = gp10b_fb_compression_page_size, .compressible_page_size = gp10b_fb_compressible_page_size, .compression_align_mask = gm20b_fb_compression_align_mask, - .vpr_info_fetch = gm20b_fb_vpr_info_fetch, - .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, + .vpr_info_fetch = NULL, + .dump_vpr_info = NULL, + .dump_wpr_info = gm20b_fb_dump_wpr_info, .read_wpr_info = gm20b_fb_read_wpr_info, .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, .set_debug_mode = gm20b_fb_set_debug_mode, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 2c6a57d4..85051c11 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -380,7 +380,8 @@ static const struct gpu_ops gp10b_ops = { .compressible_page_size = gp10b_fb_compressible_page_size, .compression_align_mask = gm20b_fb_compression_align_mask, .vpr_info_fetch = gm20b_fb_vpr_info_fetch, - .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, + .dump_vpr_info = gm20b_fb_dump_vpr_info, + .dump_wpr_info = gm20b_fb_dump_wpr_info, .read_wpr_info = gm20b_fb_read_wpr_info, .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, .set_debug_mode = gm20b_fb_set_debug_mode, diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index a4b8e836..be5341b1 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c @@ -480,8 +480,9 @@ static const struct gpu_ops gv100_ops = { .compression_page_size = gp10b_fb_compression_page_size, .compressible_page_size = gp10b_fb_compressible_page_size, .compression_align_mask = gm20b_fb_compression_align_mask, - .vpr_info_fetch = gm20b_fb_vpr_info_fetch, - .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, + .vpr_info_fetch = NULL, + .dump_vpr_info = NULL, + .dump_wpr_info = gm20b_fb_dump_wpr_info, .read_wpr_info = gm20b_fb_read_wpr_info, .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, .set_debug_mode = gm20b_fb_set_debug_mode, diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 2711ea97..468abdd1 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -444,7 +444,8 @@ static const struct gpu_ops gv11b_ops = { .compressible_page_size = gp10b_fb_compressible_page_size, .compression_align_mask = gm20b_fb_compression_align_mask, .vpr_info_fetch = gm20b_fb_vpr_info_fetch, - .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, + .dump_vpr_info = gm20b_fb_dump_vpr_info, + .dump_wpr_info = gm20b_fb_dump_wpr_info, .read_wpr_info = gm20b_fb_read_wpr_info, .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, .set_debug_mode = gm20b_fb_set_debug_mode, diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index bb46d85c..e1b44b52 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h @@ -549,7 +549,8 @@ struct gpu_ops { */ u32 (*compression_align_mask)(struct gk20a *g); - void (*dump_vpr_wpr_info)(struct gk20a *g); + void (*dump_vpr_info)(struct gk20a *g); + void (*dump_wpr_info)(struct gk20a *g); int (*vpr_info_fetch)(struct gk20a *g); void (*read_wpr_info)(struct gk20a *g, struct wpr_carveout_info *inf); diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fb_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fb_gp106.h index df60beca..1c2a1ac6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fb_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fb_gp106.h @@ -448,22 +448,6 @@ static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void) { return 0x0U; } -static inline u32 fb_mmu_vpr_info_r(void) -{ - return 0x00100cd0U; -} -static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 fb_mmu_vpr_info_fetch_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_vpr_info_fetch_true_v(void) -{ - return 0x00000001U; -} static inline u32 fb_mmu_priv_level_mask_r(void) { return 0x00100cdcU; diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h index 80ff5dc2..66727b94 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h @@ -680,58 +680,6 @@ static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) { return 0x00000000U; } -static inline u32 fb_mmu_vpr_info_r(void) -{ - return 0x00100cd0U; -} -static inline u32 fb_mmu_vpr_info_index_f(u32 v) -{ - return (v & 0x3U) << 0U; -} -static inline u32 fb_mmu_vpr_info_index_v(u32 r) -{ - return (r >> 0U) & 0x3U; -} -static inline u32 fb_mmu_vpr_info_index_m(void) -{ - return 0x3U << 0U; -} -static inline u32 fb_mmu_vpr_info_index_addr_lo_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_vpr_info_index_addr_hi_v(void) -{ - return 0x00000001U; -} -static inline u32 fb_mmu_vpr_info_index_cya_lo_v(void) -{ - return 0x00000002U; -} -static inline u32 fb_mmu_vpr_info_index_cya_hi_v(void) -{ - return 0x00000003U; -} -static inline u32 fb_mmu_vpr_info_cya_lo_in_use_m(void) -{ - return 0x1U << 4U; -} -static inline u32 fb_mmu_vpr_info_fetch_f(u32 v) -{ - return (v & 0x1U) << 2U; -} -static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) -{ - return (r >> 2U) & 0x1U; -} -static inline u32 fb_mmu_vpr_info_fetch_false_v(void) -{ - return 0x00000000U; -} -static inline u32 fb_mmu_vpr_info_fetch_true_v(void) -{ - return 0x00000001U; -} static inline u32 fb_niso_cfg1_r(void) { return 0x00100c14U; diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index e23595a0..eae0ba9e 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c @@ -244,7 +244,8 @@ static const struct gpu_ops vgpu_gp10b_ops = { .compressible_page_size = gp10b_fb_compressible_page_size, .compression_align_mask = gm20b_fb_compression_align_mask, .vpr_info_fetch = NULL, - .dump_vpr_wpr_info = NULL, + .dump_vpr_info = NULL, + .dump_wpr_info = NULL, .read_wpr_info = NULL, .is_debug_mode_enabled = NULL, .set_debug_mode = vgpu_mm_mmu_set_debug_mode, diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 497c904b..de006b1e 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -285,7 +285,8 @@ static const struct gpu_ops vgpu_gv11b_ops = { .compressible_page_size = gp10b_fb_compressible_page_size, .compression_align_mask = gm20b_fb_compression_align_mask, .vpr_info_fetch = NULL, - .dump_vpr_wpr_info = NULL, + .dump_vpr_info = NULL, + .dump_wpr_info = NULL, .read_wpr_info = NULL, .is_debug_mode_enabled = NULL, .set_debug_mode = vgpu_mm_mmu_set_debug_mode, -- cgit v1.2.2