From 7252af5389f8df8c77dd68dba0e3e73f04c433e5 Mon Sep 17 00:00:00 2001 From: Alex Frid Date: Wed, 13 Aug 2014 20:37:06 -0700 Subject: gpu: nvgpu: Disable GM20b GPCPLL SYNC mode Disabled GPCPLL SYNC mode after GM20b is switched to bypass clock when powering down GPU. Bug 1450787 Change-Id: Ifaec2c562e51c0ae1328b7505faafd19607a77f2 Signed-off-by: Alex Frid Reviewed-on: http://git-master/r/456504 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bo Yan --- drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/gpu/nvgpu') diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index 78f36692..e4e51220 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c @@ -493,6 +493,12 @@ static int clk_disable_gpcpll(struct gk20a *g, int allow_slide) trim_sys_sel_vco_gpc2clk_out_bypass_f()); gk20a_writel(g, trim_sys_sel_vco_r(), cfg); + /* clear SYNC_MODE before disabling PLL */ + cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); + cfg = set_field(cfg, trim_sys_gpcpll_cfg_sync_mode_m(), + trim_sys_gpcpll_cfg_sync_mode_disable_f()); + gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg); + /* disable PLL */ cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); cfg = set_field(cfg, trim_sys_gpcpll_cfg_enable_m(), -- cgit v1.2.2