From 69222f2de6cf9a29ee5999d9802d806b6966a7e1 Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Mon, 27 Mar 2017 12:26:32 -0700 Subject: gpu: nvgpu: add fifo ops for handling pbdma_intr_1 This is needed to handle new pbmda intr_1 in t19x JIRA GPUT19X-47 Change-Id: If75de0b57f3f18420aff07ee99feaad67ac63752 Signed-off-by: Seema Khowala Reviewed-on: https://git-master/r/1329373 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 25 ++++++++++++++++++++----- drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 2 ++ drivers/gpu/nvgpu/gk20a/gk20a.h | 3 +++ drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 1 + 4 files changed, 26 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/nvgpu') diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 37e19ef8..69a3e706 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c @@ -2391,6 +2391,23 @@ unsigned int gk20a_fifo_handle_pbdma_intr_0(struct gk20a *g, u32 pbdma_id, return rc_type; } +unsigned int gk20a_fifo_handle_pbdma_intr_1(struct gk20a *g, + u32 pbdma_id, u32 pbdma_intr_1, + u32 *handled, u32 *error_notifier) +{ + unsigned int rc_type = RC_TYPE_PBDMA_FAULT; + + /* + * all of the interrupts in _intr_1 are "host copy engine" + * related, which is not supported. For now just make them + * channel fatal. + */ + nvgpu_err(g, "hce err: pbdma_intr_1(%d):0x%08x", + pbdma_id, pbdma_intr_1); + *handled |= pbdma_intr_1; + + return rc_type; +} static u32 gk20a_fifo_handle_pbdma_intr(struct gk20a *g, struct fifo_gk20a *f, u32 pbdma_id) @@ -2413,12 +2430,9 @@ static u32 gk20a_fifo_handle_pbdma_intr(struct gk20a *g, gk20a_writel(g, pbdma_intr_0_r(pbdma_id), pbdma_intr_0); } - /* all intrs in _intr_1 are "host copy engine" related, - * which gk20a doesn't have. for now just make them channel fatal. */ if (pbdma_intr_1) { - nvgpu_err(g, "channel hce error: pbdma_intr_1(%d): 0x%08x", - pbdma_id, pbdma_intr_1); - rc_type = RC_TYPE_PBDMA_FAULT; + rc_type = g->ops.fifo.handle_pbdma_intr_1(g, pbdma_id, + pbdma_intr_1, &handled, &error_notifier); gk20a_writel(g, pbdma_intr_1_r(pbdma_id), pbdma_intr_1); } @@ -4116,6 +4130,7 @@ void gk20a_init_fifo(struct gpu_ops *gops) gops->fifo.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg; gops->fifo.handle_sched_error = gk20a_fifo_handle_sched_error; gops->fifo.handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0; + gops->fifo.handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1; #ifdef CONFIG_TEGRA_GK20A_NVHOST gops->fifo.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf; gops->fifo.free_syncpt_buf = gk20a_fifo_free_syncpt_buf; diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index 1566302f..7e919346 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h @@ -390,6 +390,8 @@ void gk20a_fifo_reset_pbdma_method(struct gk20a *g, int pbdma_id, int pbdma_method_index); unsigned int gk20a_fifo_handle_pbdma_intr_0(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_0, u32 *handled, u32 *error_notifier); +unsigned int gk20a_fifo_handle_pbdma_intr_1(struct gk20a *g, u32 pbdma_id, + u32 pbdma_intr_1, u32 *handled, u32 *error_notifier); u32 gk20a_fifo_default_timeslice_us(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index ffce1c5e..61d2dd84 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -492,6 +492,9 @@ struct gpu_ops { unsigned int (*handle_pbdma_intr_0)(struct gk20a *g, u32 pbdma_id, u32 pbdma_intr_0, u32 *handled, u32 *error_notifier); + unsigned int (*handle_pbdma_intr_1)(struct gk20a *g, + u32 pbdma_id, u32 pbdma_intr_1, + u32 *handled, u32 *error_notifier); #ifdef CONFIG_TEGRA_GK20A_NVHOST int (*alloc_syncpt_buf)(struct channel_gk20a *c, u32 syncpt_id, struct nvgpu_mem *syncpt_buf); diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index df3015da..efa0c589 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c @@ -231,6 +231,7 @@ void gm20b_init_fifo(struct gpu_ops *gops) gops->fifo.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg; gops->fifo.handle_sched_error = gk20a_fifo_handle_sched_error; gops->fifo.handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0; + gops->fifo.handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1; #ifdef CONFIG_TEGRA_GK20A_NVHOST gops->fifo.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf; gops->fifo.free_syncpt_buf = gk20a_fifo_free_syncpt_buf; -- cgit v1.2.2