From 5477d0f4c226847fe030ad00425e00206118b0d6 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 8 Dec 2014 14:07:39 +0200 Subject: gpu: nvgpu: Generic mem_desc & allocation Make mem_desc a generic container for buffers. Add functions for allocating and mapping buffers to an address space which store their data in mem_desc. Change-Id: I031643442c6fd41f5e7222fe9b7bfcaf9b784db5 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/660908 GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu --- drivers/gpu/nvgpu/gk20a/channel_gk20a.h | 1 - drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 4 +-- drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 50 +++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gk20a/mm_gk20a.h | 22 +++++++-------- 4 files changed, 62 insertions(+), 15 deletions(-) (limited to 'drivers/gpu/nvgpu') diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h index 263ca291..c60afb97 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h @@ -59,7 +59,6 @@ struct fence { /* contexts associated with a channel */ struct channel_ctx_gk20a { struct gr_ctx_desc *gr_ctx; - struct pm_ctx_desc pm_ctx; struct patch_desc patch_ctx; struct zcull_ctx_desc zcull_ctx; u64 global_ctx_buffer_va[NR_GLOBAL_CTX_BUF_VA]; diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index f2b0c83c..867e775a 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -1618,11 +1618,9 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g, virt_addr_hi); /* no user for client managed performance counter ctx */ - ch_ctx->pm_ctx.ctx_sw_mode = - ctxsw_prog_main_image_pm_mode_no_ctxsw_f(); data = gk20a_mem_rd32(ctx_ptr + ctxsw_prog_main_image_pm_o(), 0); data = data & ~ctxsw_prog_main_image_pm_mode_m(); - data |= ch_ctx->pm_ctx.ctx_sw_mode; + data |= ctxsw_prog_main_image_pm_mode_no_ctxsw_f(); gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_pm_o(), 0, data); diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index 9fdbf2b7..5e925d65 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c @@ -1546,6 +1546,56 @@ u64 gk20a_gmmu_map(struct vm_gk20a *vm, return vaddr; } +int gk20a_gmmu_alloc_map(struct vm_gk20a *vm, + size_t size, struct mem_desc *mem) +{ + struct gk20a *g = vm->mm->g; + struct device *d = dev_from_gk20a(g); + int err; + struct sg_table *sgt; + + mem->cpu_va = dma_alloc_coherent(d, size, &mem->iova, GFP_KERNEL); + if (!mem->cpu_va) + return -ENOMEM; + + err = gk20a_get_sgtable(d, &sgt, mem->cpu_va, mem->iova, size); + if (err) + goto fail_free; + + mem->gpu_va = gk20a_gmmu_map(vm, &sgt, size, 0, gk20a_mem_flag_none); + gk20a_free_sgtable(&sgt); + if (!mem->gpu_va) { + err = -ENOMEM; + goto fail_free; + } + + mem->size = size; + + return 0; + +fail_free: + dma_free_coherent(d, size, mem->cpu_va, mem->iova); + mem->cpu_va = NULL; + mem->iova = 0; + + return err; +} + +void gk20a_gmmu_unmap_free(struct vm_gk20a *vm, struct mem_desc *mem) +{ + struct gk20a *g = vm->mm->g; + struct device *d = dev_from_gk20a(g); + + if (mem->gpu_va) + gk20a_gmmu_unmap(vm, mem->gpu_va, mem->size, gk20a_mem_flag_none); + mem->gpu_va = 0; + + if (mem->cpu_va) + dma_free_coherent(d, mem->size, mem->cpu_va, mem->iova); + mem->cpu_va = NULL; + mem->iova = 0; +} + dma_addr_t gk20a_mm_gpuva_to_iova_base(struct vm_gk20a *vm, u64 gpu_vaddr) { struct mapped_buffer_node *buffer; diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h index d6cb74de..041c7edf 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h @@ -42,9 +42,10 @@ } while (0) struct mem_desc { - struct dma_buf *ref; - struct sg_table *sgt; - u32 size; + void *cpu_va; + dma_addr_t iova; + size_t size; + u64 gpu_va; }; struct mem_desc_sub { @@ -123,14 +124,6 @@ struct priv_cmd_queue_mem_desc { }; struct zcull_ctx_desc { - struct mem_desc mem; - u64 gpu_va; - u32 ctx_attr; - u32 ctx_sw_mode; -}; - -struct pm_ctx_desc { - struct mem_desc mem; u64 gpu_va; u32 ctx_attr; u32 ctx_sw_mode; @@ -427,6 +420,13 @@ u64 gk20a_gmmu_map(struct vm_gk20a *vm, u32 flags, int rw_flag); +int gk20a_gmmu_alloc_map(struct vm_gk20a *vm, + size_t size, + struct mem_desc *mem); + +void gk20a_gmmu_unmap_free(struct vm_gk20a *vm, + struct mem_desc *mem); + u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm, u64 map_offset, struct sg_table *sgt, -- cgit v1.2.2