From 526cb049984fdc9b37af4d39c41bfe00db3b6898 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 17 Mar 2017 10:15:32 -0700 Subject: gpu: nvgpu: Move sim support to its own file Simulator support is intermixed with the rest of code in gk20a.c. Move that code away from gk20a.c to an own file. Change-Id: Idd3c8795cec5eadc6e49811b5b8ff0592c49a7d2 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1323230 Reviewed-by: Bharat Nihalani Tested-by: Bharat Nihalani --- drivers/gpu/nvgpu/Makefile.nvgpu | 1 + drivers/gpu/nvgpu/gk20a/gk20a.c | 327 +-------------------------- drivers/gpu/nvgpu/gk20a/gk20a.h | 3 + drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c | 1 + drivers/gpu/nvgpu/gk20a/sim_gk20a.c | 345 +++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gk20a/sim_gk20a.h | 24 +- 6 files changed, 355 insertions(+), 346 deletions(-) create mode 100644 drivers/gpu/nvgpu/gk20a/sim_gk20a.c (limited to 'drivers/gpu/nvgpu') diff --git a/drivers/gpu/nvgpu/Makefile.nvgpu b/drivers/gpu/nvgpu/Makefile.nvgpu index bcf9bdda..3852e728 100644 --- a/drivers/gpu/nvgpu/Makefile.nvgpu +++ b/drivers/gpu/nvgpu/Makefile.nvgpu @@ -65,6 +65,7 @@ nvgpu-y := \ gk20a/ctxsw_trace_gk20a.o \ gk20a/fecs_trace_gk20a.o \ gk20a/mc_gk20a.o \ + gk20a/sim_gk20a.o \ gm20b/hal_gm20b.o \ gm20b/ltc_gm20b.o \ gm20b/ce2_gm20b.o \ diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index 1d6fb0e9..0b53bffc 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c @@ -18,7 +18,6 @@ #include #include -#include #include #include #include @@ -73,7 +72,6 @@ #include #include #include -#include #include #include #include @@ -276,16 +274,6 @@ void __nvgpu_check_gpu_state(struct gk20a *g) } } -static inline void sim_writel(struct gk20a *g, u32 r, u32 v) -{ - writel(v, g->sim.regs+r); -} - -static inline u32 sim_readl(struct gk20a *g, u32 r) -{ - return readl(g->sim.regs+r); -} - /* * Locks out the driver from accessing GPU registers. This prevents access to * thse registers after the GPU has been clock or power gated. This should help @@ -317,69 +305,7 @@ void __gk20a_warn_on_no_regs(void) WARN_ONCE(1, "Attempted access to GPU regs after unmapping!"); } -static void kunmap_and_free_iopage(void **kvaddr, struct page **page) -{ - if (*kvaddr) { - kunmap(*kvaddr); - *kvaddr = NULL; - } - if (*page) { - __free_page(*page); - *page = NULL; - } -} - -static void gk20a_free_sim_support(struct gk20a *g) -{ - /* free sim mappings, bfrs */ - kunmap_and_free_iopage(&g->sim.send_bfr.kvaddr, - &g->sim.send_bfr.page); - - kunmap_and_free_iopage(&g->sim.recv_bfr.kvaddr, - &g->sim.recv_bfr.page); - - kunmap_and_free_iopage(&g->sim.msg_bfr.kvaddr, - &g->sim.msg_bfr.page); -} - -static void gk20a_remove_sim_support(struct sim_gk20a *s) -{ - struct gk20a *g = s->g; - if (g->sim.regs) - sim_writel(g, sim_config_r(), sim_config_mode_disabled_v()); - gk20a_free_sim_support(g); -} - -static int alloc_and_kmap_iopage(struct device *d, - void **kvaddr, - u64 *phys, - struct page **page) -{ - int err = 0; - *page = alloc_page(GFP_KERNEL); - - if (!*page) { - err = -ENOMEM; - dev_err(d, "couldn't allocate io page\n"); - goto fail; - } - - *kvaddr = kmap(*page); - if (!*kvaddr) { - err = -ENOMEM; - dev_err(d, "couldn't kmap io page\n"); - goto fail; - } - *phys = page_to_phys(*page); - return 0; - - fail: - kunmap_and_free_iopage(kvaddr, page); - return err; - -} - -static void __iomem *gk20a_ioremap_resource(struct platform_device *dev, int i, +void __iomem *gk20a_ioremap_resource(struct platform_device *dev, int i, struct resource **out) { struct resource *r = platform_get_resource(dev, IORESOURCE_MEM, i); @@ -390,257 +316,6 @@ static void __iomem *gk20a_ioremap_resource(struct platform_device *dev, int i, return devm_ioremap_resource(&dev->dev, r); } -/* TBD: strip from released */ -static int gk20a_init_sim_support(struct platform_device *pdev) -{ - int err = 0; - struct device *dev = &pdev->dev; - struct gk20a *g = get_gk20a(dev); - u64 phys; - - g->sim.g = g; - g->sim.regs = gk20a_ioremap_resource(pdev, GK20A_SIM_IORESOURCE_MEM, - &g->sim.reg_mem); - if (IS_ERR(g->sim.regs)) { - dev_err(dev, "failed to remap gk20a sim regs\n"); - err = PTR_ERR(g->sim.regs); - goto fail; - } - - /* allocate sim event/msg buffers */ - err = alloc_and_kmap_iopage(dev, &g->sim.send_bfr.kvaddr, - &g->sim.send_bfr.phys, - &g->sim.send_bfr.page); - - err = err || alloc_and_kmap_iopage(dev, &g->sim.recv_bfr.kvaddr, - &g->sim.recv_bfr.phys, - &g->sim.recv_bfr.page); - - err = err || alloc_and_kmap_iopage(dev, &g->sim.msg_bfr.kvaddr, - &g->sim.msg_bfr.phys, - &g->sim.msg_bfr.page); - - if (!(g->sim.send_bfr.kvaddr && g->sim.recv_bfr.kvaddr && - g->sim.msg_bfr.kvaddr)) { - dev_err(dev, "couldn't allocate all sim buffers\n"); - goto fail; - } - - /*mark send ring invalid*/ - sim_writel(g, sim_send_ring_r(), sim_send_ring_status_invalid_f()); - - /*read get pointer and make equal to put*/ - g->sim.send_ring_put = sim_readl(g, sim_send_get_r()); - sim_writel(g, sim_send_put_r(), g->sim.send_ring_put); - - /*write send ring address and make it valid*/ - phys = g->sim.send_bfr.phys; - sim_writel(g, sim_send_ring_hi_r(), - sim_send_ring_hi_addr_f(u64_hi32(phys))); - sim_writel(g, sim_send_ring_r(), - sim_send_ring_status_valid_f() | - sim_send_ring_target_phys_pci_coherent_f() | - sim_send_ring_size_4kb_f() | - sim_send_ring_addr_lo_f(phys >> PAGE_SHIFT)); - - /*repeat for recv ring (but swap put,get as roles are opposite) */ - sim_writel(g, sim_recv_ring_r(), sim_recv_ring_status_invalid_f()); - - /*read put pointer and make equal to get*/ - g->sim.recv_ring_get = sim_readl(g, sim_recv_put_r()); - sim_writel(g, sim_recv_get_r(), g->sim.recv_ring_get); - - /*write send ring address and make it valid*/ - phys = g->sim.recv_bfr.phys; - sim_writel(g, sim_recv_ring_hi_r(), - sim_recv_ring_hi_addr_f(u64_hi32(phys))); - sim_writel(g, sim_recv_ring_r(), - sim_recv_ring_status_valid_f() | - sim_recv_ring_target_phys_pci_coherent_f() | - sim_recv_ring_size_4kb_f() | - sim_recv_ring_addr_lo_f(phys >> PAGE_SHIFT)); - - g->sim.remove_support = gk20a_remove_sim_support; - return 0; - - fail: - gk20a_free_sim_support(g); - return err; -} - -static inline u32 sim_msg_header_size(void) -{ - return 24;/*TBD: fix the header to gt this from NV_VGPU_MSG_HEADER*/ -} - -static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset) -{ - return (u32 *)(g->sim.msg_bfr.kvaddr + byte_offset); -} - -static inline u32 *sim_msg_hdr(struct gk20a *g, u32 byte_offset) -{ - return sim_msg_bfr(g, byte_offset); /*starts at 0*/ -} - -static inline u32 *sim_msg_param(struct gk20a *g, u32 byte_offset) -{ - /*starts after msg header/cmn*/ - return sim_msg_bfr(g, byte_offset + sim_msg_header_size()); -} - -static inline void sim_write_hdr(struct gk20a *g, u32 func, u32 size) -{ - /*memset(g->sim.msg_bfr.kvaddr,0,min(PAGE_SIZE,size));*/ - *sim_msg_hdr(g, sim_msg_signature_r()) = sim_msg_signature_valid_v(); - *sim_msg_hdr(g, sim_msg_result_r()) = sim_msg_result_rpc_pending_v(); - *sim_msg_hdr(g, sim_msg_spare_r()) = sim_msg_spare__init_v(); - *sim_msg_hdr(g, sim_msg_function_r()) = func; - *sim_msg_hdr(g, sim_msg_length_r()) = size + sim_msg_header_size(); -} - -static inline u32 sim_escape_read_hdr_size(void) -{ - return 12; /*TBD: fix NV_VGPU_SIM_ESCAPE_READ_HEADER*/ -} - -static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset) -{ - return (u32 *)(g->sim.send_bfr.kvaddr + byte_offset); -} - -static int rpc_send_message(struct gk20a *g) -{ - /* calculations done in units of u32s */ - u32 send_base = sim_send_put_pointer_v(g->sim.send_ring_put) * 2; - u32 dma_offset = send_base + sim_dma_r()/sizeof(u32); - u32 dma_hi_offset = send_base + sim_dma_hi_r()/sizeof(u32); - - *sim_send_ring_bfr(g, dma_offset*sizeof(u32)) = - sim_dma_target_phys_pci_coherent_f() | - sim_dma_status_valid_f() | - sim_dma_size_4kb_f() | - sim_dma_addr_lo_f(g->sim.msg_bfr.phys >> PAGE_SHIFT); - - *sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) = - u64_hi32(g->sim.msg_bfr.phys); - - *sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim.sequence_base++; - - g->sim.send_ring_put = (g->sim.send_ring_put + 2 * sizeof(u32)) % - PAGE_SIZE; - - __cpuc_flush_dcache_area(g->sim.msg_bfr.kvaddr, PAGE_SIZE); - __cpuc_flush_dcache_area(g->sim.send_bfr.kvaddr, PAGE_SIZE); - __cpuc_flush_dcache_area(g->sim.recv_bfr.kvaddr, PAGE_SIZE); - - /* Update the put pointer. This will trap into the host. */ - sim_writel(g, sim_send_put_r(), g->sim.send_ring_put); - - return 0; -} - -static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset) -{ - return (u32 *)(g->sim.recv_bfr.kvaddr + byte_offset); -} - -static int rpc_recv_poll(struct gk20a *g) -{ - u64 recv_phys_addr; - - /* XXX This read is not required (?) */ - /*pVGpu->recv_ring_get = VGPU_REG_RD32(pGpu, NV_VGPU_RECV_GET);*/ - - /* Poll the recv ring get pointer in an infinite loop*/ - do { - g->sim.recv_ring_put = sim_readl(g, sim_recv_put_r()); - } while (g->sim.recv_ring_put == g->sim.recv_ring_get); - - /* process all replies */ - while (g->sim.recv_ring_put != g->sim.recv_ring_get) { - /* these are in u32 offsets*/ - u32 dma_lo_offset = - sim_recv_put_pointer_v(g->sim.recv_ring_get)*2 + 0; - u32 dma_hi_offset = dma_lo_offset + 1; - u32 recv_phys_addr_lo = sim_dma_addr_lo_v( - *sim_recv_ring_bfr(g, dma_lo_offset*4)); - u32 recv_phys_addr_hi = sim_dma_hi_addr_v( - *sim_recv_ring_bfr(g, dma_hi_offset*4)); - - recv_phys_addr = (u64)recv_phys_addr_hi << 32 | - (u64)recv_phys_addr_lo << PAGE_SHIFT; - - if (recv_phys_addr != g->sim.msg_bfr.phys) { - dev_err(dev_from_gk20a(g), "%s Error in RPC reply\n", - __func__); - return -1; - } - - /* Update GET pointer */ - g->sim.recv_ring_get = (g->sim.recv_ring_get + 2*sizeof(u32)) % - PAGE_SIZE; - - __cpuc_flush_dcache_area(g->sim.msg_bfr.kvaddr, PAGE_SIZE); - __cpuc_flush_dcache_area(g->sim.send_bfr.kvaddr, PAGE_SIZE); - __cpuc_flush_dcache_area(g->sim.recv_bfr.kvaddr, PAGE_SIZE); - - sim_writel(g, sim_recv_get_r(), g->sim.recv_ring_get); - - g->sim.recv_ring_put = sim_readl(g, sim_recv_put_r()); - } - - return 0; -} - -static int issue_rpc_and_wait(struct gk20a *g) -{ - int err; - - err = rpc_send_message(g); - if (err) { - dev_err(dev_from_gk20a(g), "%s failed rpc_send_message\n", - __func__); - return err; - } - - err = rpc_recv_poll(g); - if (err) { - dev_err(dev_from_gk20a(g), "%s failed rpc_recv_poll\n", - __func__); - return err; - } - - /* Now check if RPC really succeeded */ - if (*sim_msg_hdr(g, sim_msg_result_r()) != sim_msg_result_success_v()) { - dev_err(dev_from_gk20a(g), "%s received failed status!\n", - __func__); - return -(*sim_msg_hdr(g, sim_msg_result_r())); - } - return 0; -} - -int gk20a_sim_esc_read(struct gk20a *g, char *path, u32 index, u32 count, u32 *data) -{ - int err; - size_t pathlen = strlen(path); - u32 data_offset; - - sim_write_hdr(g, sim_msg_function_sim_escape_read_v(), - sim_escape_read_hdr_size()); - *sim_msg_param(g, 0) = index; - *sim_msg_param(g, 4) = count; - data_offset = roundup(0xc + pathlen + 1, sizeof(u32)); - *sim_msg_param(g, 8) = data_offset; - strcpy((char *)sim_msg_param(g, 0xc), path); - - err = issue_rpc_and_wait(g); - - if (!err) - memcpy(data, sim_msg_param(g, data_offset), count); - return err; -} - static irqreturn_t gk20a_intr_isr_stall(int irq, void *dev_id) { struct gk20a *g = dev_id; diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 95730b4e..c1e1b564 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -1476,4 +1476,7 @@ int gk20a_railgating_debugfs_init(struct device *dev); #endif int gk20a_secure_page_alloc(struct device *dev); +void __iomem *gk20a_ioremap_resource(struct platform_device *dev, int i, + struct resource **out); + #endif /* GK20A_H */ diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c index 70787202..34b315e6 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c +++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c @@ -20,6 +20,7 @@ */ #include "gk20a.h" +#include "sim_gk20a.h" #include "gr_ctx_gk20a.h" int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr) diff --git a/drivers/gpu/nvgpu/gk20a/sim_gk20a.c b/drivers/gpu/nvgpu/gk20a/sim_gk20a.c new file mode 100644 index 00000000..76d29ee5 --- /dev/null +++ b/drivers/gpu/nvgpu/gk20a/sim_gk20a.c @@ -0,0 +1,345 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include + +#include "gk20a.h" + +#include + +static inline void sim_writel(struct gk20a *g, u32 r, u32 v) +{ + writel(v, g->sim.regs + r); +} + +static inline u32 sim_readl(struct gk20a *g, u32 r) +{ + return readl(g->sim.regs + r); +} + +static void kunmap_and_free_iopage(void **kvaddr, struct page **page) +{ + if (*kvaddr) { + kunmap(*kvaddr); + *kvaddr = NULL; + } + if (*page) { + __free_page(*page); + *page = NULL; + } +} + +static void gk20a_free_sim_support(struct gk20a *g) +{ + /* free sim mappings, bfrs */ + kunmap_and_free_iopage(&g->sim.send_bfr.kvaddr, + &g->sim.send_bfr.page); + + kunmap_and_free_iopage(&g->sim.recv_bfr.kvaddr, + &g->sim.recv_bfr.page); + + kunmap_and_free_iopage(&g->sim.msg_bfr.kvaddr, + &g->sim.msg_bfr.page); +} + +static void gk20a_remove_sim_support(struct sim_gk20a *s) +{ + struct gk20a *g = s->g; + if (g->sim.regs) + sim_writel(g, sim_config_r(), sim_config_mode_disabled_v()); + gk20a_free_sim_support(g); +} + +static int alloc_and_kmap_iopage(struct device *d, + void **kvaddr, + u64 *phys, + struct page **page) +{ + int err = 0; + *page = alloc_page(GFP_KERNEL); + + if (!*page) { + err = -ENOMEM; + dev_err(d, "couldn't allocate io page\n"); + goto fail; + } + + *kvaddr = kmap(*page); + if (!*kvaddr) { + err = -ENOMEM; + dev_err(d, "couldn't kmap io page\n"); + goto fail; + } + *phys = page_to_phys(*page); + return 0; + + fail: + kunmap_and_free_iopage(kvaddr, page); + return err; + +} + +int gk20a_init_sim_support(struct platform_device *pdev) +{ + int err = 0; + struct device *dev = &pdev->dev; + struct gk20a *g = get_gk20a(dev); + u64 phys; + + g->sim.g = g; + g->sim.regs = gk20a_ioremap_resource(pdev, GK20A_SIM_IORESOURCE_MEM, + &g->sim.reg_mem); + if (IS_ERR(g->sim.regs)) { + dev_err(dev, "failed to remap gk20a sim regs\n"); + err = PTR_ERR(g->sim.regs); + goto fail; + } + + /* allocate sim event/msg buffers */ + err = alloc_and_kmap_iopage(dev, &g->sim.send_bfr.kvaddr, + &g->sim.send_bfr.phys, + &g->sim.send_bfr.page); + + err = err || alloc_and_kmap_iopage(dev, &g->sim.recv_bfr.kvaddr, + &g->sim.recv_bfr.phys, + &g->sim.recv_bfr.page); + + err = err || alloc_and_kmap_iopage(dev, &g->sim.msg_bfr.kvaddr, + &g->sim.msg_bfr.phys, + &g->sim.msg_bfr.page); + + if (!(g->sim.send_bfr.kvaddr && g->sim.recv_bfr.kvaddr && + g->sim.msg_bfr.kvaddr)) { + dev_err(dev, "couldn't allocate all sim buffers\n"); + goto fail; + } + + /*mark send ring invalid*/ + sim_writel(g, sim_send_ring_r(), sim_send_ring_status_invalid_f()); + + /*read get pointer and make equal to put*/ + g->sim.send_ring_put = sim_readl(g, sim_send_get_r()); + sim_writel(g, sim_send_put_r(), g->sim.send_ring_put); + + /*write send ring address and make it valid*/ + phys = g->sim.send_bfr.phys; + sim_writel(g, sim_send_ring_hi_r(), + sim_send_ring_hi_addr_f(u64_hi32(phys))); + sim_writel(g, sim_send_ring_r(), + sim_send_ring_status_valid_f() | + sim_send_ring_target_phys_pci_coherent_f() | + sim_send_ring_size_4kb_f() | + sim_send_ring_addr_lo_f(phys >> PAGE_SHIFT)); + + /*repeat for recv ring (but swap put,get as roles are opposite) */ + sim_writel(g, sim_recv_ring_r(), sim_recv_ring_status_invalid_f()); + + /*read put pointer and make equal to get*/ + g->sim.recv_ring_get = sim_readl(g, sim_recv_put_r()); + sim_writel(g, sim_recv_get_r(), g->sim.recv_ring_get); + + /*write send ring address and make it valid*/ + phys = g->sim.recv_bfr.phys; + sim_writel(g, sim_recv_ring_hi_r(), + sim_recv_ring_hi_addr_f(u64_hi32(phys))); + sim_writel(g, sim_recv_ring_r(), + sim_recv_ring_status_valid_f() | + sim_recv_ring_target_phys_pci_coherent_f() | + sim_recv_ring_size_4kb_f() | + sim_recv_ring_addr_lo_f(phys >> PAGE_SHIFT)); + + g->sim.remove_support = gk20a_remove_sim_support; + return 0; + + fail: + gk20a_free_sim_support(g); + return err; +} + +static inline u32 sim_msg_header_size(void) +{ + return 24;/*TBD: fix the header to gt this from NV_VGPU_MSG_HEADER*/ +} + +static inline u32 *sim_msg_bfr(struct gk20a *g, u32 byte_offset) +{ + return (u32 *)(g->sim.msg_bfr.kvaddr + byte_offset); +} + +static inline u32 *sim_msg_hdr(struct gk20a *g, u32 byte_offset) +{ + return sim_msg_bfr(g, byte_offset); /*starts at 0*/ +} + +static inline u32 *sim_msg_param(struct gk20a *g, u32 byte_offset) +{ + /*starts after msg header/cmn*/ + return sim_msg_bfr(g, byte_offset + sim_msg_header_size()); +} + +static inline void sim_write_hdr(struct gk20a *g, u32 func, u32 size) +{ + /*memset(g->sim.msg_bfr.kvaddr,0,min(PAGE_SIZE,size));*/ + *sim_msg_hdr(g, sim_msg_signature_r()) = sim_msg_signature_valid_v(); + *sim_msg_hdr(g, sim_msg_result_r()) = sim_msg_result_rpc_pending_v(); + *sim_msg_hdr(g, sim_msg_spare_r()) = sim_msg_spare__init_v(); + *sim_msg_hdr(g, sim_msg_function_r()) = func; + *sim_msg_hdr(g, sim_msg_length_r()) = size + sim_msg_header_size(); +} + +static inline u32 sim_escape_read_hdr_size(void) +{ + return 12; /*TBD: fix NV_VGPU_SIM_ESCAPE_READ_HEADER*/ +} + +static u32 *sim_send_ring_bfr(struct gk20a *g, u32 byte_offset) +{ + return (u32 *)(g->sim.send_bfr.kvaddr + byte_offset); +} + +static int rpc_send_message(struct gk20a *g) +{ + /* calculations done in units of u32s */ + u32 send_base = sim_send_put_pointer_v(g->sim.send_ring_put) * 2; + u32 dma_offset = send_base + sim_dma_r()/sizeof(u32); + u32 dma_hi_offset = send_base + sim_dma_hi_r()/sizeof(u32); + + *sim_send_ring_bfr(g, dma_offset*sizeof(u32)) = + sim_dma_target_phys_pci_coherent_f() | + sim_dma_status_valid_f() | + sim_dma_size_4kb_f() | + sim_dma_addr_lo_f(g->sim.msg_bfr.phys >> PAGE_SHIFT); + + *sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) = + u64_hi32(g->sim.msg_bfr.phys); + + *sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim.sequence_base++; + + g->sim.send_ring_put = (g->sim.send_ring_put + 2 * sizeof(u32)) % + PAGE_SIZE; + + __cpuc_flush_dcache_area(g->sim.msg_bfr.kvaddr, PAGE_SIZE); + __cpuc_flush_dcache_area(g->sim.send_bfr.kvaddr, PAGE_SIZE); + __cpuc_flush_dcache_area(g->sim.recv_bfr.kvaddr, PAGE_SIZE); + + /* Update the put pointer. This will trap into the host. */ + sim_writel(g, sim_send_put_r(), g->sim.send_ring_put); + + return 0; +} + +static inline u32 *sim_recv_ring_bfr(struct gk20a *g, u32 byte_offset) +{ + return (u32 *)(g->sim.recv_bfr.kvaddr + byte_offset); +} + +static int rpc_recv_poll(struct gk20a *g) +{ + u64 recv_phys_addr; + + /* XXX This read is not required (?) */ + /*pVGpu->recv_ring_get = VGPU_REG_RD32(pGpu, NV_VGPU_RECV_GET);*/ + + /* Poll the recv ring get pointer in an infinite loop*/ + do { + g->sim.recv_ring_put = sim_readl(g, sim_recv_put_r()); + } while (g->sim.recv_ring_put == g->sim.recv_ring_get); + + /* process all replies */ + while (g->sim.recv_ring_put != g->sim.recv_ring_get) { + /* these are in u32 offsets*/ + u32 dma_lo_offset = + sim_recv_put_pointer_v(g->sim.recv_ring_get)*2 + 0; + u32 dma_hi_offset = dma_lo_offset + 1; + u32 recv_phys_addr_lo = sim_dma_addr_lo_v( + *sim_recv_ring_bfr(g, dma_lo_offset*4)); + u32 recv_phys_addr_hi = sim_dma_hi_addr_v( + *sim_recv_ring_bfr(g, dma_hi_offset*4)); + + recv_phys_addr = (u64)recv_phys_addr_hi << 32 | + (u64)recv_phys_addr_lo << PAGE_SHIFT; + + if (recv_phys_addr != g->sim.msg_bfr.phys) { + dev_err(dev_from_gk20a(g), "%s Error in RPC reply\n", + __func__); + return -1; + } + + /* Update GET pointer */ + g->sim.recv_ring_get = (g->sim.recv_ring_get + 2*sizeof(u32)) % + PAGE_SIZE; + + __cpuc_flush_dcache_area(g->sim.msg_bfr.kvaddr, PAGE_SIZE); + __cpuc_flush_dcache_area(g->sim.send_bfr.kvaddr, PAGE_SIZE); + __cpuc_flush_dcache_area(g->sim.recv_bfr.kvaddr, PAGE_SIZE); + + sim_writel(g, sim_recv_get_r(), g->sim.recv_ring_get); + + g->sim.recv_ring_put = sim_readl(g, sim_recv_put_r()); + } + + return 0; +} + +static int issue_rpc_and_wait(struct gk20a *g) +{ + int err; + + err = rpc_send_message(g); + if (err) { + dev_err(dev_from_gk20a(g), "%s failed rpc_send_message\n", + __func__); + return err; + } + + err = rpc_recv_poll(g); + if (err) { + dev_err(dev_from_gk20a(g), "%s failed rpc_recv_poll\n", + __func__); + return err; + } + + /* Now check if RPC really succeeded */ + if (*sim_msg_hdr(g, sim_msg_result_r()) != sim_msg_result_success_v()) { + dev_err(dev_from_gk20a(g), "%s received failed status!\n", + __func__); + return -(*sim_msg_hdr(g, sim_msg_result_r())); + } + return 0; +} + +int gk20a_sim_esc_readl(struct gk20a *g, char *path, u32 index, u32 *data) +{ + int err; + size_t pathlen = strlen(path); + u32 data_offset; + + sim_write_hdr(g, sim_msg_function_sim_escape_read_v(), + sim_escape_read_hdr_size()); + *sim_msg_param(g, 0) = index; + *sim_msg_param(g, 4) = sizeof(u32); + data_offset = roundup(0xc + pathlen + 1, sizeof(u32)); + *sim_msg_param(g, 8) = data_offset; + strcpy((char *)sim_msg_param(g, 0xc), path); + + err = issue_rpc_and_wait(g); + + if (!err) + memcpy(data, sim_msg_param(g, data_offset), sizeof(u32)); + return err; +} diff --git a/drivers/gpu/nvgpu/gk20a/sim_gk20a.h b/drivers/gpu/nvgpu/gk20a/sim_gk20a.h index 3c21d69e..68398b34 100644 --- a/drivers/gpu/nvgpu/gk20a/sim_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/sim_gk20a.h @@ -21,8 +21,9 @@ #ifndef __SIM_GK20A_H__ #define __SIM_GK20A_H__ - struct gk20a; +struct platform_device; + struct sim_gk20a { struct gk20a *g; struct resource *reg_mem; @@ -39,24 +40,7 @@ struct sim_gk20a { void (*remove_support)(struct sim_gk20a *); }; - -int gk20a_sim_esc_read(struct gk20a *g, char *path, u32 index, - u32 count, u32 *data); - -static inline int gk20a_sim_esc_read_no_sim(struct gk20a *g, char *p, - u32 i, u32 c, u32 *d) -{ - *d = ~(u32)0; - return -1; -} - -static inline int gk20a_sim_esc_readl(struct gk20a *g, char * p, u32 i, u32 *d) -{ - if (tegra_cpu_is_asim()) - return gk20a_sim_esc_read(g, p, i, sizeof(u32), d); - - return gk20a_sim_esc_read_no_sim(g, p, i, sizeof(u32), d); -} - +int gk20a_init_sim_support(struct platform_device *pdev); +int gk20a_sim_esc_readl(struct gk20a *g, char *path, u32 index, u32 *data); #endif /*__SIM_GK20A_H__*/ -- cgit v1.2.2