From 49be5d49292c9c853f5b6ad53c32d59f866322ec Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Wed, 15 Nov 2017 11:40:54 +0530 Subject: gpu: nvgpu: gv11b: implement ecc scrubber Check the availability of ecc units by checking relevant ecc fuse and fuse overrides. During gpu boot, initialize ecc units by scrubbing individual ecc units available. ECC initialization should be done before gr initialization. Following ecc units are scrubbed: SM LRF SM L1 DATA SM L1 TAG SM CBU SM ICACHE Bug 200339497 Change-Id: I54bf8cc1fce639a9993bf80984dafc28dca0dba3 Signed-off-by: Deepak Goyal Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1612734 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/gk20a/gk20a.h | 1 + drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 5 +- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 185 ++++++++++ drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 1 + drivers/gpu/nvgpu/gv11b/gv11b.c | 120 ++++++ drivers/gpu/nvgpu/gv11b/gv11b.h | 1 + drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 + drivers/gpu/nvgpu/include/nvgpu/enabled.h | 9 + .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 410 ++++++++++++++++++++- 9 files changed, 729 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/nvgpu') diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 2ae1b758..f1dc2f03 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h @@ -436,6 +436,7 @@ struct gpu_ops { void (*init_gfxp_wfi_timeout_count)(struct gk20a *g); unsigned long (*get_max_gfxp_wfi_timeout_count) (struct gk20a *g); + void (*ecc_init_scrub_reg)(struct gk20a *g); } gr; struct { void (*init_hw)(struct gk20a *g); diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 99f85b57..ea4d1d24 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -4478,7 +4478,10 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) if (g->ops.gr.enable_gpc_exceptions) g->ops.gr.enable_gpc_exceptions(g); - /* TBD: ECC for L1/SM */ + /* enable ECC for L1/SM */ + if (g->ops.gr.ecc_init_scrub_reg) + g->ops.gr.ecc_init_scrub_reg(g); + /* TBD: enable per BE exceptions */ /* reset and enable exceptions */ diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 033d83d5..8514cc1e 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -44,6 +44,7 @@ #include "gv11b/gr_gv11b.h" #include "gv11b/mm_gv11b.h" #include "gv11b/subctx_gv11b.h" +#include "gv11b/gv11b.h" #include #include @@ -57,6 +58,10 @@ #define GFXP_WFI_TIMEOUT_COUNT_IN_USEC_DEFAULT 1000 +/* ecc scrubbing will done in 1 pri read cycle,but for safety used 10 retries */ +#define ECC_SCRUBBING_TIMEOUT_MAX 1000 +#define ECC_SCRUBBING_TIMEOUT_DEFAULT 10 + bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) { bool valid = false; @@ -3674,3 +3679,183 @@ unsigned long gr_gv11b_get_max_gfxp_wfi_timeout_count(struct gk20a *g) /* 100 msec in usec count */ return (100 * 1000UL); } + +static int gr_gv11b_ecc_scrub_is_done(struct gk20a *g, + u32 scrub_reg, u32 scrub_mask, u32 scrub_done) +{ + struct nvgpu_timeout timeout; + int status = 0; + u32 val; + + nvgpu_timeout_init(g, &timeout, + ECC_SCRUBBING_TIMEOUT_MAX / + ECC_SCRUBBING_TIMEOUT_DEFAULT, + NVGPU_TIMER_RETRY_TIMER); + do { + val = gk20a_readl(g, scrub_reg); + if ((val & scrub_mask) == scrub_done) + goto exit; + nvgpu_udelay(ECC_SCRUBBING_TIMEOUT_DEFAULT); + } while (!nvgpu_timeout_expired(&timeout)); + + if (nvgpu_timeout_peek_expired(&timeout)) + status = -ETIMEDOUT; +exit: + return status; + +} + +static int gr_gv11b_ecc_scrub_sm_lrf(struct gk20a *g) +{ + u32 scrub_mask, scrub_done; + + if (!nvgpu_is_enabled(g, NVGPU_ECC_ENABLED_SM_LRF)) { + nvgpu_log_info(g, "ECC SM LRF is disabled"); + return 0; + } + + nvgpu_log_info(g, "gr_gv11b_ecc_scrub_sm_lrf"); + scrub_mask = + (gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp0_task_f() | + gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp1_task_f() | + gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp2_task_f() | + gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp3_task_f() | + gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp4_task_f() | + gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp5_task_f() | + gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp6_task_f() | + gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp7_task_f()); + + /* Issue scrub lrf regions with single write command */ + gk20a_writel(g, gr_pri_gpcs_tpcs_sm_lrf_ecc_control_r(), scrub_mask); + + scrub_done = + (gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp0_init_f() | + gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp1_init_f() | + gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp2_init_f() | + gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp3_init_f() | + gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp4_init_f() | + gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp5_init_f() | + gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp6_init_f() | + gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp7_init_f()); + + return gr_gv11b_ecc_scrub_is_done(g, + gr_pri_gpc0_tpc0_sm_lrf_ecc_control_r(), + scrub_mask, scrub_done); +} + +static int gr_gv11b_ecc_scrub_sm_l1_data(struct gk20a *g) +{ + u32 scrub_mask, scrub_done; + + if (!nvgpu_is_enabled(g, NVGPU_ECC_ENABLED_SM_L1_DATA)) { + nvgpu_log_info(g, "ECC L1DATA is disabled"); + return 0; + } + nvgpu_log_info(g, "gr_gv11b_ecc_scrub_sm_l1_data"); + scrub_mask = + (gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_0_task_f() | + gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_1_task_f()); + + gk20a_writel(g, gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_r(), + scrub_mask); + + scrub_done = + (gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_0_init_f() | + gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_1_init_f()); + return gr_gv11b_ecc_scrub_is_done(g, + gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_r(), + scrub_mask, scrub_done); +} + +static int gr_gv11b_ecc_scrub_sm_l1_tag(struct gk20a *g) +{ + u32 scrub_mask, scrub_done; + + if (!nvgpu_is_enabled(g, NVGPU_ECC_ENABLED_SM_L1_TAG)) { + nvgpu_log_info(g, "ECC L1TAG is disabled"); + return 0; + } + nvgpu_log_info(g, "gr_gv11b_ecc_scrub_sm_l1_tag"); + scrub_mask = + (gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_0_task_f() | + gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_1_task_f()); + gk20a_writel(g, gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_r(), scrub_mask); + + scrub_done = + (gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_0_init_f() | + gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_1_init_f()); + return gr_gv11b_ecc_scrub_is_done(g, + gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_r(), + scrub_mask, scrub_done); +} + +static int gr_gv11b_ecc_scrub_sm_cbu(struct gk20a *g) +{ + u32 scrub_mask, scrub_done; + + if (!nvgpu_is_enabled(g, NVGPU_ECC_ENABLED_SM_CBU)) { + nvgpu_log_info(g, "ECC CBU is disabled"); + return 0; + } + nvgpu_log_info(g, "gr_gv11b_ecc_scrub_sm_cbu"); + scrub_mask = + (gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm0_task_f() | + gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm1_task_f() | + gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm0_task_f() | + gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm1_task_f()); + gk20a_writel(g, gr_pri_gpcs_tpcs_sm_cbu_ecc_control_r(), scrub_mask); + + scrub_done = + (gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm0_init_f() | + gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm1_init_f() | + gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm0_init_f() | + gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm1_init_f()); + return gr_gv11b_ecc_scrub_is_done(g, + gr_pri_gpc0_tpc0_sm_cbu_ecc_control_r(), + scrub_mask, scrub_done); +} + +static int gr_gv11b_ecc_scrub_sm_icahe(struct gk20a *g) +{ + u32 scrub_mask, scrub_done; + + if (!nvgpu_is_enabled(g, NVGPU_ECC_ENABLED_SM_ICACHE)) { + nvgpu_log_info(g, "ECC ICAHE is disabled"); + return 0; + } + nvgpu_log_info(g, "gr_gv11b_ecc_scrub_sm_icahe"); + scrub_mask = + (gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_data_task_f() | + gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_predecode_task_f() | + gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_data_task_f() | + gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_predecode_task_f()); + gk20a_writel(g, gr_pri_gpcs_tpcs_sm_icache_ecc_control_r(), scrub_mask); + + scrub_done = + (gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_data_init_f() | + gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_predecode_init_f() | + gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_data_init_f() | + gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_predecode_init_f()); + return gr_gv11b_ecc_scrub_is_done(g, + gr_pri_gpc0_tpc0_sm_icache_ecc_control_r(), + scrub_mask, scrub_done); +} + +void gr_gv11b_ecc_init_scrub_reg(struct gk20a *g) +{ + nvgpu_log_fn(g, "ecc srub start "); + + gv11b_detect_ecc_enabled_units(g); + + if (gr_gv11b_ecc_scrub_sm_lrf(g)) + nvgpu_warn(g, "ECC SCRUB SM LRF Failed"); + if (gr_gv11b_ecc_scrub_sm_l1_data(g)) + nvgpu_warn(g, "ECC SCRUB SM L1 DATA Failed"); + if (gr_gv11b_ecc_scrub_sm_l1_tag(g)) + nvgpu_warn(g, "ECC SCRUB SM L1 TAG Failed"); + if (gr_gv11b_ecc_scrub_sm_cbu(g)) + nvgpu_warn(g, "ECC SCRUB SM CBU Failed"); + if (gr_gv11b_ecc_scrub_sm_icahe(g)) + nvgpu_warn(g, "ECC SCRUB SM ICACHE Failed"); + +} diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 7c56f62d..39d12b3f 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h @@ -216,5 +216,6 @@ void gr_gv11b_init_gpc_mmu(struct gk20a *g); int gr_gv11b_init_preemption_state(struct gk20a *g); void gr_gv11b_init_gfxp_wfi_timeout_count(struct gk20a *g); unsigned long gr_gv11b_get_max_gfxp_wfi_timeout_count(struct gk20a *g); +void gr_gv11b_ecc_init_scrub_reg(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/gv11b/gv11b.c b/drivers/gpu/nvgpu/gv11b/gv11b.c index 211755e5..a62e49fb 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gv11b.c @@ -26,8 +26,128 @@ #include #include "gk20a/gk20a.h" +#include "gp10b/gp10b.h" #include "gv11b/gv11b.h" +#include +#include + +void gv11b_detect_ecc_enabled_units(struct gk20a *g) +{ + u32 opt_ecc_en = gk20a_readl(g, fuse_opt_ecc_en_r()); + u32 opt_feature_fuses_override_disable = + gk20a_readl(g, + fuse_opt_feature_fuses_override_disable_r()); + u32 fecs_feature_override_ecc = + gk20a_readl(g, + gr_fecs_feature_override_ecc_r()); + + if (opt_feature_fuses_override_disable) { + if (opt_ecc_en) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_LRF, true); + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_L1_DATA, true); + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_L1_TAG, true); + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_ICACHE, true); + __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_LTC, true); + __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_CBU, true); + } + } else { + /* SM LRF */ + if (gr_fecs_feature_override_ecc_sm_lrf_override_v( + fecs_feature_override_ecc)) { + if (gr_fecs_feature_override_ecc_sm_lrf_v( + fecs_feature_override_ecc)) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_LRF, true); + } + } else { + if (opt_ecc_en) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_LRF, true); + } + } + /* SM L1 DATA*/ + if (gr_fecs_feature_override_ecc_sm_l1_data_override_v( + fecs_feature_override_ecc)) { + if (gr_fecs_feature_override_ecc_sm_l1_data_v( + fecs_feature_override_ecc)) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_L1_DATA, true); + } + } else { + if (opt_ecc_en) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_L1_DATA, true); + } + } + /* SM L1 TAG*/ + if (gr_fecs_feature_override_ecc_sm_l1_tag_override_v( + fecs_feature_override_ecc)) { + if (gr_fecs_feature_override_ecc_sm_l1_tag_v( + fecs_feature_override_ecc)) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_L1_TAG, true); + } + } else { + if (opt_ecc_en) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_L1_TAG, true); + } + } + /* SM ICACHE*/ + if (gr_fecs_feature_override_ecc_1_sm_l0_icache_override_v( + fecs_feature_override_ecc) && + gr_fecs_feature_override_ecc_1_sm_l1_icache_override_v( + fecs_feature_override_ecc)) { + if (gr_fecs_feature_override_ecc_1_sm_l0_icache_v( + fecs_feature_override_ecc) && + gr_fecs_feature_override_ecc_1_sm_l1_icache_v( + fecs_feature_override_ecc)) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_ICACHE, true); + } + } else { + if (opt_ecc_en) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_ICACHE, true); + } + } + /* LTC */ + if (gr_fecs_feature_override_ecc_ltc_override_v( + fecs_feature_override_ecc)) { + if (gr_fecs_feature_override_ecc_ltc_v( + fecs_feature_override_ecc)) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_LTC, true); + } + } else { + if (opt_ecc_en) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_LTC, true); + } + } + /* SM CBU */ + if (gr_fecs_feature_override_ecc_sm_cbu_override_v( + fecs_feature_override_ecc)) { + if (gr_fecs_feature_override_ecc_sm_cbu_v( + fecs_feature_override_ecc)) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_CBU, true); + } + } else { + if (opt_ecc_en) { + __nvgpu_set_enabled(g, + NVGPU_ECC_ENABLED_SM_CBU, true); + } + } + } +} + + int gv11b_init_gpu_characteristics(struct gk20a *g) { diff --git a/drivers/gpu/nvgpu/gv11b/gv11b.h b/drivers/gpu/nvgpu/gv11b/gv11b.h index 3d5490e6..17dfa7aa 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gv11b.h @@ -27,6 +27,7 @@ #include "gk20a/gk20a.h" +void gv11b_detect_ecc_enabled_units(struct gk20a *g); int gv11b_init_gpu_characteristics(struct gk20a *g); #endif /* GV11B_H */ diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index f6bdf6e5..65cae8de 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c @@ -392,6 +392,7 @@ static const struct gpu_ops gv11b_ops = { gr_gv11b_init_gfxp_wfi_timeout_count, .get_max_gfxp_wfi_timeout_count = gr_gv11b_get_max_gfxp_wfi_timeout_count, + .ecc_init_scrub_reg = gr_gv11b_ecc_init_scrub_reg, }, .fb = { .reset = gv11b_fb_reset, diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h index ad5b3db3..4f31e3e2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h @@ -46,6 +46,15 @@ struct gk20a; #define NVGPU_ECC_ENABLED_TEX 10 /* L2 ECC is enabled */ #define NVGPU_ECC_ENABLED_LTC 11 +/* SM L1 DATA ECC is enabled */ +#define NVGPU_ECC_ENABLED_SM_L1_DATA 12 +/* SM L1 TAG ECC is enabled */ +#define NVGPU_ECC_ENABLED_SM_L1_TAG 13 +/* SM CBU ECC is enabled */ +#define NVGPU_ECC_ENABLED_SM_CBU 14 +/* SM ICAHE ECC is enabled */ +#define NVGPU_ECC_ENABLED_SM_ICACHE 15 + /* * MM flags. */ diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 805d8b0e..29999163 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -916,6 +916,366 @@ static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(u32 { return (r >> 0U) & 0xffffU; } +static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_r(void) +{ + return 0x00419b54U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp0_f(u32 v) +{ + return (v & 0x1U) << 0U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp0_task_f(void) +{ + return 0x1U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp1_f(u32 v) +{ + return (v & 0x1U) << 1U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp1_task_f(void) +{ + return 0x2U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp2_f(u32 v) +{ + return (v & 0x1U) << 2U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp2_task_f(void) +{ + return 0x4U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp3_f(u32 v) +{ + return (v & 0x1U) << 3U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp3_task_f(void) +{ + return 0x8U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp4_f(u32 v) +{ + return (v & 0x1U) << 4U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp4_task_f(void) +{ + return 0x10U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp5_f(u32 v) +{ + return (v & 0x1U) << 5U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp5_task_f(void) +{ + return 0x20U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp6_f(u32 v) +{ + return (v & 0x1U) << 6U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp6_task_f(void) +{ + return 0x40U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp7_f(u32 v) +{ + return (v & 0x1U) << 7U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_lrf_ecc_control_scrub_qrfdp7_task_f(void) +{ + return 0x80U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_r(void) +{ + return 0x00504354U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp0_f(u32 v) +{ + return (v & 0x1U) << 0U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp0_init_f(void) +{ + return 0x0U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp1_f(u32 v) +{ + return (v & 0x1U) << 1U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp1_init_f(void) +{ + return 0x0U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp2_f(u32 v) +{ + return (v & 0x1U) << 2U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp2_init_f(void) +{ + return 0x0U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp3_f(u32 v) +{ + return (v & 0x1U) << 3U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp3_init_f(void) +{ + return 0x0U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp4_f(u32 v) +{ + return (v & 0x1U) << 4U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp4_init_f(void) +{ + return 0x0U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp5_f(u32 v) +{ + return (v & 0x1U) << 5U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp5_init_f(void) +{ + return 0x0U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp6_f(u32 v) +{ + return (v & 0x1U) << 6U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp6_init_f(void) +{ + return 0x0U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp7_f(u32 v) +{ + return (v & 0x1U) << 7U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_control_scrub_qrfdp7_init_f(void) +{ + return 0x0U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_r(void) +{ + return 0x00419b68U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_0_f(u32 v) +{ + return (v & 0x1U) << 0U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_0_task_f(void) +{ + return 0x1U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_1_f(u32 v) +{ + return (v & 0x1U) << 1U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_l1_data_ecc_control_scrub_el1_1_task_f(void) +{ + return 0x2U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_r(void) +{ + return 0x00504368U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_0_f(u32 v) +{ + return (v & 0x1U) << 0U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_0_init_f(void) +{ + return 0x0U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_1_f(u32 v) +{ + return (v & 0x1U) << 1U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_control_scrub_el1_1_init_f(void) +{ + return 0x0U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_r(void) +{ + return 0x00419e20U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_0_f(u32 v) +{ + return (v & 0x1U) << 0U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_0_task_f(void) +{ + return 0x1U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_1_f(u32 v) +{ + return (v & 0x1U) << 1U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_l1_tag_ecc_control_scrub_el1_1_task_f(void) +{ + return 0x2U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_r(void) +{ + return 0x00504620U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_0_f(u32 v) +{ + return (v & 0x1U) << 0U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_0_init_f(void) +{ + return 0x0U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_1_f(u32 v) +{ + return (v & 0x1U) << 1U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_control_scrub_el1_1_init_f(void) +{ + return 0x0U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_r(void) +{ + return 0x00419e34U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm0_f(u32 v) +{ + return (v & 0x1U) << 0U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm0_task_f(void) +{ + return 0x1U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm1_f(u32 v) +{ + return (v & 0x1U) << 1U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_warp_sm1_task_f(void) +{ + return 0x2U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm0_f(u32 v) +{ + return (v & 0x1U) << 2U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm0_task_f(void) +{ + return 0x4U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm1_f(u32 v) +{ + return (v & 0x1U) << 3U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_cbu_ecc_control_scrub_barrier_sm1_task_f(void) +{ + return 0x8U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_r(void) +{ + return 0x00504634U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm0_f(u32 v) +{ + return (v & 0x1U) << 0U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm0_init_f(void) +{ + return 0x0U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm1_f(u32 v) +{ + return (v & 0x1U) << 1U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_warp_sm1_init_f(void) +{ + return 0x0U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm0_f(u32 v) +{ + return (v & 0x1U) << 2U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm0_init_f(void) +{ + return 0x0U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm1_f(u32 v) +{ + return (v & 0x1U) << 3U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_control_scrub_barrier_sm1_init_f(void) +{ + return 0x0U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_r(void) +{ + return 0x00419e48U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_data_f(u32 v) +{ + return (v & 0x1U) << 0U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_data_task_f(void) +{ + return 0x1U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_predecode_f(u32 v) +{ + return (v & 0x1U) << 1U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l0_predecode_task_f(void) +{ + return 0x2U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_data_f(u32 v) +{ + return (v & 0x1U) << 2U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_data_task_f(void) +{ + return 0x4U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_predecode_f(u32 v) +{ + return (v & 0x1U) << 3U; +} +static inline u32 gr_pri_gpcs_tpcs_sm_icache_ecc_control_scrub_l1_predecode_task_f(void) +{ + return 0x8U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_r(void) +{ + return 0x00504648U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_data_f(u32 v) +{ + return (v & 0x1U) << 0U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_data_init_f(void) +{ + return 0x0U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_predecode_f(u32 v) +{ + return (v & 0x1U) << 1U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l0_predecode_init_f(void) +{ + return 0x0U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_data_f(u32 v) +{ + return (v & 0x1U) << 2U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_data_init_f(void) +{ + return 0x0U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_predecode_f(u32 v) +{ + return (v & 0x1U) << 3U; +} +static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_control_scrub_l1_predecode_init_f(void) +{ + return 0x0U; +} static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) { return 0x005042c4U; @@ -1920,21 +2280,65 @@ static inline u32 gr_fecs_feature_override_ecc_r(void) { return 0x00409658U; } +static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) +{ + return (r >> 0U) & 0x1U; +} static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) { return (r >> 3U) & 0x1U; } +static inline u32 gr_fecs_feature_override_ecc_sm_l1_data_v(u32 r) +{ + return (r >> 4U) & 0x1U; +} +static inline u32 gr_fecs_feature_override_ecc_sm_l1_data_override_v(u32 r) +{ + return (r >> 7U) & 0x1U; +} +static inline u32 gr_fecs_feature_override_ecc_sm_l1_tag_v(u32 r) +{ + return (r >> 8U) & 0x1U; +} +static inline u32 gr_fecs_feature_override_ecc_sm_l1_tag_override_v(u32 r) +{ + return (r >> 11U) & 0x1U; +} +static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) +{ + return (r >> 12U) & 0x1U; +} static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) { return (r >> 15U) & 0x1U; } -static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) +static inline u32 gr_fecs_feature_override_ecc_sm_cbu_v(u32 r) +{ + return (r >> 20U) & 0x1U; +} +static inline u32 gr_fecs_feature_override_ecc_sm_cbu_override_v(u32 r) +{ + return (r >> 23U) & 0x1U; +} +static inline u32 gr_fecs_feature_override_ecc_1_r(void) +{ + return 0x0040965cU; +} +static inline u32 gr_fecs_feature_override_ecc_1_sm_l0_icache_v(u32 r) { return (r >> 0U) & 0x1U; } -static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) +static inline u32 gr_fecs_feature_override_ecc_1_sm_l0_icache_override_v(u32 r) { - return (r >> 12U) & 0x1U; + return (r >> 1U) & 0x1U; +} +static inline u32 gr_fecs_feature_override_ecc_1_sm_l1_icache_v(u32 r) +{ + return (r >> 2U) & 0x1U; +} +static inline u32 gr_fecs_feature_override_ecc_1_sm_l1_icache_override_v(u32 r) +{ + return (r >> 3U) & 0x1U; } static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) { -- cgit v1.2.2