From 305dfe9fc0fa9001568a7713742418e1597886fd Mon Sep 17 00:00:00 2001 From: Seema Khowala Date: Thu, 13 Jul 2017 15:40:51 -0700 Subject: gpu: nvgpu: add ctxsw etpc regs Add etpc ctxsw regs for t19x Bug 200311674 Change-Id: I2d5076cb4df8040613c20d28518325ad7c6a9145 Signed-off-by: Seema Khowala Reviewed-on: https://git-master.nvidia.com/r/1520140 GVS: Gerrit_Virtual_Submit Tested-by: Tushar Kashalikar Reviewed-by: Tushar Kashalikar Reviewed-by: Vijayakumar Subbu --- drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c | 9 +++++++++ drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h | 1 + drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c | 19 ++++++++++++++++++- drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 1 + 4 files changed, 29 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu') diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c index eff45cb0..6e069d99 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c @@ -333,6 +333,14 @@ static int gr_gk20a_init_ctx_vars_fw(struct gk20a *g, struct gr_gk20a *gr) if (err) goto clean_up; break; + case NETLIST_REGIONID_CTXREG_ETPC: + gk20a_dbg_info("NETLIST_REGIONID_CTXREG_ETPC"); + err = gr_gk20a_alloc_load_netlist_aiv(g, + src, size, &g->gr.ctx_vars.ctxsw_regs.etpc); + if (err) + goto clean_up; + break; + default: gk20a_dbg_info("unrecognized region %d skipped", i); break; @@ -383,6 +391,7 @@ clean_up: nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.perf_pma.l); nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.pm_rop.l); nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.pm_ucgpc.l); + nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.etpc.l); nvgpu_release_firmware(g, netlist_fw); err = -ENOENT; } diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h index d645ed13..90041096 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h @@ -98,6 +98,7 @@ union __max_name { #define NETLIST_REGIONID_NVPERF_PMA 30 #define NETLIST_REGIONID_CTXREG_PMROP 31 #define NETLIST_REGIONID_CTXREG_PMUCGPC 32 +#define NETLIST_REGIONID_CTXREG_ETPC 33 struct netlist_region { u32 region_id; diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c index 12ec9c5f..36071223 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c +++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c @@ -3,7 +3,7 @@ * * GK20A Graphics Context for Simulation * - * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -72,6 +72,8 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr) &g->gr.ctx_vars.ctxsw_regs.pm_gpc.count); gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC_COUNT", 0, &g->gr.ctx_vars.ctxsw_regs.pm_tpc.count); + gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC_COUNT", 0, + &g->gr.ctx_vars.ctxsw_regs.etpc.count); err |= !alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.fecs.inst); err |= !alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.fecs.data); @@ -90,6 +92,7 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr) err |= !alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.ctxsw_regs.pm_sys); err |= !alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.ctxsw_regs.pm_gpc); err |= !alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.ctxsw_regs.pm_tpc); + err |= !alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.ctxsw_regs.etpc); if (err) goto fail; @@ -233,6 +236,20 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr) i, &l[i].value); } + gk20a_dbg(gpu_dbg_info | gpu_dbg_fn, "query GRCTX_REG_LIST_ETPC"); + for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.etpc.count; i++) { + struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.etpc.l; + gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC:ADDR", + i, &l[i].addr); + gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC:INDEX", + i, &l[i].index); + gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC:VALUE", + i, &l[i].value); + gk20a_dbg(gpu_dbg_info | gpu_dbg_fn, + "addr:0x%#08x index:0x%08x value:0x%08x", + l[i].addr, l[i].index, l[i].value); + } + g->gr.ctx_vars.valid = true; gk20a_sim_esc_readl(g, "GRCTX_GEN_CTX_REGS_BASE_INDEX", 0, diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 436377bd..d32a719e 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h @@ -270,6 +270,7 @@ struct gr_gk20a { struct aiv_list_gk20a perf_pma; struct aiv_list_gk20a pm_rop; struct aiv_list_gk20a pm_ucgpc; + struct aiv_list_gk20a etpc; } ctxsw_regs; int regs_base_index; bool valid; -- cgit v1.2.2