From 2c04ddcdf6adce0f7430cc42fd09475973d1c62c Mon Sep 17 00:00:00 2001 From: Lakshmanan M Date: Wed, 22 Jun 2016 15:57:16 +0530 Subject: gpu: nvgpu: Add interface for privileged channel allocation Added interface for privileged channel allocation to excute the privileged method (ex. CE phys mode transfer). JIRA DNVGPU-53 Change-Id: I07f9181720b14345cf5890919c2818dfcf505d86 Signed-off-by: Lakshmanan M Reviewed-on: http://git-master/r/1169315 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 27 ++++++++++++++++++++++++--- drivers/gpu/nvgpu/gk20a/channel_gk20a.h | 8 +++++++- 2 files changed, 31 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/nvgpu') diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index 91e025e1..3f9b0432 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c @@ -244,6 +244,18 @@ u32 channel_gk20a_pbdma_acquire_val(struct channel_gk20a *c) return val; } +void gk20a_channel_setup_ramfc_for_privileged_channel(struct channel_gk20a *c) +{ + struct gk20a *g = c->g; + struct mem_desc *mem = &c->inst_block; + + gk20a_dbg_info("channel %d : set ramfc privileged_channel", c->hw_chid); + + /* Enable HCE priv mode for phys mode transfer */ + gk20a_mem_wr32(g, mem, ram_fc_hce_ctrl_w(), + pbdma_hce_ctrl_hce_priv_mode_yes_f()); +} + int channel_gk20a_setup_ramfc(struct channel_gk20a *c, u64 gpfifo_base, u32 gpfifo_entries, u32 flags) { @@ -300,6 +312,9 @@ int channel_gk20a_setup_ramfc(struct channel_gk20a *c, gk20a_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid)); + if (c->is_privileged_channel) + gk20a_channel_setup_ramfc_for_privileged_channel(c); + return channel_gk20a_commit_userd(c); } @@ -1093,7 +1108,7 @@ struct channel_gk20a *gk20a_open_new_channel_with_cb(struct gk20a *g, void (*update_fn)(struct channel_gk20a *, void *), void *update_fn_data) { - struct channel_gk20a *ch = gk20a_open_new_channel(g, -1); + struct channel_gk20a *ch = gk20a_open_new_channel(g, -1, false); if (ch) { spin_lock(&ch->update_fn_lock); @@ -1105,7 +1120,9 @@ struct channel_gk20a *gk20a_open_new_channel_with_cb(struct gk20a *g, return ch; } -struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g, s32 runlist_id) +struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g, + s32 runlist_id, + bool is_privileged_channel) { struct fifo_gk20a *f = &g->fifo; struct channel_gk20a *ch; @@ -1132,6 +1149,9 @@ struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g, s32 runlist_id) /* Runlist for the channel */ ch->runlist_id = runlist_id; + /* Channel privilege level */ + ch->is_privileged_channel = is_privileged_channel; + if (g->ops.fifo.alloc_inst(g, ch)) { ch->g = NULL; free_channel(f, ch); @@ -1198,7 +1218,8 @@ static int __gk20a_channel_open(struct gk20a *g, struct file *filp, s32 runlist_ gk20a_err(dev_from_gk20a(g), "failed to power on, %d", err); return err; } - ch = gk20a_open_new_channel(g, runlist_id); + /* All the user space channel should be non privilege */ + ch = gk20a_open_new_channel(g, runlist_id, false); gk20a_idle(g->dev); if (!ch) { gk20a_err(dev_from_gk20a(g), diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h index f60bbda4..acd272b4 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h @@ -200,6 +200,8 @@ struct channel_gk20a { u32 interleave_level; u32 runlist_id; + + bool is_privileged_channel; }; static inline bool gk20a_channel_as_bound(struct channel_gk20a *ch) @@ -255,7 +257,9 @@ void _gk20a_channel_put(struct channel_gk20a *ch, const char *caller); int gk20a_wait_channel_idle(struct channel_gk20a *ch); /* runlist_id -1 is synonym for ENGINE_GR_GK20A runlist id */ -struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g, s32 runlist_id); +struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g, + s32 runlist_id, + bool is_privileged_channel); struct channel_gk20a *gk20a_open_new_channel_with_cb(struct gk20a *g, void (*update_fn)(struct channel_gk20a *, void *), void *update_fn_data); @@ -291,4 +295,6 @@ int gk20a_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice); void gk20a_channel_event_id_post_event(struct channel_gk20a *ch, int event_id); +void gk20a_channel_setup_ramfc_for_privileged_channel(struct channel_gk20a *c); + #endif /* CHANNEL_GK20A_H */ -- cgit v1.2.2