From 223ea4d8a179835dd5899bbc12fe78b4998b0bd7 Mon Sep 17 00:00:00 2001
From: Thomas Fleury <tfleury@nvidia.com>
Date: Mon, 12 Feb 2018 10:00:32 -0800
Subject: gpu: nvgpu: gv100: update registers

Update GV100 registers for nvlink.

JIRA EVLR-2328

Change-Id: I0fad01560022d979fbdcd94fd066e507691969ae
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1656052
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
---
 .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h |  462 +++++-
 .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h |   76 +
 .../nvgpu/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h |  331 +++++
 .../include/nvgpu/hw/gv100/hw_ioctrlmif_gv100.h    |  331 +++++
 .../gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h |   22 +-
 .../nvgpu/include/nvgpu/hw/gv100/hw_minion_gv100.h |  919 ++++++++++++
 .../nvgpu/include/nvgpu/hw/gv100/hw_nvl_gv100.h    | 1571 ++++++++++++++++++++
 .../nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h   |  311 ++++
 .../nvgpu/include/nvgpu/hw/gv100/hw_nvlipt_gv100.h |  279 ++++
 .../nvgpu/include/nvgpu/hw/gv100/hw_nvtlc_gv100.h  |   95 ++
 .../nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h    |   22 +-
 .../nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h    |  102 +-
 .../nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h   |  199 +++
 13 files changed, 4716 insertions(+), 4 deletions(-)
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrlmif_gv100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_minion_gv100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvl_gv100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlipt_gv100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvtlc_gv100.h
 create mode 100644 drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h

(limited to 'drivers/gpu/nvgpu')

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h
index a4fcd1e6..1bac1a6a 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fb_gv100.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -60,6 +60,82 @@ static inline u32 fb_fbhub_num_active_ltcs_r(void)
 {
 	return 0x00100800U;
 }
+static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_f(u32 v)
+{
+	return (v & 0xffU) << 16U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_m(void)
+{
+	return 0xffU << 16U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_v(u32 r)
+{
+	return (r >> 16U) & 0xffU;
+}
+static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_f(u32 v, u32 i)
+{
+	return (v & 0x1U) << (16U + i*1U);
+}
+static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_m(u32 i)
+{
+	return 0x1U << (16U + i*1U);
+}
+static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_v(u32 r, u32 i)
+{
+	return (r >> (16U + i*1U)) & 0x1U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer___size_1_v(void)
+{
+	return 0x00000008U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer___size_1_f(u32 i)
+{
+	return 0x0U << (32U + i*1U);
+}
+static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_enabled_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_enabled_f(u32 i)
+{
+	return 0x1U << (32U + i*1U);
+}
+static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_f(u32 i)
+{
+	return 0x0U << (32U + i*1U);
+}
+static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_f(u32 v)
+{
+	return (v & 0x1U) << 25U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m(void)
+{
+	return 0x1U << 25U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_v(u32 r)
+{
+	return (r >> 25U) & 0x1U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_read_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_read_f(void)
+{
+	return 0x0U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void)
+{
+	return 0x2000000U;
+}
 static inline u32 fb_mmu_ctrl_r(void)
 {
 	return 0x00100c80U;
@@ -100,6 +176,178 @@ static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void)
 {
 	return 0x0U;
 }
+static inline u32 fb_mmu_ctrl_atomic_capability_mode_f(u32 v)
+{
+	return (v & 0x3U) << 24U;
+}
+static inline u32 fb_mmu_ctrl_atomic_capability_mode_m(void)
+{
+	return 0x3U << 24U;
+}
+static inline u32 fb_mmu_ctrl_atomic_capability_mode_v(u32 r)
+{
+	return (r >> 24U) & 0x3U;
+}
+static inline u32 fb_mmu_ctrl_atomic_capability_mode_l2_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 fb_mmu_ctrl_atomic_capability_mode_l2_f(void)
+{
+	return 0x0U;
+}
+static inline u32 fb_mmu_ctrl_atomic_capability_mode_atomic_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 fb_mmu_ctrl_atomic_capability_mode_atomic_f(void)
+{
+	return 0x1000000U;
+}
+static inline u32 fb_mmu_ctrl_atomic_capability_mode_rmw_v(void)
+{
+	return 0x00000002U;
+}
+static inline u32 fb_mmu_ctrl_atomic_capability_mode_rmw_f(void)
+{
+	return 0x2000000U;
+}
+static inline u32 fb_mmu_ctrl_atomic_capability_mode_power_v(void)
+{
+	return 0x00000003U;
+}
+static inline u32 fb_mmu_ctrl_atomic_capability_mode_power_f(void)
+{
+	return 0x3000000U;
+}
+static inline u32 fb_hsmmu_pri_mmu_ctrl_r(void)
+{
+	return 0x001fac80U;
+}
+static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_f(u32 v)
+{
+	return (v & 0x3U) << 24U;
+}
+static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_m(void)
+{
+	return 0x3U << 24U;
+}
+static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_v(u32 r)
+{
+	return (r >> 24U) & 0x3U;
+}
+static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_l2_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_l2_f(void)
+{
+	return 0x0U;
+}
+static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_atomic_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_atomic_f(void)
+{
+	return 0x1000000U;
+}
+static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_rmw_v(void)
+{
+	return 0x00000002U;
+}
+static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_rmw_f(void)
+{
+	return 0x2000000U;
+}
+static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_power_v(void)
+{
+	return 0x00000003U;
+}
+static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_power_f(void)
+{
+	return 0x3000000U;
+}
+static inline u32 fb_hshub_num_active_ltcs_r(void)
+{
+	return 0x001fbc20U;
+}
+static inline u32 fb_hshub_num_active_ltcs_use_nvlink_f(u32 v)
+{
+	return (v & 0xffU) << 16U;
+}
+static inline u32 fb_hshub_num_active_ltcs_use_nvlink_m(void)
+{
+	return 0xffU << 16U;
+}
+static inline u32 fb_hshub_num_active_ltcs_use_nvlink_v(u32 r)
+{
+	return (r >> 16U) & 0xffU;
+}
+static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_f(u32 v, u32 i)
+{
+	return (v & 0x1U) << (16U + i*1U);
+}
+static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_m(u32 i)
+{
+	return 0x1U << (16U + i*1U);
+}
+static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_v(u32 r, u32 i)
+{
+	return (r >> (16U + i*1U)) & 0x1U;
+}
+static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer___size_1_v(void)
+{
+	return 0x00000008U;
+}
+static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer___size_1_f(u32 i)
+{
+	return 0x0U << (32U + i*1U);
+}
+static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_enabled_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_enabled_f(u32 i)
+{
+	return 0x1U << (32U + i*1U);
+}
+static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_f(u32 i)
+{
+	return 0x0U << (32U + i*1U);
+}
+static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_f(u32 v)
+{
+	return (v & 0x1U) << 25U;
+}
+static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m(void)
+{
+	return 0x1U << 25U;
+}
+static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_v(u32 r)
+{
+	return (r >> 25U) & 0x1U;
+}
+static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_f(void)
+{
+	return 0x0U;
+}
+static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void)
+{
+	return 0x2000000U;
+}
 static inline u32 fb_priv_mmu_phy_secure_r(void)
 {
 	return 0x00100ce4U;
@@ -508,6 +756,30 @@ static inline u32 fb_mmu_vpr_info_fetch_true_v(void)
 {
 	return 0x00000001U;
 }
+static inline u32 fb_niso_cfg1_r(void)
+{
+	return 0x00100c14U;
+}
+static inline u32 fb_niso_cfg1_sysmem_nvlink_f(u32 v)
+{
+	return (v & 0x1U) << 17U;
+}
+static inline u32 fb_niso_cfg1_sysmem_nvlink_m(void)
+{
+	return 0x1U << 17U;
+}
+static inline u32 fb_niso_cfg1_sysmem_nvlink_v(u32 r)
+{
+	return (r >> 17U) & 0x1U;
+}
+static inline u32 fb_niso_cfg1_sysmem_nvlink_enabled_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 fb_niso_cfg1_sysmem_nvlink_enabled_f(void)
+{
+	return 0x20000U;
+}
 static inline u32 fb_niso_flush_sysmem_addr_r(void)
 {
 	return 0x00100c10U;
@@ -1504,8 +1776,196 @@ static inline u32 fb_mmu_priv_level_mask_r(void)
 {
 	return 0x00100cdcU;
 }
+static inline u32 fb_mmu_priv_level_mask_write_violation_f(u32 v)
+{
+	return (v & 0x1U) << 7U;
+}
 static inline u32 fb_mmu_priv_level_mask_write_violation_m(void)
 {
 	return 0x1U << 7U;
 }
+static inline u32 fb_mmu_priv_level_mask_write_violation_v(u32 r)
+{
+	return (r >> 7U) & 0x1U;
+}
+static inline u32 fb_hshub_config0_r(void)
+{
+	return 0x001fbc00U;
+}
+static inline u32 fb_hshub_config0_sysmem_nvlink_mask_f(u32 v)
+{
+	return (v & 0xffffU) << 0U;
+}
+static inline u32 fb_hshub_config0_sysmem_nvlink_mask_m(void)
+{
+	return 0xffffU << 0U;
+}
+static inline u32 fb_hshub_config0_sysmem_nvlink_mask_v(u32 r)
+{
+	return (r >> 0U) & 0xffffU;
+}
+static inline u32 fb_hshub_config0_peer_pcie_mask_f(u32 v)
+{
+	return (v & 0xffffU) << 16U;
+}
+static inline u32 fb_hshub_config0_peer_pcie_mask_v(u32 r)
+{
+	return (r >> 16U) & 0xffffU;
+}
+static inline u32 fb_hshub_config1_r(void)
+{
+	return 0x001fbc04U;
+}
+static inline u32 fb_hshub_config1_peer_0_nvlink_mask_f(u32 v)
+{
+	return (v & 0xffU) << 0U;
+}
+static inline u32 fb_hshub_config1_peer_0_nvlink_mask_v(u32 r)
+{
+	return (r >> 0U) & 0xffU;
+}
+static inline u32 fb_hshub_config1_peer_1_nvlink_mask_f(u32 v)
+{
+	return (v & 0xffU) << 8U;
+}
+static inline u32 fb_hshub_config1_peer_1_nvlink_mask_v(u32 r)
+{
+	return (r >> 8U) & 0xffU;
+}
+static inline u32 fb_hshub_config1_peer_2_nvlink_mask_f(u32 v)
+{
+	return (v & 0xffU) << 16U;
+}
+static inline u32 fb_hshub_config1_peer_2_nvlink_mask_v(u32 r)
+{
+	return (r >> 16U) & 0xffU;
+}
+static inline u32 fb_hshub_config1_peer_3_nvlink_mask_f(u32 v)
+{
+	return (v & 0xffU) << 24U;
+}
+static inline u32 fb_hshub_config1_peer_3_nvlink_mask_v(u32 r)
+{
+	return (r >> 24U) & 0xffU;
+}
+static inline u32 fb_hshub_config2_r(void)
+{
+	return 0x001fbc08U;
+}
+static inline u32 fb_hshub_config2_peer_4_nvlink_mask_f(u32 v)
+{
+	return (v & 0xffU) << 0U;
+}
+static inline u32 fb_hshub_config2_peer_4_nvlink_mask_v(u32 r)
+{
+	return (r >> 0U) & 0xffU;
+}
+static inline u32 fb_hshub_config2_peer_5_nvlink_mask_f(u32 v)
+{
+	return (v & 0xffU) << 8U;
+}
+static inline u32 fb_hshub_config2_peer_5_nvlink_mask_v(u32 r)
+{
+	return (r >> 8U) & 0xffU;
+}
+static inline u32 fb_hshub_config2_peer_6_nvlink_mask_f(u32 v)
+{
+	return (v & 0xffU) << 16U;
+}
+static inline u32 fb_hshub_config2_peer_6_nvlink_mask_v(u32 r)
+{
+	return (r >> 16U) & 0xffU;
+}
+static inline u32 fb_hshub_config2_peer_7_nvlink_mask_f(u32 v)
+{
+	return (v & 0xffU) << 24U;
+}
+static inline u32 fb_hshub_config2_peer_7_nvlink_mask_v(u32 r)
+{
+	return (r >> 24U) & 0xffU;
+}
+static inline u32 fb_hshub_config6_r(void)
+{
+	return 0x001fbc18U;
+}
+static inline u32 fb_hshub_config7_r(void)
+{
+	return 0x001fbc1cU;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_0_physical_portmap_f(u32 v)
+{
+	return (v & 0xfU) << 0U;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_0_physical_portmap_v(u32 r)
+{
+	return (r >> 0U) & 0xfU;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_1_physical_portmap_f(u32 v)
+{
+	return (v & 0xfU) << 4U;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_1_physical_portmap_v(u32 r)
+{
+	return (r >> 4U) & 0xfU;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_2_physical_portmap_f(u32 v)
+{
+	return (v & 0xfU) << 8U;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_2_physical_portmap_v(u32 r)
+{
+	return (r >> 8U) & 0xfU;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_3_physical_portmap_f(u32 v)
+{
+	return (v & 0xfU) << 12U;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_3_physical_portmap_v(u32 r)
+{
+	return (r >> 12U) & 0xfU;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_4_physical_portmap_f(u32 v)
+{
+	return (v & 0xfU) << 16U;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_4_physical_portmap_v(u32 r)
+{
+	return (r >> 16U) & 0xfU;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_5_physical_portmap_f(u32 v)
+{
+	return (v & 0xfU) << 20U;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_5_physical_portmap_v(u32 r)
+{
+	return (r >> 20U) & 0xfU;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_6_physical_portmap_f(u32 v)
+{
+	return (v & 0xfU) << 24U;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_6_physical_portmap_v(u32 r)
+{
+	return (r >> 24U) & 0xfU;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_7_physical_portmap_f(u32 v)
+{
+	return (v & 0xfU) << 28U;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_7_physical_portmap_v(u32 r)
+{
+	return (r >> 28U) & 0xfU;
+}
+static inline u32 fb_hshub_nvl_cfg_priv_level_mask_r(void)
+{
+	return 0x001fbc50U;
+}
+static inline u32 fb_hshub_nvl_cfg_priv_level_mask_write_protection_f(u32 v)
+{
+	return (v & 0x7U) << 4U;
+}
+static inline u32 fb_hshub_nvl_cfg_priv_level_mask_write_protection_v(u32 r)
+{
+	return (r >> 4U) & 0x7U;
+}
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h
index 2e28bdb8..8e475895 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h
@@ -184,6 +184,22 @@ static inline u32 gr_exception_sked_m(void)
 {
 	return 0x1U << 8U;
 }
+static inline u32 gr_exception_pd_m(void)
+{
+	return 0x1U << 2U;
+}
+static inline u32 gr_exception_scc_m(void)
+{
+	return 0x1U << 3U;
+}
+static inline u32 gr_exception_ssync_m(void)
+{
+	return 0x1U << 5U;
+}
+static inline u32 gr_exception_mme_m(void)
+{
+	return 0x1U << 7U;
+}
 static inline u32 gr_exception1_r(void)
 {
 	return 0x00400118U;
@@ -232,6 +248,46 @@ static inline u32 gr_exception_en_ds_enabled_f(void)
 {
 	return 0x10U;
 }
+static inline u32 gr_exception_en_pd_m(void)
+{
+	return 0x1U << 2U;
+}
+static inline u32 gr_exception_en_pd_enabled_f(void)
+{
+	return 0x4U;
+}
+static inline u32 gr_exception_en_scc_m(void)
+{
+	return 0x1U << 3U;
+}
+static inline u32 gr_exception_en_scc_enabled_f(void)
+{
+	return 0x8U;
+}
+static inline u32 gr_exception_en_ssync_m(void)
+{
+	return 0x1U << 5U;
+}
+static inline u32 gr_exception_en_ssync_enabled_f(void)
+{
+	return 0x20U;
+}
+static inline u32 gr_exception_en_mme_m(void)
+{
+	return 0x1U << 7U;
+}
+static inline u32 gr_exception_en_mme_enabled_f(void)
+{
+	return 0x80U;
+}
+static inline u32 gr_exception_en_sked_m(void)
+{
+	return 0x1U << 8U;
+}
+static inline u32 gr_exception_en_sked_enabled_f(void)
+{
+	return 0x100U;
+}
 static inline u32 gr_exception1_en_r(void)
 {
 	return 0x00400130U;
@@ -872,6 +928,10 @@ static inline u32 gr_fe_hww_esr_en_enable_f(void)
 {
 	return 0x80000000U;
 }
+static inline u32 gr_fe_hww_esr_info_r(void)
+{
+	return 0x004041b0U;
+}
 static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void)
 {
 	return 0x00419eacU;
@@ -1000,6 +1060,10 @@ static inline u32 gr_mme_hww_esr_en_enable_f(void)
 {
 	return 0x80000000U;
 }
+static inline u32 gr_mme_hww_esr_info_r(void)
+{
+	return 0x00404494U;
+}
 static inline u32 gr_memfmt_hww_esr_r(void)
 {
 	return 0x00404600U;
@@ -2372,6 +2436,18 @@ static inline u32 gr_scc_hww_esr_en_enable_f(void)
 {
 	return 0x80000000U;
 }
+static inline u32 gr_ssync_hww_esr_r(void)
+{
+	return 0x00405a14U;
+}
+static inline u32 gr_ssync_hww_esr_reset_active_f(void)
+{
+	return 0x40000000U;
+}
+static inline u32 gr_ssync_hww_esr_en_enable_f(void)
+{
+	return 0x80000000U;
+}
 static inline u32 gr_sked_hww_esr_r(void)
 {
 	return 0x00407020U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h
new file mode 100644
index 00000000..c27e607c
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h
@@ -0,0 +1,331 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ioctrl_gv100_h_
+#define _hw_ioctrl_gv100_h_
+
+static inline u32 ioctrl_reset_r(void)
+{
+	return 0x00000140U;
+}
+static inline u32 ioctrl_reset_sw_post_reset_delay_microseconds_v(void)
+{
+	return 0x00000008U;
+}
+static inline u32 ioctrl_reset_linkreset_f(u32 v)
+{
+	return (v & 0x3fU) << 8U;
+}
+static inline u32 ioctrl_reset_linkreset_m(void)
+{
+	return 0x3fU << 8U;
+}
+static inline u32 ioctrl_reset_linkreset_v(u32 r)
+{
+	return (r >> 8U) & 0x3fU;
+}
+static inline u32 ioctrl_debug_reset_r(void)
+{
+	return 0x00000144U;
+}
+static inline u32 ioctrl_debug_reset_link_f(u32 v)
+{
+	return (v & 0x3fU) << 0U;
+}
+static inline u32 ioctrl_debug_reset_link_m(void)
+{
+	return 0x3fU << 0U;
+}
+static inline u32 ioctrl_debug_reset_link_v(u32 r)
+{
+	return (r >> 0U) & 0x3fU;
+}
+static inline u32 ioctrl_debug_reset_common_f(u32 v)
+{
+	return (v & 0x1U) << 31U;
+}
+static inline u32 ioctrl_debug_reset_common_m(void)
+{
+	return 0x1U << 31U;
+}
+static inline u32 ioctrl_debug_reset_common_v(u32 r)
+{
+	return (r >> 31U) & 0x1U;
+}
+static inline u32 ioctrl_clock_control_r(u32 i)
+{
+	return 0x00000180U + i*4U;
+}
+static inline u32 ioctrl_clock_control__size_1_v(void)
+{
+	return 0x00000006U;
+}
+static inline u32 ioctrl_clock_control_clkdis_f(u32 v)
+{
+	return (v & 0x1U) << 0U;
+}
+static inline u32 ioctrl_clock_control_clkdis_m(void)
+{
+	return 0x1U << 0U;
+}
+static inline u32 ioctrl_clock_control_clkdis_v(u32 r)
+{
+	return (r >> 0U) & 0x1U;
+}
+static inline u32 ioctrl_top_intr_0_status_r(void)
+{
+	return 0x00000200U;
+}
+static inline u32 ioctrl_top_intr_0_status_link_f(u32 v)
+{
+	return (v & 0x3fU) << 0U;
+}
+static inline u32 ioctrl_top_intr_0_status_link_m(void)
+{
+	return 0x3fU << 0U;
+}
+static inline u32 ioctrl_top_intr_0_status_link_v(u32 r)
+{
+	return (r >> 0U) & 0x3fU;
+}
+static inline u32 ioctrl_top_intr_0_status_common_f(u32 v)
+{
+	return (v & 0x1U) << 31U;
+}
+static inline u32 ioctrl_top_intr_0_status_common_m(void)
+{
+	return 0x1U << 31U;
+}
+static inline u32 ioctrl_top_intr_0_status_common_v(u32 r)
+{
+	return (r >> 31U) & 0x1U;
+}
+static inline u32 ioctrl_common_intr_0_mask_r(void)
+{
+	return 0x00000220U;
+}
+static inline u32 ioctrl_common_intr_0_mask_fatal_f(u32 v)
+{
+	return (v & 0x1U) << 0U;
+}
+static inline u32 ioctrl_common_intr_0_mask_fatal_v(u32 r)
+{
+	return (r >> 0U) & 0x1U;
+}
+static inline u32 ioctrl_common_intr_0_mask_nonfatal_f(u32 v)
+{
+	return (v & 0x1U) << 1U;
+}
+static inline u32 ioctrl_common_intr_0_mask_nonfatal_v(u32 r)
+{
+	return (r >> 1U) & 0x1U;
+}
+static inline u32 ioctrl_common_intr_0_mask_correctable_f(u32 v)
+{
+	return (v & 0x1U) << 2U;
+}
+static inline u32 ioctrl_common_intr_0_mask_correctable_v(u32 r)
+{
+	return (r >> 2U) & 0x1U;
+}
+static inline u32 ioctrl_common_intr_0_mask_intra_f(u32 v)
+{
+	return (v & 0x1U) << 3U;
+}
+static inline u32 ioctrl_common_intr_0_mask_intra_v(u32 r)
+{
+	return (r >> 3U) & 0x1U;
+}
+static inline u32 ioctrl_common_intr_0_mask_intrb_f(u32 v)
+{
+	return (v & 0x1U) << 4U;
+}
+static inline u32 ioctrl_common_intr_0_mask_intrb_v(u32 r)
+{
+	return (r >> 4U) & 0x1U;
+}
+static inline u32 ioctrl_common_intr_0_status_r(void)
+{
+	return 0x00000224U;
+}
+static inline u32 ioctrl_common_intr_0_status_fatal_f(u32 v)
+{
+	return (v & 0x1U) << 0U;
+}
+static inline u32 ioctrl_common_intr_0_status_fatal_v(u32 r)
+{
+	return (r >> 0U) & 0x1U;
+}
+static inline u32 ioctrl_common_intr_0_status_nonfatal_f(u32 v)
+{
+	return (v & 0x1U) << 1U;
+}
+static inline u32 ioctrl_common_intr_0_status_nonfatal_v(u32 r)
+{
+	return (r >> 1U) & 0x1U;
+}
+static inline u32 ioctrl_common_intr_0_status_correctable_f(u32 v)
+{
+	return (v & 0x1U) << 2U;
+}
+static inline u32 ioctrl_common_intr_0_status_correctable_v(u32 r)
+{
+	return (r >> 2U) & 0x1U;
+}
+static inline u32 ioctrl_common_intr_0_status_intra_f(u32 v)
+{
+	return (v & 0x1U) << 3U;
+}
+static inline u32 ioctrl_common_intr_0_status_intra_v(u32 r)
+{
+	return (r >> 3U) & 0x1U;
+}
+static inline u32 ioctrl_common_intr_0_status_intrb_f(u32 v)
+{
+	return (v & 0x1U) << 4U;
+}
+static inline u32 ioctrl_common_intr_0_status_intrb_v(u32 r)
+{
+	return (r >> 4U) & 0x1U;
+}
+static inline u32 ioctrl_link_intr_0_mask_r(u32 i)
+{
+	return 0x00000240U + i*20U;
+}
+static inline u32 ioctrl_link_intr_0_mask_fatal_f(u32 v)
+{
+	return (v & 0x1U) << 0U;
+}
+static inline u32 ioctrl_link_intr_0_mask_fatal_v(u32 r)
+{
+	return (r >> 0U) & 0x1U;
+}
+static inline u32 ioctrl_link_intr_0_mask_nonfatal_f(u32 v)
+{
+	return (v & 0x1U) << 1U;
+}
+static inline u32 ioctrl_link_intr_0_mask_nonfatal_v(u32 r)
+{
+	return (r >> 1U) & 0x1U;
+}
+static inline u32 ioctrl_link_intr_0_mask_correctable_f(u32 v)
+{
+	return (v & 0x1U) << 2U;
+}
+static inline u32 ioctrl_link_intr_0_mask_correctable_v(u32 r)
+{
+	return (r >> 2U) & 0x1U;
+}
+static inline u32 ioctrl_link_intr_0_mask_intra_f(u32 v)
+{
+	return (v & 0x1U) << 3U;
+}
+static inline u32 ioctrl_link_intr_0_mask_intra_v(u32 r)
+{
+	return (r >> 3U) & 0x1U;
+}
+static inline u32 ioctrl_link_intr_0_mask_intrb_f(u32 v)
+{
+	return (v & 0x1U) << 4U;
+}
+static inline u32 ioctrl_link_intr_0_mask_intrb_v(u32 r)
+{
+	return (r >> 4U) & 0x1U;
+}
+static inline u32 ioctrl_link_intr_0_status_r(u32 i)
+{
+	return 0x00000244U + i*20U;
+}
+static inline u32 ioctrl_link_intr_0_status_fatal_f(u32 v)
+{
+	return (v & 0x1U) << 0U;
+}
+static inline u32 ioctrl_link_intr_0_status_fatal_v(u32 r)
+{
+	return (r >> 0U) & 0x1U;
+}
+static inline u32 ioctrl_link_intr_0_status_nonfatal_f(u32 v)
+{
+	return (v & 0x1U) << 1U;
+}
+static inline u32 ioctrl_link_intr_0_status_nonfatal_v(u32 r)
+{
+	return (r >> 1U) & 0x1U;
+}
+static inline u32 ioctrl_link_intr_0_status_correctable_f(u32 v)
+{
+	return (v & 0x1U) << 2U;
+}
+static inline u32 ioctrl_link_intr_0_status_correctable_v(u32 r)
+{
+	return (r >> 2U) & 0x1U;
+}
+static inline u32 ioctrl_link_intr_0_status_intra_f(u32 v)
+{
+	return (v & 0x1U) << 3U;
+}
+static inline u32 ioctrl_link_intr_0_status_intra_v(u32 r)
+{
+	return (r >> 3U) & 0x1U;
+}
+static inline u32 ioctrl_link_intr_0_status_intrb_f(u32 v)
+{
+	return (v & 0x1U) << 4U;
+}
+static inline u32 ioctrl_link_intr_0_status_intrb_v(u32 r)
+{
+	return (r >> 4U) & 0x1U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrlmif_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrlmif_gv100.h
new file mode 100644
index 00000000..5747a9ba
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ioctrlmif_gv100.h
@@ -0,0 +1,331 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ioctrlmif_gv100_h_
+#define _hw_ioctrlmif_gv100_h_
+
+static inline u32 ioctrlmif_rx_err_contain_en_0_r(void)
+{
+	return 0x00000e0cU;
+}
+static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_f(u32 v)
+{
+	return (v & 0x1U) << 3U;
+}
+static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_m(void)
+{
+	return 0x1U << 3U;
+}
+static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_v(u32 r)
+{
+	return (r >> 3U) & 0x1U;
+}
+static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr__prod_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr__prod_f(void)
+{
+	return 0x8U;
+}
+static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_f(u32 v)
+{
+	return (v & 0x1U) << 4U;
+}
+static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_m(void)
+{
+	return 0x1U << 4U;
+}
+static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_v(u32 r)
+{
+	return (r >> 4U) & 0x1U;
+}
+static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr__prod_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr__prod_f(void)
+{
+	return 0x10U;
+}
+static inline u32 ioctrlmif_rx_err_log_en_0_r(void)
+{
+	return 0x00000e04U;
+}
+static inline u32 ioctrlmif_rx_err_log_en_0_rxramdataparityerr_f(u32 v)
+{
+	return (v & 0x1U) << 3U;
+}
+static inline u32 ioctrlmif_rx_err_log_en_0_rxramdataparityerr_m(void)
+{
+	return 0x1U << 3U;
+}
+static inline u32 ioctrlmif_rx_err_log_en_0_rxramdataparityerr_v(u32 r)
+{
+	return (r >> 3U) & 0x1U;
+}
+static inline u32 ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_f(u32 v)
+{
+	return (v & 0x1U) << 4U;
+}
+static inline u32 ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_m(void)
+{
+	return 0x1U << 4U;
+}
+static inline u32 ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_v(u32 r)
+{
+	return (r >> 4U) & 0x1U;
+}
+static inline u32 ioctrlmif_rx_err_report_en_0_r(void)
+{
+	return 0x00000e08U;
+}
+static inline u32 ioctrlmif_rx_err_report_en_0_rxramdataparityerr_f(u32 v)
+{
+	return (v & 0x1U) << 3U;
+}
+static inline u32 ioctrlmif_rx_err_report_en_0_rxramdataparityerr_m(void)
+{
+	return 0x1U << 3U;
+}
+static inline u32 ioctrlmif_rx_err_report_en_0_rxramdataparityerr_v(u32 r)
+{
+	return (r >> 3U) & 0x1U;
+}
+static inline u32 ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_f(u32 v)
+{
+	return (v & 0x1U) << 4U;
+}
+static inline u32 ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_m(void)
+{
+	return 0x1U << 4U;
+}
+static inline u32 ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_v(u32 r)
+{
+	return (r >> 4U) & 0x1U;
+}
+static inline u32 ioctrlmif_rx_err_status_0_r(void)
+{
+	return 0x00000e00U;
+}
+static inline u32 ioctrlmif_rx_err_status_0_rxramdataparityerr_f(u32 v)
+{
+	return (v & 0x1U) << 3U;
+}
+static inline u32 ioctrlmif_rx_err_status_0_rxramdataparityerr_m(void)
+{
+	return 0x1U << 3U;
+}
+static inline u32 ioctrlmif_rx_err_status_0_rxramdataparityerr_v(u32 r)
+{
+	return (r >> 3U) & 0x1U;
+}
+static inline u32 ioctrlmif_rx_err_status_0_rxramhdrparityerr_f(u32 v)
+{
+	return (v & 0x1U) << 4U;
+}
+static inline u32 ioctrlmif_rx_err_status_0_rxramhdrparityerr_m(void)
+{
+	return 0x1U << 4U;
+}
+static inline u32 ioctrlmif_rx_err_status_0_rxramhdrparityerr_v(u32 r)
+{
+	return (r >> 4U) & 0x1U;
+}
+static inline u32 ioctrlmif_rx_err_first_0_r(void)
+{
+	return 0x00000e14U;
+}
+static inline u32 ioctrlmif_tx_err_contain_en_0_r(void)
+{
+	return 0x00000a90U;
+}
+static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr_f(u32 v)
+{
+	return (v & 0x1U) << 0U;
+}
+static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr_m(void)
+{
+	return 0x1U << 0U;
+}
+static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr_v(u32 r)
+{
+	return (r >> 0U) & 0x1U;
+}
+static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr__prod_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr__prod_f(void)
+{
+	return 0x1U;
+}
+static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_f(u32 v)
+{
+	return (v & 0x1U) << 1U;
+}
+static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_m(void)
+{
+	return 0x1U << 1U;
+}
+static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_v(u32 r)
+{
+	return (r >> 1U) & 0x1U;
+}
+static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr__prod_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr__prod_f(void)
+{
+	return 0x2U;
+}
+static inline u32 ioctrlmif_tx_err_log_en_0_r(void)
+{
+	return 0x00000a88U;
+}
+static inline u32 ioctrlmif_tx_err_log_en_0_txramdataparityerr_f(u32 v)
+{
+	return (v & 0x1U) << 0U;
+}
+static inline u32 ioctrlmif_tx_err_log_en_0_txramdataparityerr_m(void)
+{
+	return 0x1U << 0U;
+}
+static inline u32 ioctrlmif_tx_err_log_en_0_txramdataparityerr_v(u32 r)
+{
+	return (r >> 0U) & 0x1U;
+}
+static inline u32 ioctrlmif_tx_err_log_en_0_txramhdrparityerr_f(u32 v)
+{
+	return (v & 0x1U) << 1U;
+}
+static inline u32 ioctrlmif_tx_err_log_en_0_txramhdrparityerr_m(void)
+{
+	return 0x1U << 1U;
+}
+static inline u32 ioctrlmif_tx_err_log_en_0_txramhdrparityerr_v(u32 r)
+{
+	return (r >> 1U) & 0x1U;
+}
+static inline u32 ioctrlmif_tx_err_report_en_0_r(void)
+{
+	return 0x00000e08U;
+}
+static inline u32 ioctrlmif_tx_err_report_en_0_txramdataparityerr_f(u32 v)
+{
+	return (v & 0x1U) << 0U;
+}
+static inline u32 ioctrlmif_tx_err_report_en_0_txramdataparityerr_m(void)
+{
+	return 0x1U << 0U;
+}
+static inline u32 ioctrlmif_tx_err_report_en_0_txramdataparityerr_v(u32 r)
+{
+	return (r >> 0U) & 0x1U;
+}
+static inline u32 ioctrlmif_tx_err_report_en_0_txramhdrparityerr_f(u32 v)
+{
+	return (v & 0x1U) << 1U;
+}
+static inline u32 ioctrlmif_tx_err_report_en_0_txramhdrparityerr_m(void)
+{
+	return 0x1U << 1U;
+}
+static inline u32 ioctrlmif_tx_err_report_en_0_txramhdrparityerr_v(u32 r)
+{
+	return (r >> 1U) & 0x1U;
+}
+static inline u32 ioctrlmif_tx_err_status_0_r(void)
+{
+	return 0x00000a84U;
+}
+static inline u32 ioctrlmif_tx_err_status_0_txramdataparityerr_f(u32 v)
+{
+	return (v & 0x1U) << 0U;
+}
+static inline u32 ioctrlmif_tx_err_status_0_txramdataparityerr_m(void)
+{
+	return 0x1U << 0U;
+}
+static inline u32 ioctrlmif_tx_err_status_0_txramdataparityerr_v(u32 r)
+{
+	return (r >> 0U) & 0x1U;
+}
+static inline u32 ioctrlmif_tx_err_status_0_txramhdrparityerr_f(u32 v)
+{
+	return (v & 0x1U) << 1U;
+}
+static inline u32 ioctrlmif_tx_err_status_0_txramhdrparityerr_m(void)
+{
+	return 0x1U << 1U;
+}
+static inline u32 ioctrlmif_tx_err_status_0_txramhdrparityerr_v(u32 r)
+{
+	return (r >> 1U) & 0x1U;
+}
+static inline u32 ioctrlmif_tx_err_first_0_r(void)
+{
+	return 0x00000a98U;
+}
+static inline u32 ioctrlmif_tx_ctrl_buffer_ready_r(void)
+{
+	return 0x00000a7cU;
+}
+static inline u32 ioctrlmif_rx_ctrl_buffer_ready_r(void)
+{
+	return 0x00000dfcU;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h
index f367991e..fb558d2f 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_mc_gv100.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -108,6 +108,10 @@ static inline u32 mc_intr_pbus_pending_f(void)
 {
 	return 0x10000000U;
 }
+static inline u32 mc_intr_nvlink_pending_f(void)
+{
+	return 0x400000U;
+}
 static inline u32 mc_intr_en_r(u32 i)
 {
 	return 0x00000140U + i*4U;
@@ -204,6 +208,22 @@ static inline u32 mc_enable_nvdec_enabled_f(void)
 {
 	return 0x8000U;
 }
+static inline u32 mc_enable_nvlink_disabled_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 mc_enable_nvlink_disabled_f(void)
+{
+	return 0x0U;
+}
+static inline u32 mc_enable_nvlink_enabled_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 mc_enable_nvlink_enabled_f(void)
+{
+	return 0x2000000U;
+}
 static inline u32 mc_intr_ltc_r(void)
 {
 	return 0x000001c0U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_minion_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_minion_gv100.h
new file mode 100644
index 00000000..c59a6e6b
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_minion_gv100.h
@@ -0,0 +1,919 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_minion_gv100_h_
+#define _hw_minion_gv100_h_
+
+static inline u32 minion_minion_status_r(void)
+{
+	return 0x00000830U;
+}
+static inline u32 minion_minion_status_status_f(u32 v)
+{
+	return (v & 0xffU) << 0U;
+}
+static inline u32 minion_minion_status_status_m(void)
+{
+	return 0xffU << 0U;
+}
+static inline u32 minion_minion_status_status_v(u32 r)
+{
+	return (r >> 0U) & 0xffU;
+}
+static inline u32 minion_minion_status_status_boot_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 minion_minion_status_status_boot_f(void)
+{
+	return 0x1U;
+}
+static inline u32 minion_minion_status_intr_code_f(u32 v)
+{
+	return (v & 0xffffffU) << 8U;
+}
+static inline u32 minion_minion_status_intr_code_m(void)
+{
+	return 0xffffffU << 8U;
+}
+static inline u32 minion_minion_status_intr_code_v(u32 r)
+{
+	return (r >> 8U) & 0xffffffU;
+}
+static inline u32 minion_falcon_irqstat_r(void)
+{
+	return 0x00000008U;
+}
+static inline u32 minion_falcon_irqstat_halt_f(u32 v)
+{
+	return (v & 0x1U) << 4U;
+}
+static inline u32 minion_falcon_irqstat_halt_v(u32 r)
+{
+	return (r >> 4U) & 0x1U;
+}
+static inline u32 minion_falcon_irqmask_r(void)
+{
+	return 0x00000018U;
+}
+static inline u32 minion_falcon_irqsclr_r(void)
+{
+	return 0x00000004U;
+}
+static inline u32 minion_falcon_irqsset_r(void)
+{
+	return 0x00000000U;
+}
+static inline u32 minion_falcon_irqmset_r(void)
+{
+	return 0x00000010U;
+}
+static inline u32 minion_falcon_irqmset_wdtmr_f(u32 v)
+{
+	return (v & 0x1U) << 1U;
+}
+static inline u32 minion_falcon_irqmset_wdtmr_m(void)
+{
+	return 0x1U << 1U;
+}
+static inline u32 minion_falcon_irqmset_wdtmr_v(u32 r)
+{
+	return (r >> 1U) & 0x1U;
+}
+static inline u32 minion_falcon_irqmset_wdtmr_set_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 minion_falcon_irqmset_wdtmr_set_f(void)
+{
+	return 0x2U;
+}
+static inline u32 minion_falcon_irqmset_halt_f(u32 v)
+{
+	return (v & 0x1U) << 4U;
+}
+static inline u32 minion_falcon_irqmset_halt_m(void)
+{
+	return 0x1U << 4U;
+}
+static inline u32 minion_falcon_irqmset_halt_v(u32 r)
+{
+	return (r >> 4U) & 0x1U;
+}
+static inline u32 minion_falcon_irqmset_halt_set_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 minion_falcon_irqmset_halt_set_f(void)
+{
+	return 0x10U;
+}
+static inline u32 minion_falcon_irqmset_exterr_f(u32 v)
+{
+	return (v & 0x1U) << 5U;
+}
+static inline u32 minion_falcon_irqmset_exterr_m(void)
+{
+	return 0x1U << 5U;
+}
+static inline u32 minion_falcon_irqmset_exterr_v(u32 r)
+{
+	return (r >> 5U) & 0x1U;
+}
+static inline u32 minion_falcon_irqmset_exterr_set_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 minion_falcon_irqmset_exterr_set_f(void)
+{
+	return 0x20U;
+}
+static inline u32 minion_falcon_irqmset_swgen0_f(u32 v)
+{
+	return (v & 0x1U) << 6U;
+}
+static inline u32 minion_falcon_irqmset_swgen0_m(void)
+{
+	return 0x1U << 6U;
+}
+static inline u32 minion_falcon_irqmset_swgen0_v(u32 r)
+{
+	return (r >> 6U) & 0x1U;
+}
+static inline u32 minion_falcon_irqmset_swgen0_set_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 minion_falcon_irqmset_swgen0_set_f(void)
+{
+	return 0x40U;
+}
+static inline u32 minion_falcon_irqmset_swgen1_f(u32 v)
+{
+	return (v & 0x1U) << 7U;
+}
+static inline u32 minion_falcon_irqmset_swgen1_m(void)
+{
+	return 0x1U << 7U;
+}
+static inline u32 minion_falcon_irqmset_swgen1_v(u32 r)
+{
+	return (r >> 7U) & 0x1U;
+}
+static inline u32 minion_falcon_irqmset_swgen1_set_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 minion_falcon_irqmset_swgen1_set_f(void)
+{
+	return 0x80U;
+}
+static inline u32 minion_falcon_irqdest_r(void)
+{
+	return 0x0000001cU;
+}
+static inline u32 minion_falcon_irqdest_host_wdtmr_f(u32 v)
+{
+	return (v & 0x1U) << 1U;
+}
+static inline u32 minion_falcon_irqdest_host_wdtmr_m(void)
+{
+	return 0x1U << 1U;
+}
+static inline u32 minion_falcon_irqdest_host_wdtmr_v(u32 r)
+{
+	return (r >> 1U) & 0x1U;
+}
+static inline u32 minion_falcon_irqdest_host_wdtmr_host_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 minion_falcon_irqdest_host_wdtmr_host_f(void)
+{
+	return 0x2U;
+}
+static inline u32 minion_falcon_irqdest_host_halt_f(u32 v)
+{
+	return (v & 0x1U) << 4U;
+}
+static inline u32 minion_falcon_irqdest_host_halt_m(void)
+{
+	return 0x1U << 4U;
+}
+static inline u32 minion_falcon_irqdest_host_halt_v(u32 r)
+{
+	return (r >> 4U) & 0x1U;
+}
+static inline u32 minion_falcon_irqdest_host_halt_host_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 minion_falcon_irqdest_host_halt_host_f(void)
+{
+	return 0x10U;
+}
+static inline u32 minion_falcon_irqdest_host_exterr_f(u32 v)
+{
+	return (v & 0x1U) << 5U;
+}
+static inline u32 minion_falcon_irqdest_host_exterr_m(void)
+{
+	return 0x1U << 5U;
+}
+static inline u32 minion_falcon_irqdest_host_exterr_v(u32 r)
+{
+	return (r >> 5U) & 0x1U;
+}
+static inline u32 minion_falcon_irqdest_host_exterr_host_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 minion_falcon_irqdest_host_exterr_host_f(void)
+{
+	return 0x20U;
+}
+static inline u32 minion_falcon_irqdest_host_swgen0_f(u32 v)
+{
+	return (v & 0x1U) << 6U;
+}
+static inline u32 minion_falcon_irqdest_host_swgen0_m(void)
+{
+	return 0x1U << 6U;
+}
+static inline u32 minion_falcon_irqdest_host_swgen0_v(u32 r)
+{
+	return (r >> 6U) & 0x1U;
+}
+static inline u32 minion_falcon_irqdest_host_swgen0_host_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 minion_falcon_irqdest_host_swgen0_host_f(void)
+{
+	return 0x40U;
+}
+static inline u32 minion_falcon_irqdest_host_swgen1_f(u32 v)
+{
+	return (v & 0x1U) << 7U;
+}
+static inline u32 minion_falcon_irqdest_host_swgen1_m(void)
+{
+	return 0x1U << 7U;
+}
+static inline u32 minion_falcon_irqdest_host_swgen1_v(u32 r)
+{
+	return (r >> 7U) & 0x1U;
+}
+static inline u32 minion_falcon_irqdest_host_swgen1_host_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 minion_falcon_irqdest_host_swgen1_host_f(void)
+{
+	return 0x80U;
+}
+static inline u32 minion_falcon_irqdest_target_wdtmr_f(u32 v)
+{
+	return (v & 0x1U) << 17U;
+}
+static inline u32 minion_falcon_irqdest_target_wdtmr_m(void)
+{
+	return 0x1U << 17U;
+}
+static inline u32 minion_falcon_irqdest_target_wdtmr_v(u32 r)
+{
+	return (r >> 17U) & 0x1U;
+}
+static inline u32 minion_falcon_irqdest_target_wdtmr_host_normal_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 minion_falcon_irqdest_target_wdtmr_host_normal_f(void)
+{
+	return 0x0U;
+}
+static inline u32 minion_falcon_irqdest_target_halt_f(u32 v)
+{
+	return (v & 0x1U) << 20U;
+}
+static inline u32 minion_falcon_irqdest_target_halt_m(void)
+{
+	return 0x1U << 20U;
+}
+static inline u32 minion_falcon_irqdest_target_halt_v(u32 r)
+{
+	return (r >> 20U) & 0x1U;
+}
+static inline u32 minion_falcon_irqdest_target_halt_host_normal_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 minion_falcon_irqdest_target_halt_host_normal_f(void)
+{
+	return 0x0U;
+}
+static inline u32 minion_falcon_irqdest_target_exterr_f(u32 v)
+{
+	return (v & 0x1U) << 21U;
+}
+static inline u32 minion_falcon_irqdest_target_exterr_m(void)
+{
+	return 0x1U << 21U;
+}
+static inline u32 minion_falcon_irqdest_target_exterr_v(u32 r)
+{
+	return (r >> 21U) & 0x1U;
+}
+static inline u32 minion_falcon_irqdest_target_exterr_host_normal_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 minion_falcon_irqdest_target_exterr_host_normal_f(void)
+{
+	return 0x0U;
+}
+static inline u32 minion_falcon_irqdest_target_swgen0_f(u32 v)
+{
+	return (v & 0x1U) << 22U;
+}
+static inline u32 minion_falcon_irqdest_target_swgen0_m(void)
+{
+	return 0x1U << 22U;
+}
+static inline u32 minion_falcon_irqdest_target_swgen0_v(u32 r)
+{
+	return (r >> 22U) & 0x1U;
+}
+static inline u32 minion_falcon_irqdest_target_swgen0_host_normal_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 minion_falcon_irqdest_target_swgen0_host_normal_f(void)
+{
+	return 0x0U;
+}
+static inline u32 minion_falcon_irqdest_target_swgen1_f(u32 v)
+{
+	return (v & 0x1U) << 23U;
+}
+static inline u32 minion_falcon_irqdest_target_swgen1_m(void)
+{
+	return 0x1U << 23U;
+}
+static inline u32 minion_falcon_irqdest_target_swgen1_v(u32 r)
+{
+	return (r >> 23U) & 0x1U;
+}
+static inline u32 minion_falcon_irqdest_target_swgen1_host_normal_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 minion_falcon_irqdest_target_swgen1_host_normal_f(void)
+{
+	return 0x0U;
+}
+static inline u32 minion_falcon_os_r(void)
+{
+	return 0x00000080U;
+}
+static inline u32 minion_falcon_mailbox1_r(void)
+{
+	return 0x00000044U;
+}
+static inline u32 minion_minion_intr_r(void)
+{
+	return 0x00000810U;
+}
+static inline u32 minion_minion_intr_fatal_f(u32 v)
+{
+	return (v & 0x1U) << 0U;
+}
+static inline u32 minion_minion_intr_fatal_m(void)
+{
+	return 0x1U << 0U;
+}
+static inline u32 minion_minion_intr_fatal_v(u32 r)
+{
+	return (r >> 0U) & 0x1U;
+}
+static inline u32 minion_minion_intr_nonfatal_f(u32 v)
+{
+	return (v & 0x1U) << 1U;
+}
+static inline u32 minion_minion_intr_nonfatal_m(void)
+{
+	return 0x1U << 1U;
+}
+static inline u32 minion_minion_intr_nonfatal_v(u32 r)
+{
+	return (r >> 1U) & 0x1U;
+}
+static inline u32 minion_minion_intr_falcon_stall_f(u32 v)
+{
+	return (v & 0x1U) << 2U;
+}
+static inline u32 minion_minion_intr_falcon_stall_m(void)
+{
+	return 0x1U << 2U;
+}
+static inline u32 minion_minion_intr_falcon_stall_v(u32 r)
+{
+	return (r >> 2U) & 0x1U;
+}
+static inline u32 minion_minion_intr_falcon_nostall_f(u32 v)
+{
+	return (v & 0x1U) << 3U;
+}
+static inline u32 minion_minion_intr_falcon_nostall_m(void)
+{
+	return 0x1U << 3U;
+}
+static inline u32 minion_minion_intr_falcon_nostall_v(u32 r)
+{
+	return (r >> 3U) & 0x1U;
+}
+static inline u32 minion_minion_intr_link_f(u32 v)
+{
+	return (v & 0xffffU) << 16U;
+}
+static inline u32 minion_minion_intr_link_m(void)
+{
+	return 0xffffU << 16U;
+}
+static inline u32 minion_minion_intr_link_v(u32 r)
+{
+	return (r >> 16U) & 0xffffU;
+}
+static inline u32 minion_minion_intr_nonstall_en_r(void)
+{
+	return 0x0000081cU;
+}
+static inline u32 minion_minion_intr_stall_en_r(void)
+{
+	return 0x00000818U;
+}
+static inline u32 minion_minion_intr_stall_en_fatal_f(u32 v)
+{
+	return (v & 0x1U) << 0U;
+}
+static inline u32 minion_minion_intr_stall_en_fatal_m(void)
+{
+	return 0x1U << 0U;
+}
+static inline u32 minion_minion_intr_stall_en_fatal_v(u32 r)
+{
+	return (r >> 0U) & 0x1U;
+}
+static inline u32 minion_minion_intr_stall_en_fatal_enable_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 minion_minion_intr_stall_en_fatal_enable_f(void)
+{
+	return 0x1U;
+}
+static inline u32 minion_minion_intr_stall_en_fatal_disable_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 minion_minion_intr_stall_en_fatal_disable_f(void)
+{
+	return 0x0U;
+}
+static inline u32 minion_minion_intr_stall_en_nonfatal_f(u32 v)
+{
+	return (v & 0x1U) << 1U;
+}
+static inline u32 minion_minion_intr_stall_en_nonfatal_m(void)
+{
+	return 0x1U << 1U;
+}
+static inline u32 minion_minion_intr_stall_en_nonfatal_v(u32 r)
+{
+	return (r >> 1U) & 0x1U;
+}
+static inline u32 minion_minion_intr_stall_en_nonfatal_enable_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 minion_minion_intr_stall_en_nonfatal_enable_f(void)
+{
+	return 0x2U;
+}
+static inline u32 minion_minion_intr_stall_en_nonfatal_disable_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 minion_minion_intr_stall_en_nonfatal_disable_f(void)
+{
+	return 0x0U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_stall_f(u32 v)
+{
+	return (v & 0x1U) << 2U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_stall_m(void)
+{
+	return 0x1U << 2U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_stall_v(u32 r)
+{
+	return (r >> 2U) & 0x1U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_stall_enable_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_stall_enable_f(void)
+{
+	return 0x4U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_stall_disable_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_stall_disable_f(void)
+{
+	return 0x0U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_nostall_f(u32 v)
+{
+	return (v & 0x1U) << 3U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_nostall_m(void)
+{
+	return 0x1U << 3U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_nostall_v(u32 r)
+{
+	return (r >> 3U) & 0x1U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_nostall_enable_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_nostall_enable_f(void)
+{
+	return 0x8U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_nostall_disable_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_nostall_disable_f(void)
+{
+	return 0x0U;
+}
+static inline u32 minion_minion_intr_stall_en_link_f(u32 v)
+{
+	return (v & 0xffffU) << 16U;
+}
+static inline u32 minion_minion_intr_stall_en_link_m(void)
+{
+	return 0xffffU << 16U;
+}
+static inline u32 minion_minion_intr_stall_en_link_v(u32 r)
+{
+	return (r >> 16U) & 0xffffU;
+}
+static inline u32 minion_nvlink_dl_cmd_r(u32 i)
+{
+	return 0x00000900U + i*4U;
+}
+static inline u32 minion_nvlink_dl_cmd___size_1_v(void)
+{
+	return 0x00000006U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_f(u32 v)
+{
+	return (v & 0xffU) << 0U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_v(u32 r)
+{
+	return (r >> 0U) & 0xffU;
+}
+static inline u32 minion_nvlink_dl_cmd_command_configeom_v(void)
+{
+	return 0x00000040U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_configeom_f(void)
+{
+	return 0x40U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_nop_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_nop_f(void)
+{
+	return 0x0U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initphy_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initphy_f(void)
+{
+	return 0x1U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initlaneenable_v(void)
+{
+	return 0x00000003U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initlaneenable_f(void)
+{
+	return 0x3U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initdlpl_v(void)
+{
+	return 0x00000004U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initdlpl_f(void)
+{
+	return 0x4U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_lanedisable_v(void)
+{
+	return 0x00000008U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_lanedisable_f(void)
+{
+	return 0x8U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_fastlanedisable_v(void)
+{
+	return 0x00000009U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_fastlanedisable_f(void)
+{
+	return 0x9U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_laneshutdown_v(void)
+{
+	return 0x0000000cU;
+}
+static inline u32 minion_nvlink_dl_cmd_command_laneshutdown_f(void)
+{
+	return 0xcU;
+}
+static inline u32 minion_nvlink_dl_cmd_command_setacmode_v(void)
+{
+	return 0x0000000aU;
+}
+static inline u32 minion_nvlink_dl_cmd_command_setacmode_f(void)
+{
+	return 0xaU;
+}
+static inline u32 minion_nvlink_dl_cmd_command_clracmode_v(void)
+{
+	return 0x0000000bU;
+}
+static inline u32 minion_nvlink_dl_cmd_command_clracmode_f(void)
+{
+	return 0xbU;
+}
+static inline u32 minion_nvlink_dl_cmd_command_enablepm_v(void)
+{
+	return 0x00000010U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_enablepm_f(void)
+{
+	return 0x10U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_disablepm_v(void)
+{
+	return 0x00000011U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_disablepm_f(void)
+{
+	return 0x11U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_savestate_v(void)
+{
+	return 0x00000018U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_savestate_f(void)
+{
+	return 0x18U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_restorestate_v(void)
+{
+	return 0x00000019U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_restorestate_f(void)
+{
+	return 0x19U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_0_v(void)
+{
+	return 0x00000020U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_0_f(void)
+{
+	return 0x20U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_1_v(void)
+{
+	return 0x00000021U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_1_f(void)
+{
+	return 0x21U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_2_v(void)
+{
+	return 0x00000022U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_2_f(void)
+{
+	return 0x22U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_3_v(void)
+{
+	return 0x00000023U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_3_f(void)
+{
+	return 0x23U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_4_v(void)
+{
+	return 0x00000024U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_4_f(void)
+{
+	return 0x24U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_5_v(void)
+{
+	return 0x00000025U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_5_f(void)
+{
+	return 0x25U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_6_v(void)
+{
+	return 0x00000026U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_6_f(void)
+{
+	return 0x26U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_7_v(void)
+{
+	return 0x00000027U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_7_f(void)
+{
+	return 0x27U;
+}
+static inline u32 minion_nvlink_dl_cmd_fault_f(u32 v)
+{
+	return (v & 0x1U) << 30U;
+}
+static inline u32 minion_nvlink_dl_cmd_fault_v(u32 r)
+{
+	return (r >> 30U) & 0x1U;
+}
+static inline u32 minion_nvlink_dl_cmd_ready_f(u32 v)
+{
+	return (v & 0x1U) << 31U;
+}
+static inline u32 minion_nvlink_dl_cmd_ready_v(u32 r)
+{
+	return (r >> 31U) & 0x1U;
+}
+static inline u32 minion_misc_0_r(void)
+{
+	return 0x000008b0U;
+}
+static inline u32 minion_misc_0_scratch_swrw_0_f(u32 v)
+{
+	return (v & 0xffffffffU) << 0U;
+}
+static inline u32 minion_misc_0_scratch_swrw_0_v(u32 r)
+{
+	return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 minion_nvlink_link_intr_r(u32 i)
+{
+	return 0x00000a00U + i*4U;
+}
+static inline u32 minion_nvlink_link_intr___size_1_v(void)
+{
+	return 0x00000006U;
+}
+static inline u32 minion_nvlink_link_intr_code_f(u32 v)
+{
+	return (v & 0xffU) << 0U;
+}
+static inline u32 minion_nvlink_link_intr_code_m(void)
+{
+	return 0xffU << 0U;
+}
+static inline u32 minion_nvlink_link_intr_code_v(u32 r)
+{
+	return (r >> 0U) & 0xffU;
+}
+static inline u32 minion_nvlink_link_intr_code_na_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 minion_nvlink_link_intr_code_na_f(void)
+{
+	return 0x0U;
+}
+static inline u32 minion_nvlink_link_intr_code_swreq_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 minion_nvlink_link_intr_code_swreq_f(void)
+{
+	return 0x1U;
+}
+static inline u32 minion_nvlink_link_intr_code_dlreq_v(void)
+{
+	return 0x00000002U;
+}
+static inline u32 minion_nvlink_link_intr_code_dlreq_f(void)
+{
+	return 0x2U;
+}
+static inline u32 minion_nvlink_link_intr_subcode_f(u32 v)
+{
+	return (v & 0xffU) << 8U;
+}
+static inline u32 minion_nvlink_link_intr_subcode_m(void)
+{
+	return 0xffU << 8U;
+}
+static inline u32 minion_nvlink_link_intr_subcode_v(u32 r)
+{
+	return (r >> 8U) & 0xffU;
+}
+static inline u32 minion_nvlink_link_intr_state_f(u32 v)
+{
+	return (v & 0x1U) << 31U;
+}
+static inline u32 minion_nvlink_link_intr_state_m(void)
+{
+	return 0x1U << 31U;
+}
+static inline u32 minion_nvlink_link_intr_state_v(u32 r)
+{
+	return (r >> 31U) & 0x1U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvl_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvl_gv100.h
new file mode 100644
index 00000000..2e4ec168
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvl_gv100.h
@@ -0,0 +1,1571 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_nvl_gv100_h_
+#define _hw_nvl_gv100_h_
+
+static inline u32 nvl_link_state_r(void)
+{
+	return 0x00000000U;
+}
+static inline u32 nvl_link_state_state_f(u32 v)
+{
+	return (v & 0xffU) << 0U;
+}
+static inline u32 nvl_link_state_state_m(void)
+{
+	return 0xffU << 0U;
+}
+static inline u32 nvl_link_state_state_v(u32 r)
+{
+	return (r >> 0U) & 0xffU;
+}
+static inline u32 nvl_link_state_state_init_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 nvl_link_state_state_init_f(void)
+{
+	return 0x0U;
+}
+static inline u32 nvl_link_state_state_hwcfg_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_link_state_state_hwcfg_f(void)
+{
+	return 0x1U;
+}
+static inline u32 nvl_link_state_state_swcfg_v(void)
+{
+	return 0x00000002U;
+}
+static inline u32 nvl_link_state_state_swcfg_f(void)
+{
+	return 0x2U;
+}
+static inline u32 nvl_link_state_state_active_v(void)
+{
+	return 0x00000003U;
+}
+static inline u32 nvl_link_state_state_active_f(void)
+{
+	return 0x3U;
+}
+static inline u32 nvl_link_state_state_fault_v(void)
+{
+	return 0x00000004U;
+}
+static inline u32 nvl_link_state_state_fault_f(void)
+{
+	return 0x4U;
+}
+static inline u32 nvl_link_state_state_rcvy_ac_v(void)
+{
+	return 0x00000008U;
+}
+static inline u32 nvl_link_state_state_rcvy_ac_f(void)
+{
+	return 0x8U;
+}
+static inline u32 nvl_link_state_state_rcvy_sw_v(void)
+{
+	return 0x00000009U;
+}
+static inline u32 nvl_link_state_state_rcvy_sw_f(void)
+{
+	return 0x9U;
+}
+static inline u32 nvl_link_state_state_rcvy_rx_v(void)
+{
+	return 0x0000000aU;
+}
+static inline u32 nvl_link_state_state_rcvy_rx_f(void)
+{
+	return 0xaU;
+}
+static inline u32 nvl_link_state_an0_busy_f(u32 v)
+{
+	return (v & 0x1U) << 12U;
+}
+static inline u32 nvl_link_state_an0_busy_m(void)
+{
+	return 0x1U << 12U;
+}
+static inline u32 nvl_link_state_an0_busy_v(u32 r)
+{
+	return (r >> 12U) & 0x1U;
+}
+static inline u32 nvl_link_state_tl_busy_f(u32 v)
+{
+	return (v & 0x1U) << 13U;
+}
+static inline u32 nvl_link_state_tl_busy_m(void)
+{
+	return 0x1U << 13U;
+}
+static inline u32 nvl_link_state_tl_busy_v(u32 r)
+{
+	return (r >> 13U) & 0x1U;
+}
+static inline u32 nvl_link_state_dbg_substate_f(u32 v)
+{
+	return (v & 0xffffU) << 16U;
+}
+static inline u32 nvl_link_state_dbg_substate_m(void)
+{
+	return 0xffffU << 16U;
+}
+static inline u32 nvl_link_state_dbg_substate_v(u32 r)
+{
+	return (r >> 16U) & 0xffffU;
+}
+static inline u32 nvl_link_activity_r(void)
+{
+	return 0x0000000cU;
+}
+static inline u32 nvl_link_activity_blkact_f(u32 v)
+{
+	return (v & 0x7U) << 0U;
+}
+static inline u32 nvl_link_activity_blkact_m(void)
+{
+	return 0x7U << 0U;
+}
+static inline u32 nvl_link_activity_blkact_v(u32 r)
+{
+	return (r >> 0U) & 0x7U;
+}
+static inline u32 nvl_sublink_activity_r(u32 i)
+{
+	return 0x00000010U + i*4U;
+}
+static inline u32 nvl_sublink_activity_blkact0_f(u32 v)
+{
+	return (v & 0x7U) << 0U;
+}
+static inline u32 nvl_sublink_activity_blkact0_m(void)
+{
+	return 0x7U << 0U;
+}
+static inline u32 nvl_sublink_activity_blkact0_v(u32 r)
+{
+	return (r >> 0U) & 0x7U;
+}
+static inline u32 nvl_sublink_activity_blkact1_f(u32 v)
+{
+	return (v & 0x7U) << 8U;
+}
+static inline u32 nvl_sublink_activity_blkact1_m(void)
+{
+	return 0x7U << 8U;
+}
+static inline u32 nvl_sublink_activity_blkact1_v(u32 r)
+{
+	return (r >> 8U) & 0x7U;
+}
+static inline u32 nvl_link_config_r(void)
+{
+	return 0x00000018U;
+}
+static inline u32 nvl_link_config_ac_safe_en_f(u32 v)
+{
+	return (v & 0x1U) << 30U;
+}
+static inline u32 nvl_link_config_ac_safe_en_m(void)
+{
+	return 0x1U << 30U;
+}
+static inline u32 nvl_link_config_ac_safe_en_v(u32 r)
+{
+	return (r >> 30U) & 0x1U;
+}
+static inline u32 nvl_link_config_ac_safe_en_on_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_link_config_ac_safe_en_on_f(void)
+{
+	return 0x40000000U;
+}
+static inline u32 nvl_link_config_link_en_f(u32 v)
+{
+	return (v & 0x1U) << 31U;
+}
+static inline u32 nvl_link_config_link_en_m(void)
+{
+	return 0x1U << 31U;
+}
+static inline u32 nvl_link_config_link_en_v(u32 r)
+{
+	return (r >> 31U) & 0x1U;
+}
+static inline u32 nvl_link_config_link_en_on_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_link_config_link_en_on_f(void)
+{
+	return 0x80000000U;
+}
+static inline u32 nvl_link_change_r(void)
+{
+	return 0x00000040U;
+}
+static inline u32 nvl_link_change_oldstate_mask_f(u32 v)
+{
+	return (v & 0xfU) << 16U;
+}
+static inline u32 nvl_link_change_oldstate_mask_m(void)
+{
+	return 0xfU << 16U;
+}
+static inline u32 nvl_link_change_oldstate_mask_v(u32 r)
+{
+	return (r >> 16U) & 0xfU;
+}
+static inline u32 nvl_link_change_oldstate_mask_dontcare_v(void)
+{
+	return 0x0000000fU;
+}
+static inline u32 nvl_link_change_oldstate_mask_dontcare_f(void)
+{
+	return 0xf0000U;
+}
+static inline u32 nvl_link_change_newstate_f(u32 v)
+{
+	return (v & 0xfU) << 4U;
+}
+static inline u32 nvl_link_change_newstate_m(void)
+{
+	return 0xfU << 4U;
+}
+static inline u32 nvl_link_change_newstate_v(u32 r)
+{
+	return (r >> 4U) & 0xfU;
+}
+static inline u32 nvl_link_change_newstate_hwcfg_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_link_change_newstate_hwcfg_f(void)
+{
+	return 0x10U;
+}
+static inline u32 nvl_link_change_newstate_swcfg_v(void)
+{
+	return 0x00000002U;
+}
+static inline u32 nvl_link_change_newstate_swcfg_f(void)
+{
+	return 0x20U;
+}
+static inline u32 nvl_link_change_newstate_active_v(void)
+{
+	return 0x00000003U;
+}
+static inline u32 nvl_link_change_newstate_active_f(void)
+{
+	return 0x30U;
+}
+static inline u32 nvl_link_change_action_f(u32 v)
+{
+	return (v & 0x3U) << 2U;
+}
+static inline u32 nvl_link_change_action_m(void)
+{
+	return 0x3U << 2U;
+}
+static inline u32 nvl_link_change_action_v(u32 r)
+{
+	return (r >> 2U) & 0x3U;
+}
+static inline u32 nvl_link_change_action_ltssm_change_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_link_change_action_ltssm_change_f(void)
+{
+	return 0x4U;
+}
+static inline u32 nvl_link_change_status_f(u32 v)
+{
+	return (v & 0x3U) << 0U;
+}
+static inline u32 nvl_link_change_status_m(void)
+{
+	return 0x3U << 0U;
+}
+static inline u32 nvl_link_change_status_v(u32 r)
+{
+	return (r >> 0U) & 0x3U;
+}
+static inline u32 nvl_link_change_status_done_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 nvl_link_change_status_done_f(void)
+{
+	return 0x0U;
+}
+static inline u32 nvl_link_change_status_busy_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_link_change_status_busy_f(void)
+{
+	return 0x1U;
+}
+static inline u32 nvl_link_change_status_fault_v(void)
+{
+	return 0x00000002U;
+}
+static inline u32 nvl_link_change_status_fault_f(void)
+{
+	return 0x2U;
+}
+static inline u32 nvl_sublink_change_r(void)
+{
+	return 0x00000044U;
+}
+static inline u32 nvl_sublink_change_countdown_f(u32 v)
+{
+	return (v & 0xfffU) << 20U;
+}
+static inline u32 nvl_sublink_change_countdown_m(void)
+{
+	return 0xfffU << 20U;
+}
+static inline u32 nvl_sublink_change_countdown_v(u32 r)
+{
+	return (r >> 20U) & 0xfffU;
+}
+static inline u32 nvl_sublink_change_oldstate_mask_f(u32 v)
+{
+	return (v & 0xfU) << 16U;
+}
+static inline u32 nvl_sublink_change_oldstate_mask_m(void)
+{
+	return 0xfU << 16U;
+}
+static inline u32 nvl_sublink_change_oldstate_mask_v(u32 r)
+{
+	return (r >> 16U) & 0xfU;
+}
+static inline u32 nvl_sublink_change_oldstate_mask_dontcare_v(void)
+{
+	return 0x0000000fU;
+}
+static inline u32 nvl_sublink_change_oldstate_mask_dontcare_f(void)
+{
+	return 0xf0000U;
+}
+static inline u32 nvl_sublink_change_sublink_f(u32 v)
+{
+	return (v & 0xfU) << 12U;
+}
+static inline u32 nvl_sublink_change_sublink_m(void)
+{
+	return 0xfU << 12U;
+}
+static inline u32 nvl_sublink_change_sublink_v(u32 r)
+{
+	return (r >> 12U) & 0xfU;
+}
+static inline u32 nvl_sublink_change_sublink_tx_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 nvl_sublink_change_sublink_tx_f(void)
+{
+	return 0x0U;
+}
+static inline u32 nvl_sublink_change_sublink_rx_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_sublink_change_sublink_rx_f(void)
+{
+	return 0x1000U;
+}
+static inline u32 nvl_sublink_change_newstate_f(u32 v)
+{
+	return (v & 0xfU) << 4U;
+}
+static inline u32 nvl_sublink_change_newstate_m(void)
+{
+	return 0xfU << 4U;
+}
+static inline u32 nvl_sublink_change_newstate_v(u32 r)
+{
+	return (r >> 4U) & 0xfU;
+}
+static inline u32 nvl_sublink_change_newstate_hs_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 nvl_sublink_change_newstate_hs_f(void)
+{
+	return 0x0U;
+}
+static inline u32 nvl_sublink_change_newstate_eighth_v(void)
+{
+	return 0x00000004U;
+}
+static inline u32 nvl_sublink_change_newstate_eighth_f(void)
+{
+	return 0x40U;
+}
+static inline u32 nvl_sublink_change_newstate_train_v(void)
+{
+	return 0x00000005U;
+}
+static inline u32 nvl_sublink_change_newstate_train_f(void)
+{
+	return 0x50U;
+}
+static inline u32 nvl_sublink_change_newstate_safe_v(void)
+{
+	return 0x00000006U;
+}
+static inline u32 nvl_sublink_change_newstate_safe_f(void)
+{
+	return 0x60U;
+}
+static inline u32 nvl_sublink_change_newstate_off_v(void)
+{
+	return 0x00000007U;
+}
+static inline u32 nvl_sublink_change_newstate_off_f(void)
+{
+	return 0x70U;
+}
+static inline u32 nvl_sublink_change_action_f(u32 v)
+{
+	return (v & 0x3U) << 2U;
+}
+static inline u32 nvl_sublink_change_action_m(void)
+{
+	return 0x3U << 2U;
+}
+static inline u32 nvl_sublink_change_action_v(u32 r)
+{
+	return (r >> 2U) & 0x3U;
+}
+static inline u32 nvl_sublink_change_action_slsm_change_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_sublink_change_action_slsm_change_f(void)
+{
+	return 0x4U;
+}
+static inline u32 nvl_sublink_change_status_f(u32 v)
+{
+	return (v & 0x3U) << 0U;
+}
+static inline u32 nvl_sublink_change_status_m(void)
+{
+	return 0x3U << 0U;
+}
+static inline u32 nvl_sublink_change_status_v(u32 r)
+{
+	return (r >> 0U) & 0x3U;
+}
+static inline u32 nvl_sublink_change_status_done_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 nvl_sublink_change_status_done_f(void)
+{
+	return 0x0U;
+}
+static inline u32 nvl_sublink_change_status_busy_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_sublink_change_status_busy_f(void)
+{
+	return 0x1U;
+}
+static inline u32 nvl_sublink_change_status_fault_v(void)
+{
+	return 0x00000002U;
+}
+static inline u32 nvl_sublink_change_status_fault_f(void)
+{
+	return 0x2U;
+}
+static inline u32 nvl_link_test_r(void)
+{
+	return 0x00000048U;
+}
+static inline u32 nvl_link_test_mode_f(u32 v)
+{
+	return (v & 0x1U) << 0U;
+}
+static inline u32 nvl_link_test_mode_m(void)
+{
+	return 0x1U << 0U;
+}
+static inline u32 nvl_link_test_mode_v(u32 r)
+{
+	return (r >> 0U) & 0x1U;
+}
+static inline u32 nvl_link_test_mode_enable_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_link_test_mode_enable_f(void)
+{
+	return 0x1U;
+}
+static inline u32 nvl_link_test_auto_hwcfg_f(u32 v)
+{
+	return (v & 0x1U) << 30U;
+}
+static inline u32 nvl_link_test_auto_hwcfg_m(void)
+{
+	return 0x1U << 30U;
+}
+static inline u32 nvl_link_test_auto_hwcfg_v(u32 r)
+{
+	return (r >> 30U) & 0x1U;
+}
+static inline u32 nvl_link_test_auto_hwcfg_enable_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_link_test_auto_hwcfg_enable_f(void)
+{
+	return 0x40000000U;
+}
+static inline u32 nvl_link_test_auto_nvhs_f(u32 v)
+{
+	return (v & 0x1U) << 31U;
+}
+static inline u32 nvl_link_test_auto_nvhs_m(void)
+{
+	return 0x1U << 31U;
+}
+static inline u32 nvl_link_test_auto_nvhs_v(u32 r)
+{
+	return (r >> 31U) & 0x1U;
+}
+static inline u32 nvl_link_test_auto_nvhs_enable_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_link_test_auto_nvhs_enable_f(void)
+{
+	return 0x80000000U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_r(void)
+{
+	return 0x00002024U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_substate_f(u32 v)
+{
+	return (v & 0xfU) << 0U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_substate_m(void)
+{
+	return 0xfU << 0U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_substate_v(u32 r)
+{
+	return (r >> 0U) & 0xfU;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_f(u32 v)
+{
+	return (v & 0xfU) << 4U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_m(void)
+{
+	return 0xfU << 4U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_v(u32 r)
+{
+	return (r >> 4U) & 0xfU;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_hs_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_hs_f(void)
+{
+	return 0x0U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_eighth_v(void)
+{
+	return 0x00000004U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_eighth_f(void)
+{
+	return 0x40U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_train_v(void)
+{
+	return 0x00000005U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_train_f(void)
+{
+	return 0x50U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_off_v(void)
+{
+	return 0x00000007U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_off_f(void)
+{
+	return 0x70U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_safe_v(void)
+{
+	return 0x00000006U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_safe_f(void)
+{
+	return 0x60U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_r(void)
+{
+	return 0x00003014U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_substate_f(u32 v)
+{
+	return (v & 0xfU) << 0U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_substate_m(void)
+{
+	return 0xfU << 0U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_substate_v(u32 r)
+{
+	return (r >> 0U) & 0xfU;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_f(u32 v)
+{
+	return (v & 0xfU) << 4U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_m(void)
+{
+	return 0xfU << 4U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_v(u32 r)
+{
+	return (r >> 4U) & 0xfU;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_hs_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_hs_f(void)
+{
+	return 0x0U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_eighth_v(void)
+{
+	return 0x00000004U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_eighth_f(void)
+{
+	return 0x40U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_train_v(void)
+{
+	return 0x00000005U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_train_f(void)
+{
+	return 0x50U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_off_v(void)
+{
+	return 0x00000007U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_off_f(void)
+{
+	return 0x70U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_safe_v(void)
+{
+	return 0x00000006U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_safe_f(void)
+{
+	return 0x60U;
+}
+static inline u32 nvl_sl0_safe_ctrl2_tx_r(void)
+{
+	return 0x00002008U;
+}
+static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_f(u32 v)
+{
+	return (v & 0x7ffU) << 0U;
+}
+static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_m(void)
+{
+	return 0x7ffU << 0U;
+}
+static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_v(u32 r)
+{
+	return (r >> 0U) & 0x7ffU;
+}
+static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_init_v(void)
+{
+	return 0x00000728U;
+}
+static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_init_f(void)
+{
+	return 0x728U;
+}
+static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_f(u32 v)
+{
+	return (v & 0x1fU) << 11U;
+}
+static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_m(void)
+{
+	return 0x1fU << 11U;
+}
+static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_v(u32 r)
+{
+	return (r >> 11U) & 0x1fU;
+}
+static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_v(void)
+{
+	return 0x0000000fU;
+}
+static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_f(void)
+{
+	return 0x7800U;
+}
+static inline u32 nvl_sl1_error_rate_ctrl_r(void)
+{
+	return 0x00003284U;
+}
+static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_f(u32 v)
+{
+	return (v & 0x7U) << 0U;
+}
+static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_m(void)
+{
+	return 0x7U << 0U;
+}
+static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_v(u32 r)
+{
+	return (r >> 0U) & 0x7U;
+}
+static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_f(u32 v)
+{
+	return (v & 0x7U) << 16U;
+}
+static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_m(void)
+{
+	return 0x7U << 16U;
+}
+static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_v(u32 r)
+{
+	return (r >> 16U) & 0x7U;
+}
+static inline u32 nvl_sl1_rxslsm_timeout_2_r(void)
+{
+	return 0x00003034U;
+}
+static inline u32 nvl_txiobist_configreg_r(void)
+{
+	return 0x00002e14U;
+}
+static inline u32 nvl_txiobist_configreg_io_bist_mode_in_f(u32 v)
+{
+	return (v & 0x1U) << 17U;
+}
+static inline u32 nvl_txiobist_configreg_io_bist_mode_in_m(void)
+{
+	return 0x1U << 17U;
+}
+static inline u32 nvl_txiobist_configreg_io_bist_mode_in_v(u32 r)
+{
+	return (r >> 17U) & 0x1U;
+}
+static inline u32 nvl_txiobist_config_r(void)
+{
+	return 0x00002e10U;
+}
+static inline u32 nvl_txiobist_config_dpg_prbsseedld_f(u32 v)
+{
+	return (v & 0x1U) << 2U;
+}
+static inline u32 nvl_txiobist_config_dpg_prbsseedld_m(void)
+{
+	return 0x1U << 2U;
+}
+static inline u32 nvl_txiobist_config_dpg_prbsseedld_v(u32 r)
+{
+	return (r >> 2U) & 0x1U;
+}
+static inline u32 nvl_intr_r(void)
+{
+	return 0x00000050U;
+}
+static inline u32 nvl_intr_tx_replay_f(u32 v)
+{
+	return (v & 0x1U) << 0U;
+}
+static inline u32 nvl_intr_tx_replay_m(void)
+{
+	return 0x1U << 0U;
+}
+static inline u32 nvl_intr_tx_replay_v(u32 r)
+{
+	return (r >> 0U) & 0x1U;
+}
+static inline u32 nvl_intr_tx_recovery_short_f(u32 v)
+{
+	return (v & 0x1U) << 1U;
+}
+static inline u32 nvl_intr_tx_recovery_short_m(void)
+{
+	return 0x1U << 1U;
+}
+static inline u32 nvl_intr_tx_recovery_short_v(u32 r)
+{
+	return (r >> 1U) & 0x1U;
+}
+static inline u32 nvl_intr_tx_recovery_long_f(u32 v)
+{
+	return (v & 0x1U) << 2U;
+}
+static inline u32 nvl_intr_tx_recovery_long_m(void)
+{
+	return 0x1U << 2U;
+}
+static inline u32 nvl_intr_tx_recovery_long_v(u32 r)
+{
+	return (r >> 2U) & 0x1U;
+}
+static inline u32 nvl_intr_tx_fault_ram_f(u32 v)
+{
+	return (v & 0x1U) << 4U;
+}
+static inline u32 nvl_intr_tx_fault_ram_m(void)
+{
+	return 0x1U << 4U;
+}
+static inline u32 nvl_intr_tx_fault_ram_v(u32 r)
+{
+	return (r >> 4U) & 0x1U;
+}
+static inline u32 nvl_intr_tx_fault_interface_f(u32 v)
+{
+	return (v & 0x1U) << 5U;
+}
+static inline u32 nvl_intr_tx_fault_interface_m(void)
+{
+	return 0x1U << 5U;
+}
+static inline u32 nvl_intr_tx_fault_interface_v(u32 r)
+{
+	return (r >> 5U) & 0x1U;
+}
+static inline u32 nvl_intr_tx_fault_sublink_change_f(u32 v)
+{
+	return (v & 0x1U) << 8U;
+}
+static inline u32 nvl_intr_tx_fault_sublink_change_m(void)
+{
+	return 0x1U << 8U;
+}
+static inline u32 nvl_intr_tx_fault_sublink_change_v(u32 r)
+{
+	return (r >> 8U) & 0x1U;
+}
+static inline u32 nvl_intr_rx_fault_sublink_change_f(u32 v)
+{
+	return (v & 0x1U) << 16U;
+}
+static inline u32 nvl_intr_rx_fault_sublink_change_m(void)
+{
+	return 0x1U << 16U;
+}
+static inline u32 nvl_intr_rx_fault_sublink_change_v(u32 r)
+{
+	return (r >> 16U) & 0x1U;
+}
+static inline u32 nvl_intr_rx_fault_dl_protocol_f(u32 v)
+{
+	return (v & 0x1U) << 20U;
+}
+static inline u32 nvl_intr_rx_fault_dl_protocol_m(void)
+{
+	return 0x1U << 20U;
+}
+static inline u32 nvl_intr_rx_fault_dl_protocol_v(u32 r)
+{
+	return (r >> 20U) & 0x1U;
+}
+static inline u32 nvl_intr_rx_short_error_rate_f(u32 v)
+{
+	return (v & 0x1U) << 21U;
+}
+static inline u32 nvl_intr_rx_short_error_rate_m(void)
+{
+	return 0x1U << 21U;
+}
+static inline u32 nvl_intr_rx_short_error_rate_v(u32 r)
+{
+	return (r >> 21U) & 0x1U;
+}
+static inline u32 nvl_intr_rx_long_error_rate_f(u32 v)
+{
+	return (v & 0x1U) << 22U;
+}
+static inline u32 nvl_intr_rx_long_error_rate_m(void)
+{
+	return 0x1U << 22U;
+}
+static inline u32 nvl_intr_rx_long_error_rate_v(u32 r)
+{
+	return (r >> 22U) & 0x1U;
+}
+static inline u32 nvl_intr_rx_ila_trigger_f(u32 v)
+{
+	return (v & 0x1U) << 23U;
+}
+static inline u32 nvl_intr_rx_ila_trigger_m(void)
+{
+	return 0x1U << 23U;
+}
+static inline u32 nvl_intr_rx_ila_trigger_v(u32 r)
+{
+	return (r >> 23U) & 0x1U;
+}
+static inline u32 nvl_intr_rx_crc_counter_f(u32 v)
+{
+	return (v & 0x1U) << 24U;
+}
+static inline u32 nvl_intr_rx_crc_counter_m(void)
+{
+	return 0x1U << 24U;
+}
+static inline u32 nvl_intr_rx_crc_counter_v(u32 r)
+{
+	return (r >> 24U) & 0x1U;
+}
+static inline u32 nvl_intr_ltssm_fault_f(u32 v)
+{
+	return (v & 0x1U) << 28U;
+}
+static inline u32 nvl_intr_ltssm_fault_m(void)
+{
+	return 0x1U << 28U;
+}
+static inline u32 nvl_intr_ltssm_fault_v(u32 r)
+{
+	return (r >> 28U) & 0x1U;
+}
+static inline u32 nvl_intr_ltssm_protocol_f(u32 v)
+{
+	return (v & 0x1U) << 29U;
+}
+static inline u32 nvl_intr_ltssm_protocol_m(void)
+{
+	return 0x1U << 29U;
+}
+static inline u32 nvl_intr_ltssm_protocol_v(u32 r)
+{
+	return (r >> 29U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_request_f(u32 v)
+{
+	return (v & 0x1U) << 30U;
+}
+static inline u32 nvl_intr_minion_request_m(void)
+{
+	return 0x1U << 30U;
+}
+static inline u32 nvl_intr_minion_request_v(u32 r)
+{
+	return (r >> 30U) & 0x1U;
+}
+static inline u32 nvl_intr_sw2_r(void)
+{
+	return 0x00000054U;
+}
+static inline u32 nvl_intr_minion_r(void)
+{
+	return 0x00000060U;
+}
+static inline u32 nvl_intr_minion_tx_replay_f(u32 v)
+{
+	return (v & 0x1U) << 0U;
+}
+static inline u32 nvl_intr_minion_tx_replay_m(void)
+{
+	return 0x1U << 0U;
+}
+static inline u32 nvl_intr_minion_tx_replay_v(u32 r)
+{
+	return (r >> 0U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_tx_recovery_short_f(u32 v)
+{
+	return (v & 0x1U) << 1U;
+}
+static inline u32 nvl_intr_minion_tx_recovery_short_m(void)
+{
+	return 0x1U << 1U;
+}
+static inline u32 nvl_intr_minion_tx_recovery_short_v(u32 r)
+{
+	return (r >> 1U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_tx_recovery_long_f(u32 v)
+{
+	return (v & 0x1U) << 2U;
+}
+static inline u32 nvl_intr_minion_tx_recovery_long_m(void)
+{
+	return 0x1U << 2U;
+}
+static inline u32 nvl_intr_minion_tx_recovery_long_v(u32 r)
+{
+	return (r >> 2U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_tx_fault_ram_f(u32 v)
+{
+	return (v & 0x1U) << 4U;
+}
+static inline u32 nvl_intr_minion_tx_fault_ram_m(void)
+{
+	return 0x1U << 4U;
+}
+static inline u32 nvl_intr_minion_tx_fault_ram_v(u32 r)
+{
+	return (r >> 4U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_tx_fault_interface_f(u32 v)
+{
+	return (v & 0x1U) << 5U;
+}
+static inline u32 nvl_intr_minion_tx_fault_interface_m(void)
+{
+	return 0x1U << 5U;
+}
+static inline u32 nvl_intr_minion_tx_fault_interface_v(u32 r)
+{
+	return (r >> 5U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_tx_fault_sublink_change_f(u32 v)
+{
+	return (v & 0x1U) << 8U;
+}
+static inline u32 nvl_intr_minion_tx_fault_sublink_change_m(void)
+{
+	return 0x1U << 8U;
+}
+static inline u32 nvl_intr_minion_tx_fault_sublink_change_v(u32 r)
+{
+	return (r >> 8U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_rx_fault_sublink_change_f(u32 v)
+{
+	return (v & 0x1U) << 16U;
+}
+static inline u32 nvl_intr_minion_rx_fault_sublink_change_m(void)
+{
+	return 0x1U << 16U;
+}
+static inline u32 nvl_intr_minion_rx_fault_sublink_change_v(u32 r)
+{
+	return (r >> 16U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_rx_fault_dl_protocol_f(u32 v)
+{
+	return (v & 0x1U) << 20U;
+}
+static inline u32 nvl_intr_minion_rx_fault_dl_protocol_m(void)
+{
+	return 0x1U << 20U;
+}
+static inline u32 nvl_intr_minion_rx_fault_dl_protocol_v(u32 r)
+{
+	return (r >> 20U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_rx_short_error_rate_f(u32 v)
+{
+	return (v & 0x1U) << 21U;
+}
+static inline u32 nvl_intr_minion_rx_short_error_rate_m(void)
+{
+	return 0x1U << 21U;
+}
+static inline u32 nvl_intr_minion_rx_short_error_rate_v(u32 r)
+{
+	return (r >> 21U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_rx_long_error_rate_f(u32 v)
+{
+	return (v & 0x1U) << 22U;
+}
+static inline u32 nvl_intr_minion_rx_long_error_rate_m(void)
+{
+	return 0x1U << 22U;
+}
+static inline u32 nvl_intr_minion_rx_long_error_rate_v(u32 r)
+{
+	return (r >> 22U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_rx_ila_trigger_f(u32 v)
+{
+	return (v & 0x1U) << 23U;
+}
+static inline u32 nvl_intr_minion_rx_ila_trigger_m(void)
+{
+	return 0x1U << 23U;
+}
+static inline u32 nvl_intr_minion_rx_ila_trigger_v(u32 r)
+{
+	return (r >> 23U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_rx_crc_counter_f(u32 v)
+{
+	return (v & 0x1U) << 24U;
+}
+static inline u32 nvl_intr_minion_rx_crc_counter_m(void)
+{
+	return 0x1U << 24U;
+}
+static inline u32 nvl_intr_minion_rx_crc_counter_v(u32 r)
+{
+	return (r >> 24U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_ltssm_fault_f(u32 v)
+{
+	return (v & 0x1U) << 28U;
+}
+static inline u32 nvl_intr_minion_ltssm_fault_m(void)
+{
+	return 0x1U << 28U;
+}
+static inline u32 nvl_intr_minion_ltssm_fault_v(u32 r)
+{
+	return (r >> 28U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_ltssm_protocol_f(u32 v)
+{
+	return (v & 0x1U) << 29U;
+}
+static inline u32 nvl_intr_minion_ltssm_protocol_m(void)
+{
+	return 0x1U << 29U;
+}
+static inline u32 nvl_intr_minion_ltssm_protocol_v(u32 r)
+{
+	return (r >> 29U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_minion_request_f(u32 v)
+{
+	return (v & 0x1U) << 30U;
+}
+static inline u32 nvl_intr_minion_minion_request_m(void)
+{
+	return 0x1U << 30U;
+}
+static inline u32 nvl_intr_minion_minion_request_v(u32 r)
+{
+	return (r >> 30U) & 0x1U;
+}
+static inline u32 nvl_intr_nonstall_en_r(void)
+{
+	return 0x0000005cU;
+}
+static inline u32 nvl_intr_stall_en_r(void)
+{
+	return 0x00000058U;
+}
+static inline u32 nvl_intr_stall_en_tx_replay_f(u32 v)
+{
+	return (v & 0x1U) << 0U;
+}
+static inline u32 nvl_intr_stall_en_tx_replay_m(void)
+{
+	return 0x1U << 0U;
+}
+static inline u32 nvl_intr_stall_en_tx_replay_v(u32 r)
+{
+	return (r >> 0U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_tx_recovery_short_f(u32 v)
+{
+	return (v & 0x1U) << 1U;
+}
+static inline u32 nvl_intr_stall_en_tx_recovery_short_m(void)
+{
+	return 0x1U << 1U;
+}
+static inline u32 nvl_intr_stall_en_tx_recovery_short_v(u32 r)
+{
+	return (r >> 1U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_tx_recovery_short_enable_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_tx_recovery_short_enable_f(void)
+{
+	return 0x2U;
+}
+static inline u32 nvl_intr_stall_en_tx_recovery_long_f(u32 v)
+{
+	return (v & 0x1U) << 2U;
+}
+static inline u32 nvl_intr_stall_en_tx_recovery_long_m(void)
+{
+	return 0x1U << 2U;
+}
+static inline u32 nvl_intr_stall_en_tx_recovery_long_v(u32 r)
+{
+	return (r >> 2U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_tx_recovery_long_enable_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_tx_recovery_long_enable_f(void)
+{
+	return 0x4U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_ram_f(u32 v)
+{
+	return (v & 0x1U) << 4U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_ram_m(void)
+{
+	return 0x1U << 4U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_ram_v(u32 r)
+{
+	return (r >> 4U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_ram_enable_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_ram_enable_f(void)
+{
+	return 0x10U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_interface_f(u32 v)
+{
+	return (v & 0x1U) << 5U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_interface_m(void)
+{
+	return 0x1U << 5U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_interface_v(u32 r)
+{
+	return (r >> 5U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_interface_enable_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_interface_enable_f(void)
+{
+	return 0x20U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_f(u32 v)
+{
+	return (v & 0x1U) << 8U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_m(void)
+{
+	return 0x1U << 8U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_v(u32 r)
+{
+	return (r >> 8U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_enable_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_enable_f(void)
+{
+	return 0x100U;
+}
+static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_f(u32 v)
+{
+	return (v & 0x1U) << 16U;
+}
+static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_m(void)
+{
+	return 0x1U << 16U;
+}
+static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_v(u32 r)
+{
+	return (r >> 16U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_enable_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_enable_f(void)
+{
+	return 0x10000U;
+}
+static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_f(u32 v)
+{
+	return (v & 0x1U) << 20U;
+}
+static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_m(void)
+{
+	return 0x1U << 20U;
+}
+static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_v(u32 r)
+{
+	return (r >> 20U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_enable_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_enable_f(void)
+{
+	return 0x100000U;
+}
+static inline u32 nvl_intr_stall_en_rx_short_error_rate_f(u32 v)
+{
+	return (v & 0x1U) << 21U;
+}
+static inline u32 nvl_intr_stall_en_rx_short_error_rate_m(void)
+{
+	return 0x1U << 21U;
+}
+static inline u32 nvl_intr_stall_en_rx_short_error_rate_v(u32 r)
+{
+	return (r >> 21U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_rx_short_error_rate_enable_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_rx_short_error_rate_enable_f(void)
+{
+	return 0x200000U;
+}
+static inline u32 nvl_intr_stall_en_rx_long_error_rate_f(u32 v)
+{
+	return (v & 0x1U) << 22U;
+}
+static inline u32 nvl_intr_stall_en_rx_long_error_rate_m(void)
+{
+	return 0x1U << 22U;
+}
+static inline u32 nvl_intr_stall_en_rx_long_error_rate_v(u32 r)
+{
+	return (r >> 22U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_rx_long_error_rate_enable_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_rx_long_error_rate_enable_f(void)
+{
+	return 0x400000U;
+}
+static inline u32 nvl_intr_stall_en_rx_ila_trigger_f(u32 v)
+{
+	return (v & 0x1U) << 23U;
+}
+static inline u32 nvl_intr_stall_en_rx_ila_trigger_m(void)
+{
+	return 0x1U << 23U;
+}
+static inline u32 nvl_intr_stall_en_rx_ila_trigger_v(u32 r)
+{
+	return (r >> 23U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_rx_ila_trigger_enable_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_rx_ila_trigger_enable_f(void)
+{
+	return 0x800000U;
+}
+static inline u32 nvl_intr_stall_en_rx_crc_counter_f(u32 v)
+{
+	return (v & 0x1U) << 24U;
+}
+static inline u32 nvl_intr_stall_en_rx_crc_counter_m(void)
+{
+	return 0x1U << 24U;
+}
+static inline u32 nvl_intr_stall_en_rx_crc_counter_v(u32 r)
+{
+	return (r >> 24U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_rx_crc_counter_enable_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_rx_crc_counter_enable_f(void)
+{
+	return 0x1000000U;
+}
+static inline u32 nvl_intr_stall_en_ltssm_fault_f(u32 v)
+{
+	return (v & 0x1U) << 28U;
+}
+static inline u32 nvl_intr_stall_en_ltssm_fault_m(void)
+{
+	return 0x1U << 28U;
+}
+static inline u32 nvl_intr_stall_en_ltssm_fault_v(u32 r)
+{
+	return (r >> 28U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_ltssm_fault_enable_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_ltssm_fault_enable_f(void)
+{
+	return 0x10000000U;
+}
+static inline u32 nvl_intr_stall_en_ltssm_protocol_f(u32 v)
+{
+	return (v & 0x1U) << 29U;
+}
+static inline u32 nvl_intr_stall_en_ltssm_protocol_m(void)
+{
+	return 0x1U << 29U;
+}
+static inline u32 nvl_intr_stall_en_ltssm_protocol_v(u32 r)
+{
+	return (r >> 29U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_ltssm_protocol_enable_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_ltssm_protocol_enable_f(void)
+{
+	return 0x20000000U;
+}
+static inline u32 nvl_intr_stall_en_minion_request_f(u32 v)
+{
+	return (v & 0x1U) << 30U;
+}
+static inline u32 nvl_intr_stall_en_minion_request_m(void)
+{
+	return 0x1U << 30U;
+}
+static inline u32 nvl_intr_stall_en_minion_request_v(u32 r)
+{
+	return (r >> 30U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_minion_request_enable_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_minion_request_enable_f(void)
+{
+	return 0x40000000U;
+}
+static inline u32 nvl_br0_cfg_cal_r(void)
+{
+	return 0x0000281cU;
+}
+static inline u32 nvl_br0_cfg_cal_rxcal_f(u32 v)
+{
+	return (v & 0x1U) << 0U;
+}
+static inline u32 nvl_br0_cfg_cal_rxcal_m(void)
+{
+	return 0x1U << 0U;
+}
+static inline u32 nvl_br0_cfg_cal_rxcal_v(u32 r)
+{
+	return (r >> 0U) & 0x1U;
+}
+static inline u32 nvl_br0_cfg_cal_rxcal_on_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvl_br0_cfg_cal_rxcal_on_f(void)
+{
+	return 0x1U;
+}
+static inline u32 nvl_br0_cfg_status_cal_r(void)
+{
+	return 0x00002838U;
+}
+static inline u32 nvl_br0_cfg_status_cal_rxcal_done_f(u32 v)
+{
+	return (v & 0x1U) << 2U;
+}
+static inline u32 nvl_br0_cfg_status_cal_rxcal_done_m(void)
+{
+	return 0x1U << 2U;
+}
+static inline u32 nvl_br0_cfg_status_cal_rxcal_done_v(u32 r)
+{
+	return (r >> 2U) & 0x1U;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h
new file mode 100644
index 00000000..9d33a9fd
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h
@@ -0,0 +1,311 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_nvlinkip_discovery_gv100_h_
+#define _hw_nvlinkip_discovery_gv100_h_
+
+static inline u32 nvlinkip_discovery_common_r(void)
+{
+	return 0x00000000U;
+}
+static inline u32 nvlinkip_discovery_common_entry_f(u32 v)
+{
+	return (v & 0x3U) << 0U;
+}
+static inline u32 nvlinkip_discovery_common_entry_v(u32 r)
+{
+	return (r >> 0U) & 0x3U;
+}
+static inline u32 nvlinkip_discovery_common_entry_invalid_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 nvlinkip_discovery_common_entry_enum_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvlinkip_discovery_common_entry_data1_v(void)
+{
+	return 0x00000002U;
+}
+static inline u32 nvlinkip_discovery_common_entry_data2_v(void)
+{
+	return 0x00000003U;
+}
+static inline u32 nvlinkip_discovery_common_contents_f(u32 v)
+{
+	return (v & 0x1fffffffU) << 2U;
+}
+static inline u32 nvlinkip_discovery_common_contents_v(u32 r)
+{
+	return (r >> 2U) & 0x1fffffffU;
+}
+static inline u32 nvlinkip_discovery_common_chain_f(u32 v)
+{
+	return (v & 0x1U) << 31U;
+}
+static inline u32 nvlinkip_discovery_common_chain_v(u32 r)
+{
+	return (r >> 31U) & 0x1U;
+}
+static inline u32 nvlinkip_discovery_common_chain_enable_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvlinkip_discovery_common_device_f(u32 v)
+{
+	return (v & 0x3fU) << 2U;
+}
+static inline u32 nvlinkip_discovery_common_device_v(u32 r)
+{
+	return (r >> 2U) & 0x3fU;
+}
+static inline u32 nvlinkip_discovery_common_device_invalid_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 nvlinkip_discovery_common_device_ioctrl_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvlinkip_discovery_common_device_nvltl_v(void)
+{
+	return 0x00000002U;
+}
+static inline u32 nvlinkip_discovery_common_device_nvlink_v(void)
+{
+	return 0x00000003U;
+}
+static inline u32 nvlinkip_discovery_common_device_minion_v(void)
+{
+	return 0x00000004U;
+}
+static inline u32 nvlinkip_discovery_common_device_nvlipt_v(void)
+{
+	return 0x00000005U;
+}
+static inline u32 nvlinkip_discovery_common_device_nvltlc_v(void)
+{
+	return 0x00000006U;
+}
+static inline u32 nvlinkip_discovery_common_device_dlpl_v(void)
+{
+	return 0x0000000bU;
+}
+static inline u32 nvlinkip_discovery_common_device_ioctrlmif_v(void)
+{
+	return 0x00000007U;
+}
+static inline u32 nvlinkip_discovery_common_device_dlpl_multicast_v(void)
+{
+	return 0x00000008U;
+}
+static inline u32 nvlinkip_discovery_common_device_nvltlc_multicast_v(void)
+{
+	return 0x00000009U;
+}
+static inline u32 nvlinkip_discovery_common_device_ioctrlmif_multicast_v(void)
+{
+	return 0x0000000aU;
+}
+static inline u32 nvlinkip_discovery_common_device_sioctrl_v(void)
+{
+	return 0x0000000cU;
+}
+static inline u32 nvlinkip_discovery_common_device_tioctrl_v(void)
+{
+	return 0x0000000dU;
+}
+static inline u32 nvlinkip_discovery_common_id_f(u32 v)
+{
+	return (v & 0xffU) << 8U;
+}
+static inline u32 nvlinkip_discovery_common_id_v(u32 r)
+{
+	return (r >> 8U) & 0xffU;
+}
+static inline u32 nvlinkip_discovery_common_version_f(u32 v)
+{
+	return (v & 0x7ffU) << 20U;
+}
+static inline u32 nvlinkip_discovery_common_version_v(u32 r)
+{
+	return (r >> 20U) & 0x7ffU;
+}
+static inline u32 nvlinkip_discovery_common_pri_base_f(u32 v)
+{
+	return (v & 0xfffU) << 12U;
+}
+static inline u32 nvlinkip_discovery_common_pri_base_v(u32 r)
+{
+	return (r >> 12U) & 0xfffU;
+}
+static inline u32 nvlinkip_discovery_common_intr_f(u32 v)
+{
+	return (v & 0x1fU) << 7U;
+}
+static inline u32 nvlinkip_discovery_common_intr_v(u32 r)
+{
+	return (r >> 7U) & 0x1fU;
+}
+static inline u32 nvlinkip_discovery_common_reset_f(u32 v)
+{
+	return (v & 0x1fU) << 2U;
+}
+static inline u32 nvlinkip_discovery_common_reset_v(u32 r)
+{
+	return (r >> 2U) & 0x1fU;
+}
+static inline u32 nvlinkip_discovery_common_ioctrl_length_f(u32 v)
+{
+	return (v & 0x3fU) << 24U;
+}
+static inline u32 nvlinkip_discovery_common_ioctrl_length_v(u32 r)
+{
+	return (r >> 24U) & 0x3fU;
+}
+static inline u32 nvlinkip_discovery_common_dlpl_num_tx_f(u32 v)
+{
+	return (v & 0x7U) << 24U;
+}
+static inline u32 nvlinkip_discovery_common_dlpl_num_tx_v(u32 r)
+{
+	return (r >> 24U) & 0x7U;
+}
+static inline u32 nvlinkip_discovery_common_dlpl_num_rx_f(u32 v)
+{
+	return (v & 0x7U) << 27U;
+}
+static inline u32 nvlinkip_discovery_common_dlpl_num_rx_v(u32 r)
+{
+	return (r >> 27U) & 0x7U;
+}
+static inline u32 nvlinkip_discovery_common_data1_ioctrl_length_f(u32 v)
+{
+	return (v & 0x7ffffU) << 12U;
+}
+static inline u32 nvlinkip_discovery_common_data1_ioctrl_length_v(u32 r)
+{
+	return (r >> 12U) & 0x7ffffU;
+}
+static inline u32 nvlinkip_discovery_common_data2_type_f(u32 v)
+{
+	return (v & 0x1fU) << 26U;
+}
+static inline u32 nvlinkip_discovery_common_data2_type_v(u32 r)
+{
+	return (r >> 26U) & 0x1fU;
+}
+static inline u32 nvlinkip_discovery_common_data2_type_invalid_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 nvlinkip_discovery_common_data2_type_pllcontrol_v(void)
+{
+	return 0x00000001U;
+}
+static inline u32 nvlinkip_discovery_common_data2_type_resetreg_v(void)
+{
+	return 0x00000002U;
+}
+static inline u32 nvlinkip_discovery_common_data2_type_intrreg_v(void)
+{
+	return 0x00000003U;
+}
+static inline u32 nvlinkip_discovery_common_data2_type_discovery_v(void)
+{
+	return 0x00000004U;
+}
+static inline u32 nvlinkip_discovery_common_data2_type_unicast_v(void)
+{
+	return 0x00000005U;
+}
+static inline u32 nvlinkip_discovery_common_data2_type_broadcast_v(void)
+{
+	return 0x00000006U;
+}
+static inline u32 nvlinkip_discovery_common_data2_addr_f(u32 v)
+{
+	return (v & 0xffffffU) << 2U;
+}
+static inline u32 nvlinkip_discovery_common_data2_addr_v(u32 r)
+{
+	return (r >> 2U) & 0xffffffU;
+}
+static inline u32 nvlinkip_discovery_common_dlpl_data2_type_f(u32 v)
+{
+	return (v & 0x1fU) << 26U;
+}
+static inline u32 nvlinkip_discovery_common_dlpl_data2_type_v(u32 r)
+{
+	return (r >> 26U) & 0x1fU;
+}
+static inline u32 nvlinkip_discovery_common_dlpl_data2_master_f(u32 v)
+{
+	return (v & 0x1U) << 15U;
+}
+static inline u32 nvlinkip_discovery_common_dlpl_data2_master_v(u32 r)
+{
+	return (r >> 15U) & 0x1U;
+}
+static inline u32 nvlinkip_discovery_common_dlpl_data2_masterid_f(u32 v)
+{
+	return (v & 0x7fU) << 8U;
+}
+static inline u32 nvlinkip_discovery_common_dlpl_data2_masterid_v(u32 r)
+{
+	return (r >> 8U) & 0x7fU;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlipt_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlipt_gv100.h
new file mode 100644
index 00000000..5f73fabd
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvlipt_gv100.h
@@ -0,0 +1,279 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_nvlipt_gv100_h_
+#define _hw_nvlipt_gv100_h_
+
+static inline u32 nvlipt_intr_control_link0_r(void)
+{
+	return 0x000004b4U;
+}
+static inline u32 nvlipt_intr_control_link0_stallenable_f(u32 v)
+{
+	return (v & 0x1U) << 0U;
+}
+static inline u32 nvlipt_intr_control_link0_stallenable_m(void)
+{
+	return 0x1U << 0U;
+}
+static inline u32 nvlipt_intr_control_link0_stallenable_v(u32 r)
+{
+	return (r >> 0U) & 0x1U;
+}
+static inline u32 nvlipt_intr_control_link0_nostallenable_f(u32 v)
+{
+	return (v & 0x1U) << 1U;
+}
+static inline u32 nvlipt_intr_control_link0_nostallenable_m(void)
+{
+	return 0x1U << 1U;
+}
+static inline u32 nvlipt_intr_control_link0_nostallenable_v(u32 r)
+{
+	return (r >> 1U) & 0x1U;
+}
+static inline u32 nvlipt_err_uc_status_link0_r(void)
+{
+	return 0x00000524U;
+}
+static inline u32 nvlipt_err_uc_status_link0_dlprotocol_f(u32 v)
+{
+	return (v & 0x1U) << 4U;
+}
+static inline u32 nvlipt_err_uc_status_link0_dlprotocol_v(u32 r)
+{
+	return (r >> 4U) & 0x1U;
+}
+static inline u32 nvlipt_err_uc_status_link0_datapoisoned_f(u32 v)
+{
+	return (v & 0x1U) << 12U;
+}
+static inline u32 nvlipt_err_uc_status_link0_datapoisoned_v(u32 r)
+{
+	return (r >> 12U) & 0x1U;
+}
+static inline u32 nvlipt_err_uc_status_link0_flowcontrol_f(u32 v)
+{
+	return (v & 0x1U) << 13U;
+}
+static inline u32 nvlipt_err_uc_status_link0_flowcontrol_v(u32 r)
+{
+	return (r >> 13U) & 0x1U;
+}
+static inline u32 nvlipt_err_uc_status_link0_responsetimeout_f(u32 v)
+{
+	return (v & 0x1U) << 14U;
+}
+static inline u32 nvlipt_err_uc_status_link0_responsetimeout_v(u32 r)
+{
+	return (r >> 14U) & 0x1U;
+}
+static inline u32 nvlipt_err_uc_status_link0_targeterror_f(u32 v)
+{
+	return (v & 0x1U) << 15U;
+}
+static inline u32 nvlipt_err_uc_status_link0_targeterror_v(u32 r)
+{
+	return (r >> 15U) & 0x1U;
+}
+static inline u32 nvlipt_err_uc_status_link0_unexpectedresponse_f(u32 v)
+{
+	return (v & 0x1U) << 16U;
+}
+static inline u32 nvlipt_err_uc_status_link0_unexpectedresponse_v(u32 r)
+{
+	return (r >> 16U) & 0x1U;
+}
+static inline u32 nvlipt_err_uc_status_link0_receiveroverflow_f(u32 v)
+{
+	return (v & 0x1U) << 17U;
+}
+static inline u32 nvlipt_err_uc_status_link0_receiveroverflow_v(u32 r)
+{
+	return (r >> 17U) & 0x1U;
+}
+static inline u32 nvlipt_err_uc_status_link0_malformedpacket_f(u32 v)
+{
+	return (v & 0x1U) << 18U;
+}
+static inline u32 nvlipt_err_uc_status_link0_malformedpacket_v(u32 r)
+{
+	return (r >> 18U) & 0x1U;
+}
+static inline u32 nvlipt_err_uc_status_link0_stompedpacketreceived_f(u32 v)
+{
+	return (v & 0x1U) << 19U;
+}
+static inline u32 nvlipt_err_uc_status_link0_stompedpacketreceived_v(u32 r)
+{
+	return (r >> 19U) & 0x1U;
+}
+static inline u32 nvlipt_err_uc_status_link0_unsupportedrequest_f(u32 v)
+{
+	return (v & 0x1U) << 20U;
+}
+static inline u32 nvlipt_err_uc_status_link0_unsupportedrequest_v(u32 r)
+{
+	return (r >> 20U) & 0x1U;
+}
+static inline u32 nvlipt_err_uc_status_link0_ucinternal_f(u32 v)
+{
+	return (v & 0x1U) << 22U;
+}
+static inline u32 nvlipt_err_uc_status_link0_ucinternal_v(u32 r)
+{
+	return (r >> 22U) & 0x1U;
+}
+static inline u32 nvlipt_err_uc_mask_link0_r(void)
+{
+	return 0x00000528U;
+}
+static inline u32 nvlipt_err_uc_severity_link0_r(void)
+{
+	return 0x0000052cU;
+}
+static inline u32 nvlipt_err_uc_first_link0_r(void)
+{
+	return 0x00000530U;
+}
+static inline u32 nvlipt_err_uc_advisory_link0_r(void)
+{
+	return 0x00000534U;
+}
+static inline u32 nvlipt_err_c_status_link0_r(void)
+{
+	return 0x00000538U;
+}
+static inline u32 nvlipt_err_c_mask_link0_r(void)
+{
+	return 0x0000053cU;
+}
+static inline u32 nvlipt_err_c_first_link0_r(void)
+{
+	return 0x00000540U;
+}
+static inline u32 nvlipt_err_control_link0_r(void)
+{
+	return 0x00000544U;
+}
+static inline u32 nvlipt_err_control_link0_fatalenable_f(u32 v)
+{
+	return (v & 0x1U) << 1U;
+}
+static inline u32 nvlipt_err_control_link0_fatalenable_m(void)
+{
+	return 0x1U << 1U;
+}
+static inline u32 nvlipt_err_control_link0_fatalenable_v(u32 r)
+{
+	return (r >> 1U) & 0x1U;
+}
+static inline u32 nvlipt_err_control_link0_nonfatalenable_f(u32 v)
+{
+	return (v & 0x1U) << 2U;
+}
+static inline u32 nvlipt_err_control_link0_nonfatalenable_m(void)
+{
+	return 0x1U << 2U;
+}
+static inline u32 nvlipt_err_control_link0_nonfatalenable_v(u32 r)
+{
+	return (r >> 2U) & 0x1U;
+}
+static inline u32 nvlipt_intr_control_common_r(void)
+{
+	return 0x000004b0U;
+}
+static inline u32 nvlipt_intr_control_common_stallenable_f(u32 v)
+{
+	return (v & 0x1U) << 0U;
+}
+static inline u32 nvlipt_intr_control_common_stallenable_m(void)
+{
+	return 0x1U << 0U;
+}
+static inline u32 nvlipt_intr_control_common_stallenable_v(u32 r)
+{
+	return (r >> 0U) & 0x1U;
+}
+static inline u32 nvlipt_intr_control_common_nonstallenable_f(u32 v)
+{
+	return (v & 0x1U) << 1U;
+}
+static inline u32 nvlipt_intr_control_common_nonstallenable_m(void)
+{
+	return 0x1U << 1U;
+}
+static inline u32 nvlipt_intr_control_common_nonstallenable_v(u32 r)
+{
+	return (r >> 1U) & 0x1U;
+}
+static inline u32 nvlipt_scratch_cold_r(void)
+{
+	return 0x000007d4U;
+}
+static inline u32 nvlipt_scratch_cold_data_f(u32 v)
+{
+	return (v & 0xffffffffU) << 0U;
+}
+static inline u32 nvlipt_scratch_cold_data_v(u32 r)
+{
+	return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 nvlipt_scratch_cold_data_init_v(void)
+{
+	return 0xdeadbaadU;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvtlc_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvtlc_gv100.h
new file mode 100644
index 00000000..cc31b12b
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_nvtlc_gv100.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_nvtlc_gv100_h_
+#define _hw_nvtlc_gv100_h_
+
+static inline u32 nvtlc_tx_err_report_en_0_r(void)
+{
+	return 0x00000708U;
+}
+static inline u32 nvtlc_rx_err_report_en_0_r(void)
+{
+	return 0x00000f08U;
+}
+static inline u32 nvtlc_rx_err_report_en_1_r(void)
+{
+	return 0x00000f20U;
+}
+static inline u32 nvtlc_tx_err_status_0_r(void)
+{
+	return 0x00000700U;
+}
+static inline u32 nvtlc_rx_err_status_0_r(void)
+{
+	return 0x00000f00U;
+}
+static inline u32 nvtlc_rx_err_status_1_r(void)
+{
+	return 0x00000f18U;
+}
+static inline u32 nvtlc_tx_err_first_0_r(void)
+{
+	return 0x00000714U;
+}
+static inline u32 nvtlc_rx_err_first_0_r(void)
+{
+	return 0x00000f14U;
+}
+static inline u32 nvtlc_rx_err_first_1_r(void)
+{
+	return 0x00000f2cU;
+}
+#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h
index 6b3e8aa6..11333f43 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ram_gv100.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -128,6 +128,26 @@ static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void)
 {
 	return 0x20U;
 }
+static inline u32 ram_in_use_ver2_pt_format_f(u32 v)
+{
+	return (v & 0x1U) << 10U;
+}
+static inline u32 ram_in_use_ver2_pt_format_m(void)
+{
+	return 0x1U << 10U;
+}
+static inline u32 ram_in_use_ver2_pt_format_w(void)
+{
+	return 128U;
+}
+static inline u32 ram_in_use_ver2_pt_format_true_f(void)
+{
+	return 0x400U;
+}
+static inline u32 ram_in_use_ver2_pt_format_false_f(void)
+{
+	return 0x0U;
+}
 static inline u32 ram_in_big_page_size_f(u32 v)
 {
 	return (v & 0x1U) << 11U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h
index da297b72..ff9c046c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_top_gv100.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -168,6 +168,14 @@ static inline u32 top_device_info_type_enum_lce_f(void)
 {
 	return 0x4cU;
 }
+static inline u32 top_device_info_type_enum_ioctrl_v(void)
+{
+	return 0x00000012U;
+}
+static inline u32 top_device_info_type_enum_ioctrl_f(void)
+{
+	return 0x48U;
+}
 static inline u32 top_device_info_engine_v(u32 r)
 {
 	return (r >> 5U) & 0x1U;
@@ -200,6 +208,10 @@ static inline u32 top_device_info_entry_data_v(void)
 {
 	return 0x00000001U;
 }
+static inline u32 top_device_info_entry_engine_type_v(void)
+{
+	return 0x00000003U;
+}
 static inline u32 top_device_info_data_type_v(u32 r)
 {
 	return (r >> 30U) & 0x1U;
@@ -232,4 +244,92 @@ static inline u32 top_device_info_data_fault_id_valid_v(void)
 {
 	return 0x00000001U;
 }
+static inline u32 top_nvhsclk_ctrl_r(void)
+{
+	return 0x00022424U;
+}
+static inline u32 top_nvhsclk_ctrl_e_clk_nvl_f(u32 v)
+{
+	return (v & 0x7U) << 0U;
+}
+static inline u32 top_nvhsclk_ctrl_e_clk_nvl_m(void)
+{
+	return 0x7U << 0U;
+}
+static inline u32 top_nvhsclk_ctrl_e_clk_nvl_v(u32 r)
+{
+	return (r >> 0U) & 0x7U;
+}
+static inline u32 top_nvhsclk_ctrl_e_clk_pcie_f(u32 v)
+{
+	return (v & 0x1U) << 3U;
+}
+static inline u32 top_nvhsclk_ctrl_e_clk_pcie_m(void)
+{
+	return 0x1U << 3U;
+}
+static inline u32 top_nvhsclk_ctrl_e_clk_pcie_v(u32 r)
+{
+	return (r >> 3U) & 0x1U;
+}
+static inline u32 top_nvhsclk_ctrl_e_clk_core_f(u32 v)
+{
+	return (v & 0x1U) << 4U;
+}
+static inline u32 top_nvhsclk_ctrl_e_clk_core_m(void)
+{
+	return 0x1U << 4U;
+}
+static inline u32 top_nvhsclk_ctrl_e_clk_core_v(u32 r)
+{
+	return (r >> 4U) & 0x1U;
+}
+static inline u32 top_nvhsclk_ctrl_rfu_f(u32 v)
+{
+	return (v & 0xfU) << 5U;
+}
+static inline u32 top_nvhsclk_ctrl_rfu_m(void)
+{
+	return 0xfU << 5U;
+}
+static inline u32 top_nvhsclk_ctrl_rfu_v(u32 r)
+{
+	return (r >> 5U) & 0xfU;
+}
+static inline u32 top_nvhsclk_ctrl_swap_clk_nvl_f(u32 v)
+{
+	return (v & 0x7U) << 10U;
+}
+static inline u32 top_nvhsclk_ctrl_swap_clk_nvl_m(void)
+{
+	return 0x7U << 10U;
+}
+static inline u32 top_nvhsclk_ctrl_swap_clk_nvl_v(u32 r)
+{
+	return (r >> 10U) & 0x7U;
+}
+static inline u32 top_nvhsclk_ctrl_swap_clk_pcie_f(u32 v)
+{
+	return (v & 0x1U) << 9U;
+}
+static inline u32 top_nvhsclk_ctrl_swap_clk_pcie_m(void)
+{
+	return 0x1U << 9U;
+}
+static inline u32 top_nvhsclk_ctrl_swap_clk_pcie_v(u32 r)
+{
+	return (r >> 9U) & 0x1U;
+}
+static inline u32 top_nvhsclk_ctrl_swap_clk_core_f(u32 v)
+{
+	return (v & 0x1U) << 13U;
+}
+static inline u32 top_nvhsclk_ctrl_swap_clk_core_m(void)
+{
+	return 0x1U << 13U;
+}
+static inline u32 top_nvhsclk_ctrl_swap_clk_core_v(u32 r)
+{
+	return (r >> 13U) & 0x1U;
+}
 #endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h
new file mode 100644
index 00000000..9e7ceaff
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_trim_gv100.h
@@ -0,0 +1,199 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_trim_gv100_h_
+#define _hw_trim_gv100_h_
+
+static inline u32 trim_sys_nvlink_uphy_cfg_r(void)
+{
+	return 0x00132410U;
+}
+static inline u32 trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_f(u32 v)
+{
+	return (v & 0x3ffU) << 0U;
+}
+static inline u32 trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_m(void)
+{
+	return 0x3ffU << 0U;
+}
+static inline u32 trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_v(u32 r)
+{
+	return (r >> 0U) & 0x3ffU;
+}
+static inline u32 trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_f(u32 v)
+{
+	return (v & 0x1U) << 12U;
+}
+static inline u32 trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_m(void)
+{
+	return 0x1U << 12U;
+}
+static inline u32 trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_v(u32 r)
+{
+	return (r >> 12U) & 0x1U;
+}
+static inline u32 trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_f(u32 v)
+{
+	return (v & 0xffU) << 16U;
+}
+static inline u32 trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_m(void)
+{
+	return 0xffU << 16U;
+}
+static inline u32 trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_v(u32 r)
+{
+	return (r >> 16U) & 0xffU;
+}
+static inline u32 trim_sys_nvlink0_ctrl_r(void)
+{
+	return 0x00132420U;
+}
+static inline u32 trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_f(u32 v)
+{
+	return (v & 0x1U) << 0U;
+}
+static inline u32 trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_m(void)
+{
+	return 0x1U << 0U;
+}
+static inline u32 trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_v(u32 r)
+{
+	return (r >> 0U) & 0x1U;
+}
+static inline u32 trim_sys_nvlink0_status_r(void)
+{
+	return 0x00132424U;
+}
+static inline u32 trim_sys_nvlink0_status_pll_off_f(u32 v)
+{
+	return (v & 0x1U) << 5U;
+}
+static inline u32 trim_sys_nvlink0_status_pll_off_m(void)
+{
+	return 0x1U << 5U;
+}
+static inline u32 trim_sys_nvlink0_status_pll_off_v(u32 r)
+{
+	return (r >> 5U) & 0x1U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_r(void)
+{
+	return 0x001371c4U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_f(u32 v)
+{
+	return (v & 0x3U) << 16U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_m(void)
+{
+	return 0x3U << 16U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_v(u32 r)
+{
+	return (r >> 16U) & 0x3U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal4x_v(void)
+{
+	return 0x00000003U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal4x_f(void)
+{
+	return 0x30000U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal_in_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal_in_f(void)
+{
+	return 0x0U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_f(u32 v)
+{
+	return (v & 0x3U) << 0U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_m(void)
+{
+	return 0x3U << 0U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_v(u32 r)
+{
+	return (r >> 0U) & 0x3U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_slowclk_v(void)
+{
+	return 0x00000000U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_slowclk_f(void)
+{
+	return 0x0U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_miscclk_v(void)
+{
+	return 0x00000002U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_miscclk_f(void)
+{
+	return 0x2U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_onesrcclk_v(void)
+{
+	return 0x00000003U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_onesrcclk_f(void)
+{
+	return 0x3U;
+}
+#endif
-- 
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