From 2173add7ae7210606afdaa56995a61d012b9a2f1 Mon Sep 17 00:00:00 2001 From: David Nieto Date: Fri, 12 May 2017 11:07:00 -0700 Subject: gpu: nvgpu: per-chip GPCCS exception support Adding support for ISR handling of GPCCS exceptions and GCC ECC support JIRA: GPUT19X-83 Change-Id: Ica749dc678f152d536052cf47f2ea2b205a231d6 Signed-off-by: David Nieto Reviewed-on: http://git-master/r/1480997 Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 122 +++++- .../gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 460 +++++++++++++++++++++ 2 files changed, 580 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu') diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 014ba537..764374cc 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c @@ -634,6 +634,70 @@ static int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc, return 0; } +static int gr_gv11b_handle_gpccs_ecc_exception(struct gk20a *g, u32 gpc, + u32 exception) +{ + int ret = 0; + u32 ecc_status, ecc_addr, corrected_cnt, uncorrected_cnt; + int hww_esr; + u32 offset = proj_gpc_stride_v() * gpc; + + hww_esr = gk20a_readl(g, gr_gpc0_gpccs_hww_esr_r() + offset); + + if (!(hww_esr & (gr_gpc0_gpccs_hww_esr_ecc_uncorrected_m() | + gr_gpc0_gpccs_hww_esr_ecc_corrected_m()))) + return ret; + + ecc_status = gk20a_readl(g, + gr_gpc0_gpccs_falcon_ecc_status_r() + offset); + ecc_addr = gk20a_readl(g, + gr_gpc0_gpccs_falcon_ecc_address_r() + offset); + corrected_cnt = gk20a_readl(g, + gr_gpc0_gpccs_falcon_ecc_corrected_err_count_r() + offset); + uncorrected_cnt = gk20a_readl(g, + gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_r() + offset); + + /* clear the interrupt */ + gk20a_writel(g, gr_gpc0_gpccs_falcon_ecc_status_r() + offset, + gr_gpc0_gpccs_falcon_ecc_status_reset_task_f()); + + nvgpu_log(g, gpu_dbg_intr, + "gppcs gpc:%d ecc interrupt intr: 0x%x", gpc, hww_esr); + + if (ecc_status & gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_m()) + nvgpu_log(g, gpu_dbg_intr, "imem ecc error corrected"); + if (ecc_status & + gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_m()) + nvgpu_log(g, gpu_dbg_intr, "imem ecc error uncorrected"); + if (ecc_status & + gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_m()) + nvgpu_log(g, gpu_dbg_intr, "dmem ecc error corrected"); + if (ecc_status & + gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_m()) + nvgpu_log(g, gpu_dbg_intr, "dmem ecc error uncorrected"); + + nvgpu_log(g, gpu_dbg_intr, + "ecc error row address: 0x%x", + gr_gpc0_gpccs_falcon_ecc_address_row_address_v(ecc_addr)); + + nvgpu_log(g, gpu_dbg_intr, + "ecc error count corrected: %d, uncorrected %d", + gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_v(corrected_cnt), + gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_v(uncorrected_cnt)); + + return ret; +} + +static int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc, + u32 gpc_exception) +{ + if (gpc_exception & gr_gpc0_gpccs_gpc_exception_gpccs_m()) + return gr_gv11b_handle_gpccs_ecc_exception(g, gpc, + gpc_exception); + + return 0; +} + static void gr_gv11b_enable_gpc_exceptions(struct gk20a *g) { struct gr_gk20a *gr = &g->gr; @@ -646,7 +710,8 @@ static void gr_gv11b_enable_gpc_exceptions(struct gk20a *g) gr_gpcs_gpccs_gpc_exception_en_tpc_f((1 << gr->tpc_count) - 1); gk20a_writel(g, gr_gpcs_gpccs_gpc_exception_en_r(), - (tpc_mask | gr_gpcs_gpccs_gpc_exception_en_gcc_f(1))); + (tpc_mask | gr_gpcs_gpccs_gpc_exception_en_gcc_f(1) + gr_gpcs_gpccs_gpc_exception_en_gpccs_f(1)); } static int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, @@ -1622,6 +1687,55 @@ static int gr_gv11b_get_cilp_preempt_pending_chid(struct gk20a *g, int *__chid) return ret; } +static void gr_gv11b_handle_fecs_ecc_error(struct gk20a *g, u32 intr) +{ + u32 ecc_status, ecc_addr, corrected_cnt, uncorrected_cnt; + + if (intr & (gr_fecs_host_int_status_ecc_uncorrected_m() | + gr_fecs_host_int_status_ecc_corrected_m())) { + ecc_status = gk20a_readl(g, gr_fecs_falcon_ecc_status_r()); + ecc_addr = gk20a_readl(g, + gr_fecs_falcon_ecc_address_r()); + corrected_cnt = gk20a_readl(g, + gr_fecs_falcon_ecc_corrected_err_count_r()); + uncorrected_cnt = gk20a_readl(g, + gr_fecs_falcon_ecc_uncorrected_err_count_r()); + + /* clear the interrupt */ + gk20a_writel(g, gr_fecs_falcon_ecc_status_r(), + gr_fecs_falcon_ecc_status_reset_task_f()); + + nvgpu_log(g, gpu_dbg_intr, + "fecs ecc interrupt intr: 0x%x", intr); + + if (ecc_status & + gr_fecs_falcon_ecc_status_corrected_err_imem_m()) + nvgpu_log(g, gpu_dbg_intr, "imem ecc error corrected"); + if (ecc_status & + gr_fecs_falcon_ecc_status_uncorrected_err_imem_m()) + nvgpu_log(g, gpu_dbg_intr, + "imem ecc error uncorrected"); + if (ecc_status & + gr_fecs_falcon_ecc_status_corrected_err_dmem_m()) + nvgpu_log(g, gpu_dbg_intr, "dmem ecc error corrected"); + if (ecc_status & + gr_fecs_falcon_ecc_status_uncorrected_err_dmem_m()) + nvgpu_log(g, gpu_dbg_intr, + "dmem ecc error uncorrected"); + + nvgpu_log(g, gpu_dbg_intr, + "ecc error row address: 0x%x", + gr_fecs_falcon_ecc_address_row_address_v(ecc_addr)); + + nvgpu_log(g, gpu_dbg_intr, + "ecc error count corrected: %d, uncorrected %d", + gr_fecs_falcon_ecc_corrected_err_count_total_v( + corrected_cnt), + gr_fecs_falcon_ecc_uncorrected_err_count_total_v( + uncorrected_cnt)); + } +} + static int gr_gv11b_handle_fecs_error(struct gk20a *g, struct channel_gk20a *__ch, struct gr_gk20a_isr_data *isr_data) @@ -1680,6 +1794,9 @@ static int gr_gv11b_handle_fecs_error(struct gk20a *g, gk20a_channel_put(ch); } + /* Handle ECC errors */ + gr_gv11b_handle_fecs_ecc_error(g, gr_fecs_intr); + clean_up: /* handle any remaining interrupts */ return gk20a_gr_handle_fecs_error(g, __ch, isr_data); @@ -2214,5 +2331,6 @@ void gv11b_init_gr(struct gpu_ops *gops) gops->gr.write_pm_ptr = gr_gv11b_write_pm_ptr; gops->gr.init_elcg_mode = gr_gv11b_init_elcg_mode; gops->gr.load_tpc_mask = gr_gv11b_load_tpc_mask; - + gops->gr.handle_gpc_gpccs_exception = + gr_gv11b_handle_gpc_gpccs_exception; } diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 6f38cf5b..9917f86d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h @@ -1398,6 +1398,22 @@ static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) { return (v & 0xffff) << 0; } +static inline u32 gr_fecs_host_int_status_ecc_corrected_f(u32 v) +{ + return (v & 0x1) << 21; +} +static inline u32 gr_fecs_host_int_status_ecc_corrected_m(void) +{ + return 0x1 << 21; +} +static inline u32 gr_fecs_host_int_status_ecc_uncorrected_f(u32 v) +{ + return (v & 0x1) << 22; +} +static inline u32 gr_fecs_host_int_status_ecc_uncorrected_m(void) +{ + return 0x1 << 22; +} static inline u32 gr_fecs_host_int_clear_r(void) { return 0x00409c20; @@ -3378,6 +3394,10 @@ static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) { return (v & 0xff) << 16; } +static inline u32 gr_gpcs_gpccs_gpc_exception_en_gpccs_f(u32 v) +{ + return (v & 0x1) << 14; +} static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) { return 0x00502c90; @@ -3450,6 +3470,18 @@ static inline u32 gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_v(u32 r) { return (r >> 0) & 0xffff; } +static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_f(u32 v) +{ + return (v & 0x1) << 14; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_m(void) +{ + return 0x1 << 14; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_gpccs_pending_f(void) +{ + return 0x4000; +} static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) { return 0x00504508; @@ -3954,4 +3986,432 @@ static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) { return 0x1ff << 0; } +static inline u32 gr_gpc0_gpccs_hww_esr_r(void) +{ + return 0x00502c98; +} +static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpc0_gpccs_hww_esr_ecc_corrected_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_gpc0_gpccs_hww_esr_ecc_uncorrected_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_r(void) +{ + return 0x00502678; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 10; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f(void) +{ + return 0x400; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 8; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f(void) +{ + return 0x100; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m(void) +{ + return 0x1 << 11; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f(void) +{ + return 0x800; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 9; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_m(void) +{ + return 0x1 << 9; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f(void) +{ + return 0x200; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_reset_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_status_reset_task_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_address_r(void) +{ + return 0x00502684; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_address_index_f(u32 v) +{ + return (v & 0x7fffff) << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_s(void) +{ + return 20; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_f(u32 v) +{ + return (v & 0xfffff) << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_m(void) +{ + return 0xfffff << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_address_row_address_v(u32 r) +{ + return (r >> 0) & 0xfffff; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_r(void) +{ + return 0x0050267c; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_s(void) +{ + return 16; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_m(void) +{ + return 0xffff << 16; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_corrected_err_count_unique_total_v(u32 r) +{ + return (r >> 16) & 0xffff; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_r(void) +{ + return 0x00502680; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_s(void) +{ + return 16; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_m(void) +{ + return 0xffff << 16; +} +static inline u32 gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) +{ + return (r >> 16) & 0xffff; +} +static inline u32 gr_fecs_falcon_ecc_status_r(void) +{ + return 0x00409678; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_imem_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_dmem_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_imem_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_m(void) +{ + return 0x1 << 5; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_dmem_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 10; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_pending_f(void) +{ + return 0x400; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_m(void) +{ + return 0x1 << 8; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_total_counter_overflow_pending_f(void) +{ + return 0x100; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_m(void) +{ + return 0x1 << 11; +} +static inline u32 gr_fecs_falcon_ecc_status_uncorrected_err_unique_counter_overflow_pending_f(void) +{ + return 0x800; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_f(u32 v) +{ + return (v & 0x1) << 9; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_m(void) +{ + return 0x1 << 9; +} +static inline u32 gr_fecs_falcon_ecc_status_corrected_err_unique_counter_overflow_pending_f(void) +{ + return 0x200; +} +static inline u32 gr_fecs_falcon_ecc_status_reset_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_fecs_falcon_ecc_status_reset_task_f(void) +{ + return 0x80000000; +} +static inline u32 gr_fecs_falcon_ecc_address_r(void) +{ + return 0x00409684; +} +static inline u32 gr_fecs_falcon_ecc_address_index_f(u32 v) +{ + return (v & 0x7fffff) << 0; +} +static inline u32 gr_fecs_falcon_ecc_address_row_address_s(void) +{ + return 20; +} +static inline u32 gr_fecs_falcon_ecc_address_row_address_f(u32 v) +{ + return (v & 0xfffff) << 0; +} +static inline u32 gr_fecs_falcon_ecc_address_row_address_m(void) +{ + return 0xfffff << 0; +} +static inline u32 gr_fecs_falcon_ecc_address_row_address_v(u32 r) +{ + return (r >> 0) & 0xfffff; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_r(void) +{ + return 0x0040967c; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_s(void) +{ + return 16; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_s(void) +{ + return 16; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_m(void) +{ + return 0xffff << 16; +} +static inline u32 gr_fecs_falcon_ecc_corrected_err_count_unique_total_v(u32 r) +{ + return (r >> 16) & 0xffff; +} +static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_r(void) +{ + return 0x00409680; +} +static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_total_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_s(void) +{ + return 16; +} +static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_m(void) +{ + return 0xffff << 16; +} +static inline u32 gr_fecs_falcon_ecc_uncorrected_err_count_unique_total_v(u32 r) +{ + return (r >> 16) & 0xffff; +} #endif -- cgit v1.2.2