From 1cee7b2a390a8b2486b25d2383e4e11667dcff08 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Tue, 27 Jun 2017 21:53:51 +0530 Subject: gpu: nvgpu: falcon interface/HAL update - Add methods to read/write falcon mailbox at interface layer - Created falcon mailbox read/write HAL - Added HAL methods to read/write mailbox - Added macro to get next block based on address - Added macro to get IMEM tag using IMEM address - Added ucode header format Change-Id: I879b1df4538d403cac40fd4ed6e723190f62922c Signed-off-by: Mahantesh Kumbar (cherry picked from commit 30e8b76a7be9d9e6d8225bdc08e441f408692f63) Reviewed-on: https://git-master.nvidia.com/r/1509469 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/common/falcon/falcon.c | 26 +++++++++++++++++++++++ drivers/gpu/nvgpu/gk20a/flcn_gk20a.c | 32 ++++++++++++++++++++++++++++ drivers/gpu/nvgpu/include/nvgpu/falcon.h | 36 ++++++++++++++++++++++++++++++++ 3 files changed, 94 insertions(+) (limited to 'drivers/gpu/nvgpu') diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c index 99b2c249..d8420ece 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon.c @@ -286,6 +286,32 @@ int nvgpu_flcn_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector) return status; } +u32 nvgpu_flcn_mailbox_read(struct nvgpu_falcon *flcn, u32 mailbox_index) +{ + struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; + u32 data = 0; + + if (flcn_ops->mailbox_read) + data = flcn_ops->mailbox_read(flcn, mailbox_index); + else + nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ", + flcn->flcn_id); + + return data; +} + +void nvgpu_flcn_mailbox_write(struct nvgpu_falcon *flcn, u32 mailbox_index, + u32 data) +{ + struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; + + if (flcn_ops->mailbox_write) + flcn_ops->mailbox_write(flcn, mailbox_index, data); + else + nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ", + flcn->flcn_id); +} + void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn) { struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; diff --git a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c index 8d459903..83850a19 100644 --- a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c @@ -402,6 +402,36 @@ static int gk20a_falcon_bootstrap(struct nvgpu_falcon *flcn, return 0; } +static u32 gk20a_falcon_mailbox_read(struct nvgpu_falcon *flcn, + u32 mailbox_index) +{ + struct gk20a *g = flcn->g; + u32 data = 0; + + if (mailbox_index < FALCON_MAILBOX_COUNT) + data = gk20a_readl(g, flcn->flcn_base + (mailbox_index ? + falcon_falcon_mailbox1_r() : + falcon_falcon_mailbox0_r())); + else + nvgpu_err(g, "incorrect mailbox id %d", mailbox_index); + + return data; +} + +static void gk20a_falcon_mailbox_write(struct nvgpu_falcon *flcn, + u32 mailbox_index, u32 data) +{ + struct gk20a *g = flcn->g; + + if (mailbox_index < FALCON_MAILBOX_COUNT) + gk20a_writel(g, flcn->flcn_base + (mailbox_index ? + falcon_falcon_mailbox1_r() : + falcon_falcon_mailbox0_r()), + data); + else + nvgpu_err(g, "incorrect mailbox id %d", mailbox_index); +} + static void gk20a_falcon_dump_imblk(struct nvgpu_falcon *flcn) { struct gk20a *g = flcn->g; @@ -612,6 +642,8 @@ void gk20a_falcon_ops(struct nvgpu_falcon *flcn) flcn_ops->copy_from_imem = gk20a_flcn_copy_from_imem; flcn_ops->bootstrap = gk20a_falcon_bootstrap; flcn_ops->dump_falcon_stats = gk20a_falcon_dump_stats; + flcn_ops->mailbox_read = gk20a_falcon_mailbox_read; + flcn_ops->mailbox_write = gk20a_falcon_mailbox_write; gk20a_falcon_engine_dependency_ops(flcn); } diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h index 888d8e70..4be16576 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/falcon.h +++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h @@ -79,6 +79,15 @@ #define FALCON_REG_RSVD2 (31) #define FALCON_REG_SIZE (32) +#define FALCON_MAILBOX_COUNT 0x02 +#define FALCON_BLOCK_SIZE 0x100 + +#define GET_IMEM_TAG(IMEM_ADDR) (IMEM_ADDR >> 8) + +#define GET_NEXT_BLOCK(ADDR) \ + ((((ADDR + (FALCON_BLOCK_SIZE - 1)) & ~(FALCON_BLOCK_SIZE-1)) \ + / FALCON_BLOCK_SIZE) << 8) + /* * Falcon HWCFG request read types defines */ @@ -113,6 +122,33 @@ enum flcn_mem_type { MEM_IMEM }; +/* Falcon ucode header format + * OS Code Offset + * OS Code Size + * OS Data Offset + * OS Data Size + * NumApps (N) + * App 0 Code Offset + * App 0 Code Size + * . . . . + * App N - 1 Code Offset + * App N - 1 Code Size + * App 0 Data Offset + * App 0 Data Size + * . . . . + * App N - 1 Data Offset + * App N - 1 Data Size + * OS Ovl Offset + * OS Ovl Size +*/ +#define OS_CODE_OFFSET 0x0 +#define OS_CODE_SIZE 0x1 +#define OS_DATA_OFFSET 0x2 +#define OS_DATA_SIZE 0x3 +#define NUM_APPS 0x4 +#define APP_0_CODE_OFFSET 0x5 +#define APP_0_CODE_SIZE 0x6 + struct nvgpu_falcon_dma_info { u32 fb_base; u32 fb_off; -- cgit v1.2.2