From 1ca4c5f069f8b055248aab61619c9a2490b1fe9c Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Wed, 29 Mar 2017 14:28:15 +0530 Subject: gpu: nvgpu: check return value of mutex_init in clk code - check return value of nvgpu_mutex_init in clk_gk20a.c/clk_gm20b.c/clk_gp106.c - add corresponding nvgpu_mutex_destroy calls Jira NVGPU-13 Change-Id: If6ddc2c924e1ab13274b857f904859033722479a Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1321293 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gk20a/clk_gk20a.c | 26 ++++++++++++++++++++------ drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 26 ++++++++++++++++++++------ drivers/gpu/nvgpu/gp106/clk_gp106.c | 16 ++++++++++++++-- 3 files changed, 54 insertions(+), 14 deletions(-) (limited to 'drivers/gpu/nvgpu') diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c index 24bb8eda..38d4b555 100644 --- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c @@ -419,22 +419,30 @@ static int gk20a_init_clk_setup_sw(struct gk20a *g) static int initialized; struct clk *ref; unsigned long ref_rate; + int err; gk20a_dbg_fn(""); + err = nvgpu_mutex_init(&clk->clk_mutex); + if (err) + return err; + if (clk->sw_ready) { gk20a_dbg_fn("skip init"); return 0; } - if (!gk20a_clk_get(g)) - return -EINVAL; + if (!gk20a_clk_get(g)) { + err = -EINVAL; + goto fail; + } ref = clk_get_parent(clk_get_parent(clk->tegra_clk)); if (IS_ERR(ref)) { gk20a_err(dev_from_gk20a(g), "failed to get GPCPLL reference clock"); - return -EINVAL; + err = -EINVAL; + goto fail; } ref_rate = clk_get_rate(ref); @@ -443,7 +451,8 @@ static int gk20a_init_clk_setup_sw(struct gk20a *g) if (clk->gpc_pll.clk_in == 0) { gk20a_err(dev_from_gk20a(g), "GPCPLL reference clock is zero"); - return -EINVAL; + err = -EINVAL; + goto fail; } /* Decide initial frequency */ @@ -457,12 +466,14 @@ static int gk20a_init_clk_setup_sw(struct gk20a *g) clk->gpc_pll.freq /= pl_to_div[clk->gpc_pll.PL]; } - nvgpu_mutex_init(&clk->clk_mutex); - clk->sw_ready = true; gk20a_dbg_fn("done"); return 0; + +fail: + nvgpu_mutex_destroy(&clk->clk_mutex); + return err; } static int gk20a_init_clk_setup_hw(struct gk20a *g) @@ -684,6 +695,9 @@ static int gk20a_suspend_clk_support(struct gk20a *g) ret = clk_disable_gpcpll(g, 1); g->clk.clk_hw_on = false; nvgpu_mutex_release(&g->clk.clk_mutex); + + nvgpu_mutex_destroy(&g->clk.clk_mutex); + return ret; } diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index d6eec0a5..451dd7b6 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c @@ -1122,16 +1122,23 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) struct clk_gk20a *clk = &g->clk; unsigned long safe_rate; struct clk *ref, *c; + int err; gk20a_dbg_fn(""); + err = nvgpu_mutex_init(&clk->clk_mutex); + if (err) + return err; + if (clk->sw_ready) { gk20a_dbg_fn("skip init"); return 0; } - if (!gk20a_clk_get(g)) - return -EINVAL; + if (!gk20a_clk_get(g)) { + err = -EINVAL; + goto fail; + } /* * On Tegra GPU clock exposed to frequency governor is a shared user on @@ -1149,7 +1156,8 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) if (IS_ERR(ref)) { gk20a_err(dev_from_gk20a(g), "failed to get GPCPLL reference clock"); - return -EINVAL; + err = -EINVAL; + goto fail; } clk->gpc_pll.id = GK20A_GPC_PLL; @@ -1157,7 +1165,8 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) if (clk->gpc_pll.clk_in == 0) { gk20a_err(dev_from_gk20a(g), "GPCPLL reference clock is zero"); - return -EINVAL; + err = -EINVAL; + goto fail; } safe_rate = tegra_dvfs_get_fmax_at_vmin_safe_t(c); @@ -1191,8 +1200,6 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) } #endif - nvgpu_mutex_init(&clk->clk_mutex); - clk->sw_ready = true; gk20a_dbg_fn("done"); @@ -1200,6 +1207,10 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) clk->gpc_pll.mode == GPC_PLL_MODE_DVFS ? " NA mode," : "", clk->gpc_pll.M, clk->gpc_pll.N, clk->gpc_pll.PL); return 0; + +fail: + nvgpu_mutex_destroy(&clk->clk_mutex); + return err; } @@ -1587,6 +1598,9 @@ static int gm20b_suspend_clk_support(struct gk20a *g) ret = clk_disable_gpcpll(g, 1); g->clk.clk_hw_on = false; nvgpu_mutex_release(&g->clk.clk_mutex); + + nvgpu_mutex_destroy(&g->clk.clk_mutex); + return ret; } diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c index 8869c94b..8bc47ead 100644 --- a/drivers/gpu/nvgpu/gp106/clk_gp106.c +++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c @@ -78,18 +78,23 @@ static int gp106_init_clk_support(struct gk20a *g) { gk20a_dbg_fn(""); - nvgpu_mutex_init(&clk->clk_mutex); + err = nvgpu_mutex_init(&clk->clk_mutex); + if (err) + return err; clk->clk_namemap = (struct namemap_cfg *) nvgpu_kzalloc(g, sizeof(struct namemap_cfg) * NUM_NAMEMAPS); - if (!clk->clk_namemap) + if (!clk->clk_namemap) { + nvgpu_mutex_destroy(&clk->clk_mutex); return -ENOMEM; + } clk->namemap_xlat_table = nvgpu_kcalloc(g, NUM_NAMEMAPS, sizeof(u32)); if (!clk->namemap_xlat_table) { nvgpu_kfree(g, clk->clk_namemap); + nvgpu_mutex_destroy(&clk->clk_mutex); return -ENOMEM; } @@ -265,8 +270,15 @@ err_out: } #endif /* CONFIG_DEBUG_FS */ +static int gp106_suspend_clk_support(struct gk20a *g) +{ + nvgpu_mutex_destroy(&g->clk.clk_mutex); + return 0; +} + void gp106_init_clk_ops(struct gpu_ops *gops) { gops->clk.init_clk_support = gp106_init_clk_support; gops->clk.get_crystal_clk_hz = gp106_crystal_clk_hz; gops->clk.measure_freq = gp106_clk_measure_freq; + gops->clk.suspend_clk_support = gp106_suspend_clk_support; } -- cgit v1.2.2