From 17aeb7e87ecfc103d90c93902414e59509a51497 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 19 Sep 2014 13:39:36 +0300 Subject: gpu: nvgpu: Fix calculation of MMU debug address Fix calculation of the debug buffer address. Bug 1551221 Change-Id: I8d7921070549a1689dba0675d83bfdbf76ba5193 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/500705 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Riku Salminen Tested-by: Riku Salminen Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 21 +++++++-------------- drivers/gpu/nvgpu/gk20a/hw_fb_gk20a.h | 8 ++++---- 2 files changed, 11 insertions(+), 18 deletions(-) (limited to 'drivers/gpu/nvgpu') diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 0c71ece3..90838c64 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c @@ -4239,7 +4239,6 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) struct aiv_list_gk20a *sw_ctx_load = &g->gr.ctx_vars.sw_ctx_load; struct av_list_gk20a *sw_method_init = &g->gr.ctx_vars.sw_method_init; u32 data; - u32 addr_lo, addr_hi; u64 addr; unsigned long end_jiffies = jiffies + msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); @@ -4249,31 +4248,25 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) gk20a_dbg_fn(""); - if (g->ops.gr.init_gpc_mmu) - g->ops.gr.init_gpc_mmu(g); - /* init mmu debug buffer */ addr = NV_MC_SMMU_VADDR_TRANSLATE(gr->mmu_wr_mem.iova); - addr_lo = u64_lo32(addr); - addr_hi = u64_hi32(addr); - addr = (addr_lo >> fb_mmu_debug_wr_addr_alignment_v()) | - (addr_hi << (32 - fb_mmu_debug_wr_addr_alignment_v())); + addr >>= fb_mmu_debug_wr_addr_alignment_v(); gk20a_writel(g, fb_mmu_debug_wr_r(), fb_mmu_debug_wr_aperture_vid_mem_f() | fb_mmu_debug_wr_vol_false_f() | - fb_mmu_debug_wr_addr_v(addr)); + fb_mmu_debug_wr_addr_f(addr)); addr = NV_MC_SMMU_VADDR_TRANSLATE(gr->mmu_rd_mem.iova); - addr_lo = u64_lo32(addr); - addr_hi = u64_hi32(addr); - addr = (addr_lo >> fb_mmu_debug_rd_addr_alignment_v()) | - (addr_hi << (32 - fb_mmu_debug_rd_addr_alignment_v())); + addr >>= fb_mmu_debug_rd_addr_alignment_v(); gk20a_writel(g, fb_mmu_debug_rd_r(), fb_mmu_debug_rd_aperture_vid_mem_f() | fb_mmu_debug_rd_vol_false_f() | - fb_mmu_debug_rd_addr_v(addr)); + fb_mmu_debug_rd_addr_f(addr)); + + if (g->ops.gr.init_gpc_mmu) + g->ops.gr.init_gpc_mmu(g); /* load gr floorsweeping registers */ data = gk20a_readl(g, gr_gpc0_ppc0_pes_vsc_strem_r()); diff --git a/drivers/gpu/nvgpu/gk20a/hw_fb_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_fb_gk20a.h index b7edc29d..1c50d0d5 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_fb_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_fb_gk20a.h @@ -154,9 +154,9 @@ static inline u32 fb_mmu_debug_wr_vol_true_f(void) { return 0x4; } -static inline u32 fb_mmu_debug_wr_addr_v(u32 r) +static inline u32 fb_mmu_debug_wr_addr_f(u32 v) { - return (r >> 4) & 0xfffffff; + return (v & 0xfffffff) << 4; } static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) { @@ -174,9 +174,9 @@ static inline u32 fb_mmu_debug_rd_vol_false_f(void) { return 0x0; } -static inline u32 fb_mmu_debug_rd_addr_v(u32 r) +static inline u32 fb_mmu_debug_rd_addr_f(u32 v) { - return (r >> 4) & 0xfffffff; + return (v & 0xfffffff) << 4; } static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) { -- cgit v1.2.2