From 0dc80244eea4c7e504976d8028a3ddb72ba60b0e Mon Sep 17 00:00:00 2001 From: Sunny He Date: Thu, 22 Jun 2017 16:43:51 -0700 Subject: gpu: nvgpu: Reorganize ltc HAL initialization Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the ltc sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: I1110e301e57b502cf7f97e6739424cb33cc52a69 Signed-off-by: Sunny He Reviewed-on: https://git-master/r/1507564 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/Makefile.nvgpu | 1 - drivers/gpu/nvgpu/gk20a/hal_gk20a.c | 17 +++++++++++++++-- drivers/gpu/nvgpu/gk20a/ltc_gk20a.c | 33 +++++++++------------------------ drivers/gpu/nvgpu/gk20a/ltc_gk20a.h | 20 +++++++++++++++++++- drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 20 +++++++++++++++++--- drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | 26 +++----------------------- drivers/gpu/nvgpu/gm20b/ltc_gm20b.h | 7 +++++-- drivers/gpu/nvgpu/gp106/hal_gp106.c | 22 +++++++++++++++++++--- drivers/gpu/nvgpu/gp106/ltc_gp106.c | 27 --------------------------- drivers/gpu/nvgpu/gp106/ltc_gp106.h | 19 ------------------- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 20 ++++++++++++++++++-- drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 27 ++++----------------------- drivers/gpu/nvgpu/gp10b/ltc_gp10b.h | 10 ++++++++-- 13 files changed, 117 insertions(+), 132 deletions(-) delete mode 100644 drivers/gpu/nvgpu/gp106/ltc_gp106.c delete mode 100644 drivers/gpu/nvgpu/gp106/ltc_gp106.h (limited to 'drivers/gpu/nvgpu') diff --git a/drivers/gpu/nvgpu/Makefile.nvgpu b/drivers/gpu/nvgpu/Makefile.nvgpu index 6ffbdc44..cc1632a0 100644 --- a/drivers/gpu/nvgpu/Makefile.nvgpu +++ b/drivers/gpu/nvgpu/Makefile.nvgpu @@ -197,7 +197,6 @@ nvgpu-y += \ gp106/acr_gp106.o \ gp106/sec2_gp106.o \ gp106/fifo_gp106.o \ - gp106/ltc_gp106.o \ gp106/fb_gp106.o \ gp106/regops_gp106.o \ pstate/pstate.o \ diff --git a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c index b19398a6..27ddbca1 100644 --- a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c @@ -43,7 +43,20 @@ #include -static struct gpu_ops gk20a_ops = { +static const struct gpu_ops gk20a_ops = { + .ltc = { + .determine_L2_size_bytes = gk20a_determine_L2_size_bytes, + .init_comptags = gk20a_ltc_init_comptags, + .cbc_ctrl = gk20a_ltc_cbc_ctrl, + .set_zbc_color_entry = gk20a_ltc_set_zbc_color_entry, + .set_zbc_depth_entry = gk20a_ltc_set_zbc_depth_entry, + .init_cbc = gk20a_ltc_init_cbc, +#ifdef CONFIG_DEBUG_FS + .sync_debugfs = gk20a_ltc_sync_debugfs, +#endif + .init_fs_state = gk20a_ltc_init_fs_state, + .isr = gk20a_ltc_isr, + }, .clock_gating = { .slcg_gr_load_gating_prod = gr_gk20a_slcg_gr_load_gating_prod, @@ -151,6 +164,7 @@ int gk20a_init_hal(struct gk20a *g) struct gpu_ops *gops = &g->ops; struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; + gops->ltc = gk20a_ops.ltc; gops->clock_gating = gk20a_ops.clock_gating; gops->privsecurity = 0; gops->securegpccs = 0; @@ -158,7 +172,6 @@ int gk20a_init_hal(struct gk20a *g) gk20a_init_bus(gops); gk20a_init_mc(gops); gk20a_init_priv_ring(gops); - gk20a_init_ltc(gops); gk20a_init_gr_ops(gops); gk20a_init_fecs_trace_ops(gops); gk20a_init_fb(gops); diff --git a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c index 1d517c27..9220685a 100644 --- a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c @@ -51,7 +51,7 @@ int gk20a_ltc_alloc_virt_cbc(struct gk20a *g, size_t compbit_backing_size) } /* HW reg dependent stuff: */ -static int gk20a_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) +int gk20a_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) { /* max memory size (MB) to cover */ u32 max_size = gr->max_comptag_mem; @@ -125,7 +125,7 @@ static int gk20a_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) return 0; } -static int gk20a_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, +int gk20a_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, u32 min, u32 max) { int err = 0; @@ -196,14 +196,14 @@ out: } -static void gk20a_ltc_init_fs_state(struct gk20a *g) +void gk20a_ltc_init_fs_state(struct gk20a *g) { gk20a_dbg_info("initialize gk20a L2"); g->max_ltc_count = g->ltc_count = 1; } -static void gk20a_ltc_isr(struct gk20a *g) +void gk20a_ltc_isr(struct gk20a *g) { u32 intr; @@ -212,7 +212,7 @@ static void gk20a_ltc_isr(struct gk20a *g) gk20a_writel(g, ltc_ltc0_ltss_intr_r(), intr); } -static int gk20a_determine_L2_size_bytes(struct gk20a *g) +int gk20a_determine_L2_size_bytes(struct gk20a *g) { u32 lts_per_ltc; u32 ways; @@ -256,7 +256,7 @@ static int gk20a_determine_L2_size_bytes(struct gk20a *g) /* * Sets the ZBC color for the passed index. */ -static void gk20a_ltc_set_zbc_color_entry(struct gk20a *g, +void gk20a_ltc_set_zbc_color_entry(struct gk20a *g, struct zbc_entry *color_val, u32 index) { @@ -277,7 +277,7 @@ static void gk20a_ltc_set_zbc_color_entry(struct gk20a *g, /* * Sets the ZBC depth for the passed index. */ -static void gk20a_ltc_set_zbc_depth_entry(struct gk20a *g, +void gk20a_ltc_set_zbc_depth_entry(struct gk20a *g, struct zbc_entry *depth_val, u32 index) { @@ -292,7 +292,7 @@ static void gk20a_ltc_set_zbc_depth_entry(struct gk20a *g, gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r()); } -static void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr) +void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr) { u32 max_size = gr->max_comptag_mem; u32 max_comptag_lines = max_size << 3; @@ -342,7 +342,7 @@ static void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr) } #ifdef CONFIG_DEBUG_FS -static void gk20a_ltc_sync_debugfs(struct gk20a *g) +void gk20a_ltc_sync_debugfs(struct gk20a *g) { u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(); @@ -363,18 +363,3 @@ static void gk20a_ltc_sync_debugfs(struct gk20a *g) nvgpu_spinlock_release(&g->debugfs_lock); } #endif - -void gk20a_init_ltc(struct gpu_ops *gops) -{ - gops->ltc.determine_L2_size_bytes = gk20a_determine_L2_size_bytes; - gops->ltc.init_comptags = gk20a_ltc_init_comptags; - gops->ltc.cbc_ctrl = gk20a_ltc_cbc_ctrl; - gops->ltc.set_zbc_color_entry = gk20a_ltc_set_zbc_color_entry; - gops->ltc.set_zbc_depth_entry = gk20a_ltc_set_zbc_depth_entry; - gops->ltc.init_cbc = gk20a_ltc_init_cbc; -#ifdef CONFIG_DEBUG_FS - gops->ltc.sync_debugfs = gk20a_ltc_sync_debugfs; -#endif - gops->ltc.init_fs_state = gk20a_ltc_init_fs_state; - gops->ltc.isr = gk20a_ltc_isr; -} diff --git a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.h b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.h index 30d4163f..ee7d7f91 100644 --- a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.h @@ -16,8 +16,26 @@ #ifndef LTC_GK20A_H #define LTC_GK20A_H struct gpu_ops; +struct gr_gk20a; +struct zbc_entry; +enum gk20a_cbc_op; -void gk20a_init_ltc(struct gpu_ops *gops); +int gk20a_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr); +int gk20a_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, + u32 min, u32 max); +void gk20a_ltc_init_fs_state(struct gk20a *g); +void gk20a_ltc_isr(struct gk20a *g); +int gk20a_determine_L2_size_bytes(struct gk20a *g); +void gk20a_ltc_set_zbc_color_entry(struct gk20a *g, + struct zbc_entry *color_val, + u32 index); +void gk20a_ltc_set_zbc_depth_entry(struct gk20a *g, + struct zbc_entry *depth_val, + u32 index); +void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr); +#ifdef CONFIG_DEBUG_FS +void gk20a_ltc_sync_debugfs(struct gk20a *g); +#endif int gk20a_ltc_alloc_phys_cbc(struct gk20a *g, size_t compbit_backing_size); int gk20a_ltc_alloc_virt_cbc(struct gk20a *g, size_t compbit_backing_size); #endif diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 831fd5da..53542702 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c @@ -46,7 +46,22 @@ #define PRIV_SECURITY_DISABLE 0x01 -static struct gpu_ops gm20b_ops = { +static const struct gpu_ops gm20b_ops = { + .ltc = { + .determine_L2_size_bytes = gm20b_determine_L2_size_bytes, + .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, + .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, + .init_cbc = gm20b_ltc_init_cbc, + .init_fs_state = gm20b_ltc_init_fs_state, + .init_comptags = gm20b_ltc_init_comptags, + .cbc_ctrl = gm20b_ltc_cbc_ctrl, + .isr = gm20b_ltc_isr, + .cbc_fix_config = gm20b_ltc_cbc_fix_config, + .flush = gm20b_flush_ltc, +#ifdef CONFIG_DEBUG_FS + .sync_debugfs = gm20b_ltc_sync_debugfs, +#endif + }, .clock_gating = { .slcg_bus_load_gating_prod = gm20b_slcg_bus_load_gating_prod, @@ -189,6 +204,7 @@ int gm20b_init_hal(struct gk20a *g) struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; u32 val; + gops->ltc = gm20b_ops.ltc; gops->clock_gating = gm20b_ops.clock_gating; gops->securegpccs = false; gops->pmupstate = false; @@ -222,9 +238,7 @@ int gm20b_init_hal(struct gk20a *g) gk20a_init_bus(gops); gm20b_init_mc(gops); gk20a_init_priv_ring(gops); - gm20b_init_ltc(gops); gm20b_init_gr(gops); - gm20b_init_ltc(gops); gm20b_init_fb(gops); gm20b_init_fifo(gops); gm20b_init_ce2(gops); diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c index e4e385fb..5e938141 100644 --- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c @@ -29,7 +29,7 @@ #include "gk20a/ltc_gk20a.h" #include "ltc_gm20b.h" -static int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) +int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) { /* max memory size (MB) to cover */ u32 max_size = gr->max_comptag_mem; @@ -309,7 +309,7 @@ void gm20b_flush_ltc(struct gk20a *g) } } -static int gm20b_determine_L2_size_bytes(struct gk20a *g) +int gm20b_determine_L2_size_bytes(struct gk20a *g) { u32 lts_per_ltc; u32 ways; @@ -438,7 +438,7 @@ void gm20b_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr) } #ifdef CONFIG_DEBUG_FS -static void gm20b_ltc_sync_debugfs(struct gk20a *g) +void gm20b_ltc_sync_debugfs(struct gk20a *g) { u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(); @@ -459,23 +459,3 @@ static void gm20b_ltc_sync_debugfs(struct gk20a *g) nvgpu_spinlock_release(&g->debugfs_lock); } #endif - -void gm20b_init_ltc(struct gpu_ops *gops) -{ - /* Gk20a reused ops. */ - gops->ltc.determine_L2_size_bytes = gm20b_determine_L2_size_bytes; - gops->ltc.set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry; - gops->ltc.set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry; - gops->ltc.init_cbc = gm20b_ltc_init_cbc; - - /* GM20b specific ops. */ - gops->ltc.init_fs_state = gm20b_ltc_init_fs_state; - gops->ltc.init_comptags = gm20b_ltc_init_comptags; - gops->ltc.cbc_ctrl = gm20b_ltc_cbc_ctrl; - gops->ltc.isr = gm20b_ltc_isr; - gops->ltc.cbc_fix_config = gm20b_ltc_cbc_fix_config; - gops->ltc.flush = gm20b_flush_ltc; -#ifdef CONFIG_DEBUG_FS - gops->ltc.sync_debugfs = gm20b_ltc_sync_debugfs; -#endif -} diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.h b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.h index 4fe83250..b5661d4e 100644 --- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.h @@ -17,6 +17,8 @@ #define _NVHOST_GM20B_LTC struct gpu_ops; +int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr); +int gm20b_determine_L2_size_bytes(struct gk20a *g); void gm20b_ltc_set_zbc_color_entry(struct gk20a *g, struct zbc_entry *color_val, u32 index); @@ -24,8 +26,9 @@ void gm20b_ltc_set_zbc_depth_entry(struct gk20a *g, struct zbc_entry *depth_val, u32 index); void gm20b_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr); - -void gm20b_init_ltc(struct gpu_ops *gops); +#ifdef CONFIG_DEBUG_FS +void gm20b_ltc_sync_debugfs(struct gk20a *g); +#endif void gm20b_ltc_init_fs_state(struct gk20a *g); int gm20b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, u32 min, u32 max); diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index d923e5e9..adea3eb8 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c @@ -20,6 +20,7 @@ #include "gk20a/pramin_gk20a.h" #include "gk20a/flcn_gk20a.h" +#include "gp10b/ltc_gp10b.h" #include "gp10b/gr_gp10b.h" #include "gp10b/fecs_trace_gp10b.h" #include "gp10b/mc_gp10b.h" @@ -32,6 +33,7 @@ #include "gp106/fifo_gp106.h" #include "gp106/regops_gp106.h" +#include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/fifo_gm20b.h" #include "gm20b/pmu_gm20b.h" @@ -42,7 +44,6 @@ #include "gp106/therm_gp106.h" #include "gp106/xve_gp106.h" #include "gp106/fifo_gp106.h" -#include "gp106/ltc_gp106.h" #include "gp106/clk_gp106.h" #include "gp106/mm_gp106.h" #include "gp106/pmu_gp106.h" @@ -58,7 +59,22 @@ #include -static struct gpu_ops gp106_ops = { +static const struct gpu_ops gp106_ops = { + .ltc = { + .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, + .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, + .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, + .init_cbc = NULL, + .init_fs_state = gm20b_ltc_init_fs_state, + .init_comptags = gp10b_ltc_init_comptags, + .cbc_ctrl = gm20b_ltc_cbc_ctrl, + .isr = gp10b_ltc_isr, + .cbc_fix_config = NULL, + .flush = gm20b_flush_ltc, +#ifdef CONFIG_DEBUG_FS + .sync_debugfs = gp10b_ltc_sync_debugfs, +#endif + }, .clock_gating = { .slcg_bus_load_gating_prod = gp106_slcg_bus_load_gating_prod, @@ -229,6 +245,7 @@ int gp106_init_hal(struct gk20a *g) gk20a_dbg_fn(""); + gops->ltc = gp106_ops.ltc; gops->clock_gating = gp106_ops.clock_gating; gops->privsecurity = 1; @@ -239,7 +256,6 @@ int gp106_init_hal(struct gk20a *g) gp10b_init_priv_ring(gops); gp106_init_gr(gops); gp10b_init_fecs_trace_ops(gops); - gp106_init_ltc(gops); gp106_init_fb(gops); gp106_init_fifo(gops); gp10b_init_ce(gops); diff --git a/drivers/gpu/nvgpu/gp106/ltc_gp106.c b/drivers/gpu/nvgpu/gp106/ltc_gp106.c deleted file mode 100644 index 755e4b05..00000000 --- a/drivers/gpu/nvgpu/gp106/ltc_gp106.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include "gk20a/gk20a.h" -#include "gm20b/ltc_gm20b.h" -#include "gp10b/ltc_gp10b.h" -#include "gp106/ltc_gp106.h" - -void gp106_init_ltc(struct gpu_ops *gops) -{ - gp10b_init_ltc(gops); - - /* dGPU does not need the LTC hack */ - gops->ltc.cbc_fix_config = NULL; - gops->ltc.init_cbc = NULL; - gops->ltc.init_fs_state = gm20b_ltc_init_fs_state; -} diff --git a/drivers/gpu/nvgpu/gp106/ltc_gp106.h b/drivers/gpu/nvgpu/gp106/ltc_gp106.h deleted file mode 100644 index 4720d7a1..00000000 --- a/drivers/gpu/nvgpu/gp106/ltc_gp106.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef LTC_GP106_H -#define LTC_GP106_H -struct gpu_ops; - -void gp106_init_ltc(struct gpu_ops *gops); -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index a1906a08..bf7a039c 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -36,6 +36,7 @@ #include "gp10b/therm_gp10b.h" #include "gp10b/priv_ring_gp10b.h" +#include "gm20b/ltc_gm20b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/fifo_gm20b.h" #include "gm20b/pmu_gm20b.h" @@ -51,7 +52,22 @@ #include #include -static struct gpu_ops gp10b_ops = { +static const struct gpu_ops gp10b_ops = { + .ltc = { + .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, + .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, + .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, + .init_cbc = gm20b_ltc_init_cbc, + .init_fs_state = gp10b_ltc_init_fs_state, + .init_comptags = gp10b_ltc_init_comptags, + .cbc_ctrl = gm20b_ltc_cbc_ctrl, + .isr = gp10b_ltc_isr, + .cbc_fix_config = gm20b_ltc_cbc_fix_config, + .flush = gm20b_flush_ltc, +#ifdef CONFIG_DEBUG_FS + .sync_debugfs = gp10b_ltc_sync_debugfs, +#endif + }, .clock_gating = { .slcg_bus_load_gating_prod = gp10b_slcg_bus_load_gating_prod, @@ -196,6 +212,7 @@ int gp10b_init_hal(struct gk20a *g) struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; u32 val; + gops->ltc = gp10b_ops.ltc; gops->clock_gating = gp10b_ops.clock_gating; gops->pmupstate = false; #ifdef CONFIG_TEGRA_ACR @@ -240,7 +257,6 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_priv_ring(gops); gp10b_init_gr(gops); gp10b_init_fecs_trace_ops(gops); - gp10b_init_ltc(gops); gp10b_init_fb(gops); gp10b_init_fifo(gops); gp10b_init_ce(gops); diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index d94e56ce..baa275c7 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c @@ -27,7 +27,7 @@ #include "gk20a/ltc_gk20a.h" #include "ltc_gp10b.h" -static int gp10b_determine_L2_size_bytes(struct gk20a *g) +int gp10b_determine_L2_size_bytes(struct gk20a *g) { u32 tmp; int ret; @@ -47,7 +47,7 @@ static int gp10b_determine_L2_size_bytes(struct gk20a *g) return ret; } -static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) +int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) { /* max memory size (MB) to cover */ u32 max_size = gr->max_comptag_mem; @@ -188,7 +188,7 @@ void gp10b_ltc_isr(struct gk20a *g) } } -static void gp10b_ltc_init_fs_state(struct gk20a *g) +void gp10b_ltc_init_fs_state(struct gk20a *g) { u32 ltc_intr; @@ -206,7 +206,7 @@ static void gp10b_ltc_init_fs_state(struct gk20a *g) } #ifdef CONFIG_DEBUG_FS -static void gp10b_ltc_sync_debugfs(struct gk20a *g) +void gp10b_ltc_sync_debugfs(struct gk20a *g) { u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(); @@ -227,22 +227,3 @@ static void gp10b_ltc_sync_debugfs(struct gk20a *g) nvgpu_spinlock_release(&g->debugfs_lock); } #endif - -void gp10b_init_ltc(struct gpu_ops *gops) -{ - gops->ltc.determine_L2_size_bytes = gp10b_determine_L2_size_bytes; - gops->ltc.set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry; - gops->ltc.set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry; - gops->ltc.init_cbc = gm20b_ltc_init_cbc; - - /* GM20b specific ops. */ - gops->ltc.init_fs_state = gp10b_ltc_init_fs_state; - gops->ltc.init_comptags = gp10b_ltc_init_comptags; - gops->ltc.cbc_ctrl = gm20b_ltc_cbc_ctrl; - gops->ltc.isr = gp10b_ltc_isr; - gops->ltc.cbc_fix_config = gm20b_ltc_cbc_fix_config; - gops->ltc.flush = gm20b_flush_ltc; -#ifdef CONFIG_DEBUG_FS - gops->ltc.sync_debugfs = gp10b_ltc_sync_debugfs; -#endif -} diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.h b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.h index d7571c8d..b5f2cda6 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,5 +16,11 @@ struct gpu_ops; void gp10b_ltc_isr(struct gk20a *g); -void gp10b_init_ltc(struct gpu_ops *gops); + +int gp10b_determine_L2_size_bytes(struct gk20a *g); +int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr); +void gp10b_ltc_init_fs_state(struct gk20a *g); +#ifdef CONFIG_DEBUG_FS +void gp10b_ltc_sync_debugfs(struct gk20a *g); +#endif #endif -- cgit v1.2.2