From 01ba044bdbbfa831eb9f507230bac0a1ed67e4ce Mon Sep 17 00:00:00 2001 From: Aingara Paramakuru Date: Thu, 27 Aug 2015 14:01:45 -0400 Subject: gpu: nvgpu: vgpu: add gp10b support Add support for gp10b in a virtualized environment. Bug 1677153 VFND-693 Change-Id: I919ffa44c6773940a7a3411ee8bbc403a992b7cb Signed-off-by: Aingara Paramakuru Reviewed-on: http://git-master/r/792556 Reviewed-on: http://git-master/r/806193 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/vgpu/gp10b/Makefile | 16 +++ drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c | 20 +++ drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h | 21 +++ drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c | 20 +++ drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h | 21 +++ drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 35 +++++ drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c | 172 +++++++++++++++++++++++++ drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h | 21 +++ 8 files changed, 326 insertions(+) create mode 100644 drivers/gpu/nvgpu/vgpu/gp10b/Makefile create mode 100644 drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c create mode 100644 drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h create mode 100644 drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c create mode 100644 drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h create mode 100644 drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c create mode 100644 drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c create mode 100644 drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h (limited to 'drivers/gpu/nvgpu/vgpu') diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/Makefile b/drivers/gpu/nvgpu/vgpu/gp10b/Makefile new file mode 100644 index 00000000..fed8a08e --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/Makefile @@ -0,0 +1,16 @@ +GCOV_PROFILE := y + +ccflags-$(CONFIG_GK20A) += -I$(srctree)/drivers/gpu/nvgpu +ccflags-$(CONFIG_GK20A) += -I$(srctree)/include +ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/drivers/gpu/nvgpu +ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/include +ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/include/uapi + +ccflags-$(CONFIG_GK20A) += -Wno-multichar +ccflags-y += -Werror + +obj-$(CONFIG_GK20A) += \ + vgpu_hal_gp10b.o \ + vgpu_gr_gp10b.o \ + vgpu_mm_gp10b.o \ + vgpu_fifo_gp10b.o diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c new file mode 100644 index 00000000..34d942c1 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "vgpu_fifo_gp10b.h" + +void vgpu_gp10b_init_fifo_ops(struct gpu_ops *gops) +{ + /* syncpoint protection not supported yet */ + gops->fifo.resetup_ramfc = NULL; +} diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h new file mode 100644 index 00000000..4ede0b6d --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __VGPU_FIFO_GP10B_H__ +#define __VGPU_FIFO_GP10B_H__ + +#include "gk20a/gk20a.h" + +void vgpu_gp10b_init_fifo_ops(struct gpu_ops *gops); + +#endif diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c new file mode 100644 index 00000000..9df29eee --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "vgpu_gr_gp10b.h" +#include "vgpu/gm20b/vgpu_gr_gm20b.h" + +void vgpu_gp10b_init_gr_ops(struct gpu_ops *gops) +{ + vgpu_gm20b_init_gr_ops(gops); +} diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h new file mode 100644 index 00000000..b3be49a7 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __VGPU_GR_GP10B_H__ +#define __VGPU_GR_GP10B_H__ + +#include "gk20a/gk20a.h" + +void vgpu_gp10b_init_gr_ops(struct gpu_ops *gops); + +#endif diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c new file mode 100644 index 00000000..14a7768a --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "vgpu/vgpu.h" +#include "gp10b/hal_gp10b.h" +#include "vgpu_gr_gp10b.h" +#include "vgpu_fifo_gp10b.h" +#include "vgpu_mm_gp10b.h" + +int vgpu_gp10b_init_hal(struct gk20a *g) +{ + int err; + + gk20a_dbg_fn(""); + + err = gp10b_init_hal(g); + if (err) + return err; + + vgpu_init_hal_common(g); + vgpu_gp10b_init_gr_ops(&g->ops); + vgpu_gp10b_init_fifo_ops(&g->ops); + vgpu_gp10b_init_mm_ops(&g->ops); + return 0; +} diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c new file mode 100644 index 00000000..0a769e94 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c @@ -0,0 +1,172 @@ +/* + * Virtualized GPU Memory Management + * + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include "vgpu/vgpu.h" +#include "vgpu_mm_gp10b.h" +#include "gk20a/semaphore_gk20a.h" +#include "gk20a/mm_gk20a.h" + +static int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g) +{ + g->mm.bypass_smmu = true; + g->mm.disable_bigpage = true; + return 0; +} + +static inline int add_mem_desc(struct tegra_vgpu_mem_desc *mem_desc, + u64 addr, u64 size, size_t *oob_size) +{ + if (*oob_size < sizeof(*mem_desc)) + return -ENOMEM; + + mem_desc->addr = addr; + mem_desc->length = size; + *oob_size -= sizeof(*mem_desc); + return 0; +} + +static u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, + u64 map_offset, + struct sg_table *sgt, + u64 buffer_offset, + u64 size, + int pgsz_idx, + u8 kind_v, + u32 ctag_offset, + u32 flags, + int rw_flag, + bool clear_ctags, + bool sparse, + bool priv, + struct vm_gk20a_mapping_batch *batch) +{ + int err = 0; + struct device *d = dev_from_vm(vm); + struct gk20a *g = gk20a_from_vm(vm); + struct gk20a_platform *platform = gk20a_get_platform(g->dev); + struct tegra_vgpu_cmd_msg msg; + struct tegra_vgpu_as_map_ex_params *p = &msg.params.as_map_ex; + struct tegra_vgpu_mem_desc *mem_desc; + u32 page_size = vm->gmmu_page_sizes[pgsz_idx]; + u64 space_to_skip = buffer_offset; + u64 buffer_size = 0; + u32 mem_desc_count = 0; + struct scatterlist *sgl; + void *handle = NULL; + size_t oob_size; + u8 prot; + + gk20a_dbg_fn(""); + + /* FIXME: add support for sparse mappings */ + + if (WARN_ON(!sgt) || WARN_ON(!g->mm.bypass_smmu)) + return -EINVAL; + + if (space_to_skip & (page_size - 1)) + return -EINVAL; + + /* Allocate (or validate when map_offset != 0) the virtual address. */ + if (!map_offset) { + map_offset = gk20a_vm_alloc_va(vm, size, pgsz_idx); + if (!map_offset) { + gk20a_err(d, "failed to allocate va space"); + err = -ENOMEM; + goto fail; + } + } + + handle = tegra_gr_comm_oob_get_ptr(TEGRA_GR_COMM_CTX_CLIENT, + tegra_gr_comm_get_server_vmid(), + TEGRA_VGPU_QUEUE_CMD, + (void **)&mem_desc, &oob_size); + if (!handle) { + err = -EINVAL; + goto fail; + } + + sgl = sgt->sgl; + while (space_to_skip && sgl && + (space_to_skip + page_size > sgl->length)) { + space_to_skip -= sgl->length; + sgl = sg_next(sgl); + } + WARN_ON(!sgl); + + if (add_mem_desc(&mem_desc[mem_desc_count++], + sg_phys(sgl) + space_to_skip, + sgl->length - space_to_skip, + &oob_size)) { + err = -ENOMEM; + goto fail; + } + buffer_size += sgl->length - space_to_skip; + + sgl = sg_next(sgl); + while (sgl && buffer_size < size) { + if (add_mem_desc(&mem_desc[mem_desc_count++], sg_phys(sgl), + sgl->length, &oob_size)) { + err = -ENOMEM; + goto fail; + } + + buffer_size += sgl->length; + sgl = sg_next(sgl); + } + + if (rw_flag == gk20a_mem_flag_read_only) + prot = TEGRA_VGPU_MAP_PROT_READ_ONLY; + else if (rw_flag == gk20a_mem_flag_write_only) + prot = TEGRA_VGPU_MAP_PROT_WRITE_ONLY; + else + prot = TEGRA_VGPU_MAP_PROT_NONE; + + msg.cmd = TEGRA_VGPU_CMD_AS_MAP_EX; + msg.handle = platform->virt_handle; + p->handle = vm->handle; + p->gpu_va = map_offset; + p->size = size; + p->mem_desc_count = mem_desc_count; + p->pgsz_idx = pgsz_idx; + p->iova = 0; + p->kind = kind_v; + p->cacheable = + (flags & NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE) ? 1 : 0; + p->prot = prot; + p->ctag_offset = ctag_offset; + p->clear_ctags = clear_ctags; + err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); + if (err || msg.ret) + goto fail; + + /* TLB invalidate handled on server side */ + + tegra_gr_comm_oob_put_ptr(handle); + return map_offset; +fail: + if (handle) + tegra_gr_comm_oob_put_ptr(handle); + gk20a_err(d, "%s: failed with err=%d\n", __func__, err); + return 0; +} + +void vgpu_gp10b_init_mm_ops(struct gpu_ops *gops) +{ + gk20a_dbg_fn(""); + + gops->mm.gmmu_map = vgpu_gp10b_locked_gmmu_map; + gops->mm.init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw; +} diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h new file mode 100644 index 00000000..5bdc9d1b --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __VGPU_MM_GP10B_H__ +#define __VGPU_MM_GP10B_H__ + +#include "gk20a/gk20a.h" + +void vgpu_gp10b_init_mm_ops(struct gpu_ops *gops); + +#endif -- cgit v1.2.2 From 9320d4711f3e39d90d27daae97211d8fc753ba37 Mon Sep 17 00:00:00 2001 From: Aingara Paramakuru Date: Tue, 29 Sep 2015 09:57:37 -0700 Subject: gpu: nvgpu: vgpu: add interface to alloc ctxsw buffers gp10b introduces support for preemption (GfxP and CILP). Add a new interface to allow allocating buffers needed to support this functionality. Bug 1677153 Change-Id: I8578a7b0a4327f3496d852eeb8be5fc778e2c225 Signed-off-by: Aingara Paramakuru Reviewed-on: http://git-master/r/806963 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/817039 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c | 169 +++++++++++++++++++++++++++ 1 file changed, 169 insertions(+) (limited to 'drivers/gpu/nvgpu/vgpu') diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c index 9df29eee..5edaa819 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c @@ -11,10 +11,179 @@ * more details. */ +#include "vgpu/vgpu.h" #include "vgpu_gr_gp10b.h" #include "vgpu/gm20b/vgpu_gr_gm20b.h" +#include "gp10b/hw_gr_gp10b.h" + +static void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, + struct gr_ctx_desc *gr_ctx) +{ + gk20a_dbg_fn(""); + + if (!gr_ctx || !gr_ctx->mem.gpu_va) + return; + + gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.pagepool_ctxsw_buffer); + gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer); + gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer); + gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer); + vgpu_gr_free_gr_ctx(g, vm, gr_ctx); +} + +static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, + struct gr_ctx_desc **__gr_ctx, + struct vm_gk20a *vm, + u32 class, + u32 flags) +{ + struct gk20a_platform *platform = gk20a_get_platform(g->dev); + struct tegra_vgpu_cmd_msg msg; + struct tegra_vgpu_gr_bind_ctxsw_buffers_params *p = + &msg.params.gr_bind_ctxsw_buffers; + struct gr_ctx_desc *gr_ctx = *__gr_ctx; + int err; + + gk20a_dbg_fn(""); + + WARN_ON(TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAX != + TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST); + + err = vgpu_gr_alloc_gr_ctx(g, __gr_ctx, vm, class, flags); + if (err) + return err; + + if (class == PASCAL_A && g->gr.t18x.ctx_vars.force_preemption_gfxp) + flags |= NVGPU_ALLOC_OBJ_FLAGS_GFXP; + + if (class == PASCAL_COMPUTE_A && + g->gr.t18x.ctx_vars.force_preemption_cilp) + flags |= NVGPU_ALLOC_OBJ_FLAGS_CILP; + + if (flags & NVGPU_ALLOC_OBJ_FLAGS_GFXP) { + u32 spill_size = + gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() * + gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); + u32 pagepool_size = g->ops.gr.pagepool_default_size(g) * + gr_scc_pagepool_total_pages_byte_granularity_v(); + u32 betacb_size = g->gr.attrib_cb_default_size + + (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - + gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); + u32 attrib_cb_size = (betacb_size + g->gr.alpha_cb_size) * + gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() * + g->gr.max_tpc_count; + struct mem_desc *desc; + + attrib_cb_size = ALIGN(attrib_cb_size, 128); + + gk20a_dbg_info("gfxp context preempt size=%d", + g->gr.t18x.ctx_vars.preempt_image_size); + gk20a_dbg_info("gfxp context spill size=%d", spill_size); + gk20a_dbg_info("gfxp context pagepool size=%d", pagepool_size); + gk20a_dbg_info("gfxp context attrib cb size=%d", + attrib_cb_size); + + err = gk20a_gmmu_alloc_map(vm, + g->gr.t18x.ctx_vars.preempt_image_size, + &gr_ctx->t18x.preempt_ctxsw_buffer); + if (err) { + err = -ENOMEM; + goto fail; + } + desc = &gr_ctx->t18x.preempt_ctxsw_buffer; + p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->gpu_va; + p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->size; + + err = gk20a_gmmu_alloc_map(vm, spill_size, + &gr_ctx->t18x.spill_ctxsw_buffer); + if (err) { + err = -ENOMEM; + goto fail; + } + desc = &gr_ctx->t18x.spill_ctxsw_buffer; + p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->gpu_va; + p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->size; + + err = gk20a_gmmu_alloc_map(vm, pagepool_size, + &gr_ctx->t18x.pagepool_ctxsw_buffer); + if (err) { + err = -ENOMEM; + goto fail; + } + desc = &gr_ctx->t18x.pagepool_ctxsw_buffer; + p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = + desc->gpu_va; + p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = desc->size; + + err = gk20a_gmmu_alloc_map(vm, attrib_cb_size, + &gr_ctx->t18x.betacb_ctxsw_buffer); + if (err) { + err = -ENOMEM; + goto fail; + } + desc = &gr_ctx->t18x.betacb_ctxsw_buffer; + p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = + desc->gpu_va; + p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = desc->size; + + gr_ctx->preempt_mode = NVGPU_GR_PREEMPTION_MODE_GFXP; + p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_GFX_GFXP; + } + + if (class == PASCAL_COMPUTE_A) { + if (flags & NVGPU_ALLOC_OBJ_FLAGS_CILP) { + gr_ctx->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CILP; + p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CILP; + } else { + gr_ctx->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CTA; + p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CTA; + } + } + + if (gr_ctx->preempt_mode) { + msg.cmd = TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS; + msg.handle = platform->virt_handle; + p->handle = gr_ctx->virt_ctx; + err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); + if (err || msg.ret) { + err = -ENOMEM; + goto fail; + } + } + + gk20a_dbg_fn("done"); + return err; + +fail: + vgpu_gr_gp10b_free_gr_ctx(g, vm, gr_ctx); + return err; +} + +static int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g) +{ + struct gk20a_platform *platform = gk20a_get_platform(g->dev); + int err; + + gk20a_dbg_fn(""); + + err = vgpu_gr_init_ctx_state(g); + if (err) + return err; + + vgpu_get_attribute(platform->virt_handle, + TEGRA_VGPU_ATTRIB_PREEMPT_CTX_SIZE, + &g->gr.t18x.ctx_vars.preempt_image_size); + if (!g->gr.t18x.ctx_vars.preempt_image_size) + return -ENXIO; + + return 0; +} + void vgpu_gp10b_init_gr_ops(struct gpu_ops *gops) { vgpu_gm20b_init_gr_ops(gops); + gops->gr.alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx; + gops->gr.free_gr_ctx = vgpu_gr_gp10b_free_gr_ctx; + gops->gr.init_ctx_state = vgpu_gr_gp10b_init_ctx_state; } -- cgit v1.2.2 From b7de6b004be56e489879616a57bd65a1fbcb0ece Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Mon, 12 Oct 2015 15:24:25 -0700 Subject: gpu: nvgpu: vgpu: set correct page size index for gp10b VM server only know big page and small page, so convert gmmu_page_size_kernel to according page size index. JIRA VFND-890 Change-Id: Id1f932752b8ca33d14635ac9d71019364aa89dc4 Signed-off-by: Richard Zhao Reviewed-on: http://git-master/r/816359 (cherry picked from commit 5bfc4a2a55889f5457bd34aa06861c042ee67421) Reviewed-on: http://git-master/r/827131 GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov --- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'drivers/gpu/nvgpu/vgpu') diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c index 0a769e94..3a286249 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c @@ -134,6 +134,19 @@ static u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, else prot = TEGRA_VGPU_MAP_PROT_NONE; + if (pgsz_idx == gmmu_page_size_kernel) { + if (page_size == vm->gmmu_page_sizes[gmmu_page_size_small]) { + pgsz_idx = gmmu_page_size_small; + } else if (page_size == + vm->gmmu_page_sizes[gmmu_page_size_big]) { + pgsz_idx = gmmu_page_size_big; + } else { + gk20a_err(d, "invalid kernel page size %d\n", + page_size); + goto fail; + } + } + msg.cmd = TEGRA_VGPU_CMD_AS_MAP_EX; msg.handle = platform->virt_handle; p->handle = vm->handle; -- cgit v1.2.2 From 9ab9436268ae2121d3dc57c98d16890953f6cd35 Mon Sep 17 00:00:00 2001 From: Aingara Paramakuru Date: Tue, 3 Nov 2015 11:44:14 -0500 Subject: gpu: nvgpu: gp10b: map GfxP buffers as GPU cacheable Some of the allocated buffers are used during normal graphics processing. Mark them as GPU cacheable to improve performance. Bug 1695718 Change-Id: I71d5d1538516e966526abe5e38a557776321597f Signed-off-by: Aingara Paramakuru Reviewed-on: http://git-master/r/827087 (cherry picked from commit 60b40ac144c94e24a2c449c8be937edf8865e1ed) Reviewed-on: http://git-master/r/828493 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) (limited to 'drivers/gpu/nvgpu/vgpu') diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c index 5edaa819..c5c53b58 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c @@ -84,9 +84,9 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, gk20a_dbg_info("gfxp context attrib cb size=%d", attrib_cb_size); - err = gk20a_gmmu_alloc_map(vm, - g->gr.t18x.ctx_vars.preempt_image_size, - &gr_ctx->t18x.preempt_ctxsw_buffer); + err = gr_gp10b_alloc_buffer(vm, + g->gr.t18x.ctx_vars.preempt_image_size, + &gr_ctx->t18x.preempt_ctxsw_buffer); if (err) { err = -ENOMEM; goto fail; @@ -95,8 +95,9 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->gpu_va; p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->size; - err = gk20a_gmmu_alloc_map(vm, spill_size, - &gr_ctx->t18x.spill_ctxsw_buffer); + err = gr_gp10b_alloc_buffer(vm, + spill_size, + &gr_ctx->t18x.spill_ctxsw_buffer); if (err) { err = -ENOMEM; goto fail; @@ -105,8 +106,9 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->gpu_va; p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->size; - err = gk20a_gmmu_alloc_map(vm, pagepool_size, - &gr_ctx->t18x.pagepool_ctxsw_buffer); + err = gr_gp10b_alloc_buffer(vm, + pagepool_size, + &gr_ctx->t18x.pagepool_ctxsw_buffer); if (err) { err = -ENOMEM; goto fail; @@ -116,8 +118,9 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, desc->gpu_va; p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = desc->size; - err = gk20a_gmmu_alloc_map(vm, attrib_cb_size, - &gr_ctx->t18x.betacb_ctxsw_buffer); + err = gr_gp10b_alloc_buffer(vm, + attrib_cb_size, + &gr_ctx->t18x.betacb_ctxsw_buffer); if (err) { err = -ENOMEM; goto fail; -- cgit v1.2.2 From 36fa64cab4559e3c066b159303fcade7da9124c3 Mon Sep 17 00:00:00 2001 From: Aingara Paramakuru Date: Mon, 14 Dec 2015 20:39:47 -0500 Subject: gpu: nvgpu: vgpu: update interface to free GR ctx The server only releases ownership of the ctxsw buffer mappings after the GR ctx has been released. Update the sequence to account for this. JIRA VFND-1117 Bug 1708163 Change-Id: I3aed015805b4ca51433e7d37ad32de2f8353999f Signed-off-by: Aingara Paramakuru Reviewed-on: http://git-master/r/922817 Reviewed-by: Richard Zhao GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov --- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/vgpu') diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c index c5c53b58..3023ef4b 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c @@ -20,16 +20,30 @@ static void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, struct gr_ctx_desc *gr_ctx) { + struct gk20a_platform *platform = gk20a_get_platform(g->dev); + struct tegra_vgpu_cmd_msg msg; + struct tegra_vgpu_gr_ctx_params *p = &msg.params.gr_ctx; + int err; + gk20a_dbg_fn(""); if (!gr_ctx || !gr_ctx->mem.gpu_va) return; + msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FREE_GR_CTX; + msg.handle = platform->virt_handle; + p->handle = gr_ctx->virt_ctx; + err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); + WARN_ON(err || msg.ret); + + gk20a_vm_free_va(vm, gr_ctx->mem.gpu_va, gr_ctx->mem.size, 0); + gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.pagepool_ctxsw_buffer); gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer); gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer); gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer); - vgpu_gr_free_gr_ctx(g, vm, gr_ctx); + + kfree(gr_ctx); } static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, -- cgit v1.2.2 From 83e9c506eed0bc61b707694756ff716b13fef45d Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Fri, 29 Jan 2016 11:32:44 -0800 Subject: gpu: nvgpu: vgpu: fix sparse warnings Bug 200088648 Change-Id: I61be7b4787e9bc9bac310a8739977f43c38a67ee Signed-off-by: Richard Zhao Reviewed-on: http://git-master/r/1000174 Reviewed-by: Aingara Paramakuru GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/nvgpu/vgpu') diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 14a7768a..b665a8dd 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c @@ -16,6 +16,7 @@ #include "vgpu_gr_gp10b.h" #include "vgpu_fifo_gp10b.h" #include "vgpu_mm_gp10b.h" +#include "nvgpu_gpuid_t18x.h" int vgpu_gp10b_init_hal(struct gk20a *g) { -- cgit v1.2.2 From eada66b2a90d08e3323ec76dfd4ad78f3c9f0ee5 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 8 Mar 2016 10:54:02 -0800 Subject: gpu: nvgpu: gp10b: Allow importing makefile via include Refactor makefiles so that there is one makefile, and that file can be included in the main nvgpu build. Bug 1476801 Change-Id: I23ac451d695fc64064de2300e83b9d9487c52743 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1028353 Reviewed-by: Konsta Holtta GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/vgpu/gp10b/Makefile | 16 ---------------- 1 file changed, 16 deletions(-) delete mode 100644 drivers/gpu/nvgpu/vgpu/gp10b/Makefile (limited to 'drivers/gpu/nvgpu/vgpu') diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/Makefile b/drivers/gpu/nvgpu/vgpu/gp10b/Makefile deleted file mode 100644 index fed8a08e..00000000 --- a/drivers/gpu/nvgpu/vgpu/gp10b/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -GCOV_PROFILE := y - -ccflags-$(CONFIG_GK20A) += -I$(srctree)/drivers/gpu/nvgpu -ccflags-$(CONFIG_GK20A) += -I$(srctree)/include -ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/drivers/gpu/nvgpu -ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/include -ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/include/uapi - -ccflags-$(CONFIG_GK20A) += -Wno-multichar -ccflags-y += -Werror - -obj-$(CONFIG_GK20A) += \ - vgpu_hal_gp10b.o \ - vgpu_gr_gp10b.o \ - vgpu_mm_gp10b.o \ - vgpu_fifo_gp10b.o -- cgit v1.2.2 From 6113c679a99ca09256d33a582a4dfe648e100c23 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Tue, 19 Apr 2016 16:58:28 +0530 Subject: gpu: nvgpu: API to set preemption mode Separate out new API gr_gp10b_set_ctxsw_preemption_mode() which will check requested preemption modes and take appropriate action for each preemption mode This API will also do some sanity checking for valid preemption modes and combinations Define API set_preemption_mode() for gp10b which will set the preemption modes passed as argument and then use gr_gp10b_set_ctxsw_preemption_mode() and update_ctxsw_preemption_mode() to update preemption mode Legacy path from gr_gp10b_alloc_gr_ctx() will convert flags NVGPU_ALLOC_OBJ_FLAGS_* into appropriate preemption modes and then call gr_gp10b_set_ctxsw_preemption_mode() New API set_preemption_mode() will use new flags NVGPU_GRAPHICS/COMPUTE_PREEMPTION_MODE_* and set and update ctxsw preemption mode In gr_gp10b_update_ctxsw_preemption_mode(), update graphics context to set CTA premption mode if mode NVGPU_COMPUTE_PREEMPTION_MODE_CTA is set Also, define preemption modes in nvgpu-t18x.h and use them everywhere Remove old definitions of modes from gr_gp10b.h Bug 1646259 Change-Id: Ib4dc1fb9933b15d32f0122a9e52665b69402df18 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1131806 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/nvgpu/vgpu') diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c index 3023ef4b..08793e18 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c @@ -144,21 +144,21 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, desc->gpu_va; p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = desc->size; - gr_ctx->preempt_mode = NVGPU_GR_PREEMPTION_MODE_GFXP; + gr_ctx->graphics_preempt_mode = NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP; p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_GFX_GFXP; } if (class == PASCAL_COMPUTE_A) { if (flags & NVGPU_ALLOC_OBJ_FLAGS_CILP) { - gr_ctx->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CILP; + gr_ctx->compute_preempt_mode = NVGPU_COMPUTE_PREEMPTION_MODE_CILP; p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CILP; } else { - gr_ctx->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CTA; + gr_ctx->compute_preempt_mode = NVGPU_COMPUTE_PREEMPTION_MODE_CTA; p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CTA; } } - if (gr_ctx->preempt_mode) { + if (gr_ctx->graphics_preempt_mode || gr_ctx->compute_preempt_mode) { msg.cmd = TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS; msg.handle = platform->virt_handle; p->handle = gr_ctx->virt_ctx; -- cgit v1.2.2 From 2029134634fe5292f56ba049fef30fc85a5bcef0 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Mon, 9 May 2016 15:25:44 -0700 Subject: gpu: nvgpu: vgpu: manage gr_ctx as independent resource gr_ctx will managed as independent resource in RM server and vgpu can get a gr_ctx handle. Bug 1702773 Change-Id: Ifceb44b7d9a1ba03fc2a4df847f4a78ac4c4a0d4 Signed-off-by: Richard Zhao Reviewed-on: http://git-master/r/1144934 (cherry picked from commit 0da3101d9b59fe1f9a47ce7b70b30cb8919f35ac) Reviewed-on: http://git-master/r/1150707 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/nvgpu/vgpu') diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c index 08793e18..3194fff1 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -21,7 +21,7 @@ static void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, struct gr_ctx_desc *gr_ctx) { struct gk20a_platform *platform = gk20a_get_platform(g->dev); - struct tegra_vgpu_cmd_msg msg; + struct tegra_vgpu_cmd_msg msg = {0}; struct tegra_vgpu_gr_ctx_params *p = &msg.params.gr_ctx; int err; @@ -30,9 +30,9 @@ static void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, if (!gr_ctx || !gr_ctx->mem.gpu_va) return; - msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FREE_GR_CTX; + msg.cmd = TEGRA_VGPU_CMD_GR_CTX_FREE; msg.handle = platform->virt_handle; - p->handle = gr_ctx->virt_ctx; + p->gr_ctx_handle = gr_ctx->virt_ctx; err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); WARN_ON(err || msg.ret); @@ -53,10 +53,10 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, u32 flags) { struct gk20a_platform *platform = gk20a_get_platform(g->dev); - struct tegra_vgpu_cmd_msg msg; + struct tegra_vgpu_cmd_msg msg = {0}; struct tegra_vgpu_gr_bind_ctxsw_buffers_params *p = &msg.params.gr_bind_ctxsw_buffers; - struct gr_ctx_desc *gr_ctx = *__gr_ctx; + struct gr_ctx_desc *gr_ctx; int err; gk20a_dbg_fn(""); @@ -68,6 +68,8 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, if (err) return err; + gr_ctx = *__gr_ctx; + if (class == PASCAL_A && g->gr.t18x.ctx_vars.force_preemption_gfxp) flags |= NVGPU_ALLOC_OBJ_FLAGS_GFXP; @@ -161,7 +163,7 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, if (gr_ctx->graphics_preempt_mode || gr_ctx->compute_preempt_mode) { msg.cmd = TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS; msg.handle = platform->virt_handle; - p->handle = gr_ctx->virt_ctx; + p->gr_ctx_handle = gr_ctx->virt_ctx; err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); if (err || msg.ret) { err = -ENOMEM; -- cgit v1.2.2 From e175580d52759c4faa0e05eb728340b31fa7c4d6 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 23 Jun 2016 09:22:33 -0700 Subject: gpu: nvgpu: vgpu: Add CE engine to engine list Initialize CE engine also for gp10b. Change-Id: Ibce2f80b523a09fb1345995c03c5430f3b20844f Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1170453 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aingara Paramakuru Tested-by: Aingara Paramakuru GVS: Gerrit_Virtual_Submit Reviewed-by: Lakshmanan M --- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c | 30 +++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/vgpu') diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c index 34d942c1..23d945fb 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -13,8 +13,36 @@ #include "vgpu_fifo_gp10b.h" +static int vgpu_gp10b_fifo_init_engine_info(struct fifo_gk20a *f) +{ + struct fifo_engine_info_gk20a *gr_info; + struct fifo_engine_info_gk20a *ce_info; + const u32 gr_sw_id = ENGINE_GR_GK20A; + const u32 ce_sw_id = ENGINE_GRCE_GK20A; + + gk20a_dbg_fn(""); + + f->num_engines = 2; + + gr_info = &f->engine_info[0]; + + /* FIXME: retrieve this from server */ + gr_info->runlist_id = 0; + gr_info->engine_enum = gr_sw_id; + f->active_engines_list[0] = 0; + + ce_info = &f->engine_info[1]; + ce_info->runlist_id = 0; + ce_info->inst_id = 0; + ce_info->engine_enum = ce_sw_id; + f->active_engines_list[1] = 1; + + return 0; +} + void vgpu_gp10b_init_fifo_ops(struct gpu_ops *gops) { /* syncpoint protection not supported yet */ + gops->fifo.init_engine_info = vgpu_gp10b_fifo_init_engine_info; gops->fifo.resetup_ramfc = NULL; } -- cgit v1.2.2 From bc45c8ef2ba7836eba3ffd7a911905322ed17ab4 Mon Sep 17 00:00:00 2001 From: Konsta Holtta Date: Fri, 17 Jun 2016 15:45:38 +0300 Subject: gpu: nvgpu: gp10x: support in-kernel vidmem mappings Propagate the buffer aperture flag in gk20a_locked_gmmu_map up so that buffers represented as a mem_desc and present in vidmem can be mapped to gpu. JIRA DNVGPU-18 JIRA DNVGPU-76 Change-Id: Icd675e83e3c28836f0ed8880425748697713bb0a Signed-off-by: Konsta Holtta Reviewed-on: http://git-master/r/1169296 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/vgpu') diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c index 3a286249..1b6003b3 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c @@ -51,7 +51,8 @@ static u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, bool clear_ctags, bool sparse, bool priv, - struct vm_gk20a_mapping_batch *batch) + struct vm_gk20a_mapping_batch *batch, + enum gk20a_aperture aperture) { int err = 0; struct device *d = dev_from_vm(vm); -- cgit v1.2.2 From a862dd612204813b603dd0c07442488f47c50448 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Thu, 21 Jul 2016 16:56:15 -0700 Subject: gpu: nvgpu: vgpu: move to use vgpu_get_handle helper function JIRA VFND-2103 Change-Id: Ic11cff40e64849cb6abb193bec54d03857433416 Signed-off-by: Richard Zhao Reviewed-on: http://git-master/r/1185205 GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov --- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c | 9 +++------ drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c | 5 ++--- 2 files changed, 5 insertions(+), 9 deletions(-) (limited to 'drivers/gpu/nvgpu/vgpu') diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c index 3194fff1..78205afb 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c @@ -20,7 +20,6 @@ static void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, struct gr_ctx_desc *gr_ctx) { - struct gk20a_platform *platform = gk20a_get_platform(g->dev); struct tegra_vgpu_cmd_msg msg = {0}; struct tegra_vgpu_gr_ctx_params *p = &msg.params.gr_ctx; int err; @@ -31,7 +30,7 @@ static void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, return; msg.cmd = TEGRA_VGPU_CMD_GR_CTX_FREE; - msg.handle = platform->virt_handle; + msg.handle = vgpu_get_handle(g); p->gr_ctx_handle = gr_ctx->virt_ctx; err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); WARN_ON(err || msg.ret); @@ -52,7 +51,6 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, u32 class, u32 flags) { - struct gk20a_platform *platform = gk20a_get_platform(g->dev); struct tegra_vgpu_cmd_msg msg = {0}; struct tegra_vgpu_gr_bind_ctxsw_buffers_params *p = &msg.params.gr_bind_ctxsw_buffers; @@ -162,7 +160,7 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, if (gr_ctx->graphics_preempt_mode || gr_ctx->compute_preempt_mode) { msg.cmd = TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS; - msg.handle = platform->virt_handle; + msg.handle = vgpu_get_handle(g); p->gr_ctx_handle = gr_ctx->virt_ctx; err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); if (err || msg.ret) { @@ -181,7 +179,6 @@ fail: static int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g) { - struct gk20a_platform *platform = gk20a_get_platform(g->dev); int err; gk20a_dbg_fn(""); @@ -190,7 +187,7 @@ static int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g) if (err) return err; - vgpu_get_attribute(platform->virt_handle, + vgpu_get_attribute(vgpu_get_handle(g), TEGRA_VGPU_ATTRIB_PREEMPT_CTX_SIZE, &g->gr.t18x.ctx_vars.preempt_image_size); if (!g->gr.t18x.ctx_vars.preempt_image_size) diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c index 1b6003b3..8be6b19c 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c @@ -1,7 +1,7 @@ /* * Virtualized GPU Memory Management * - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -57,7 +57,6 @@ static u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, int err = 0; struct device *d = dev_from_vm(vm); struct gk20a *g = gk20a_from_vm(vm); - struct gk20a_platform *platform = gk20a_get_platform(g->dev); struct tegra_vgpu_cmd_msg msg; struct tegra_vgpu_as_map_ex_params *p = &msg.params.as_map_ex; struct tegra_vgpu_mem_desc *mem_desc; @@ -149,7 +148,7 @@ static u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, } msg.cmd = TEGRA_VGPU_CMD_AS_MAP_EX; - msg.handle = platform->virt_handle; + msg.handle = vgpu_get_handle(g); p->handle = vm->handle; p->gpu_va = map_offset; p->size = size; -- cgit v1.2.2 From cb78f5aa749fcea198851ae4adf6e3acd47b37ac Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Mon, 10 Oct 2016 11:32:05 -0700 Subject: gpu: nvgpu: vgpu: add set_preemption_mode Implement HAL callback set_preemption_mode Bug 200238497 JIRA VFND-2683 Change-Id: I8fca8e1ba112d8782ce18f0899eca38a1d12b512 Signed-off-by: Richard Zhao Reviewed-on: http://git-master/r/1236976 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c | 149 ++++++++++++++++++++++++--- 1 file changed, 132 insertions(+), 17 deletions(-) (limited to 'drivers/gpu/nvgpu/vgpu') diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c index 78205afb..4746f04b 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c @@ -51,31 +51,80 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, u32 class, u32 flags) { - struct tegra_vgpu_cmd_msg msg = {0}; - struct tegra_vgpu_gr_bind_ctxsw_buffers_params *p = - &msg.params.gr_bind_ctxsw_buffers; struct gr_ctx_desc *gr_ctx; + u32 graphics_preempt_mode = 0; + u32 compute_preempt_mode = 0; int err; gk20a_dbg_fn(""); - WARN_ON(TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAX != - TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST); - err = vgpu_gr_alloc_gr_ctx(g, __gr_ctx, vm, class, flags); if (err) return err; gr_ctx = *__gr_ctx; + if (flags & NVGPU_ALLOC_OBJ_FLAGS_GFXP) + graphics_preempt_mode = NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP; + if (flags & NVGPU_ALLOC_OBJ_FLAGS_CILP) + compute_preempt_mode = NVGPU_COMPUTE_PREEMPTION_MODE_CILP; + + if (graphics_preempt_mode || compute_preempt_mode) { + if (g->ops.gr.set_ctxsw_preemption_mode) { + err = g->ops.gr.set_ctxsw_preemption_mode(g, gr_ctx, vm, + class, graphics_preempt_mode, compute_preempt_mode); + if (err) { + gk20a_err(dev_from_gk20a(g), + "set_ctxsw_preemption_mode failed"); + goto fail; + } + } else { + err = -ENOSYS; + goto fail; + } + } + + gk20a_dbg_fn("done"); + return err; + +fail: + vgpu_gr_gp10b_free_gr_ctx(g, vm, gr_ctx); + return err; +} + +static int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, + struct gr_ctx_desc *gr_ctx, + struct vm_gk20a *vm, u32 class, + u32 graphics_preempt_mode, + u32 compute_preempt_mode) +{ + struct tegra_vgpu_cmd_msg msg = {}; + struct tegra_vgpu_gr_bind_ctxsw_buffers_params *p = + &msg.params.gr_bind_ctxsw_buffers; + int err = 0; + + WARN_ON(TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAX != + TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST); + if (class == PASCAL_A && g->gr.t18x.ctx_vars.force_preemption_gfxp) - flags |= NVGPU_ALLOC_OBJ_FLAGS_GFXP; + graphics_preempt_mode = NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP; if (class == PASCAL_COMPUTE_A && g->gr.t18x.ctx_vars.force_preemption_cilp) - flags |= NVGPU_ALLOC_OBJ_FLAGS_CILP; + compute_preempt_mode = NVGPU_COMPUTE_PREEMPTION_MODE_CILP; + + /* check for invalid combinations */ + if ((graphics_preempt_mode == 0) && (compute_preempt_mode == 0)) + return -EINVAL; + + if ((graphics_preempt_mode == NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP) && + (compute_preempt_mode == NVGPU_COMPUTE_PREEMPTION_MODE_CILP)) + return -EINVAL; - if (flags & NVGPU_ALLOC_OBJ_FLAGS_GFXP) { + /* set preemption modes */ + switch (graphics_preempt_mode) { + case NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP: + { u32 spill_size = gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() * gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); @@ -146,15 +195,37 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, gr_ctx->graphics_preempt_mode = NVGPU_GRAPHICS_PREEMPTION_MODE_GFXP; p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_GFX_GFXP; + break; + } + case NVGPU_GRAPHICS_PREEMPTION_MODE_WFI: + gr_ctx->graphics_preempt_mode = graphics_preempt_mode; + break; + + default: + break; } if (class == PASCAL_COMPUTE_A) { - if (flags & NVGPU_ALLOC_OBJ_FLAGS_CILP) { - gr_ctx->compute_preempt_mode = NVGPU_COMPUTE_PREEMPTION_MODE_CILP; - p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CILP; - } else { - gr_ctx->compute_preempt_mode = NVGPU_COMPUTE_PREEMPTION_MODE_CTA; - p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CTA; + switch (compute_preempt_mode) { + case NVGPU_COMPUTE_PREEMPTION_MODE_WFI: + gr_ctx->compute_preempt_mode = + NVGPU_COMPUTE_PREEMPTION_MODE_WFI; + p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_WFI; + break; + case NVGPU_COMPUTE_PREEMPTION_MODE_CTA: + gr_ctx->compute_preempt_mode = + NVGPU_COMPUTE_PREEMPTION_MODE_CTA; + p->mode = + TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CTA; + break; + case NVGPU_COMPUTE_PREEMPTION_MODE_CILP: + gr_ctx->compute_preempt_mode = + NVGPU_COMPUTE_PREEMPTION_MODE_CILP; + p->mode = + TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CILP; + break; + default: + break; } } @@ -169,11 +240,52 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, } } - gk20a_dbg_fn("done"); return err; fail: - vgpu_gr_gp10b_free_gr_ctx(g, vm, gr_ctx); + gk20a_err(dev_from_gk20a(g), "%s failed %d", __func__, err); + return err; +} + +static int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, + u32 graphics_preempt_mode, + u32 compute_preempt_mode) +{ + struct gr_ctx_desc *gr_ctx = ch->ch_ctx.gr_ctx; + struct gk20a *g = ch->g; + struct tsg_gk20a *tsg; + struct vm_gk20a *vm; + u32 class; + int err; + + class = ch->obj_class; + if (!class) + return -EINVAL; + + /* preemption already set ? */ + if (gr_ctx->graphics_preempt_mode || gr_ctx->compute_preempt_mode) + return -EINVAL; + + if (gk20a_is_channel_marked_as_tsg(ch)) { + tsg = &g->fifo.tsg[ch->tsgid]; + vm = tsg->vm; + } else { + vm = ch->vm; + } + + if (g->ops.gr.set_ctxsw_preemption_mode) { + err = g->ops.gr.set_ctxsw_preemption_mode(g, gr_ctx, vm, class, + graphics_preempt_mode, + compute_preempt_mode); + if (err) { + gk20a_err(dev_from_gk20a(g), + "set_ctxsw_preemption_mode failed"); + return err; + } + } else { + err = -ENOSYS; + } + return err; } @@ -202,4 +314,7 @@ void vgpu_gp10b_init_gr_ops(struct gpu_ops *gops) gops->gr.alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx; gops->gr.free_gr_ctx = vgpu_gr_gp10b_free_gr_ctx; gops->gr.init_ctx_state = vgpu_gr_gp10b_init_ctx_state; + gops->gr.set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode; + gops->gr.set_ctxsw_preemption_mode = + vgpu_gr_gp10b_set_ctxsw_preemption_mode; } -- cgit v1.2.2 From d7f15a2b507f05445b97fb410bf788327fef7376 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Wed, 30 Nov 2016 13:50:27 -0800 Subject: gpu: nvgpu: vgpu: fix va leak when call gk20a_vm_free_va page size index needs to be set explicitly when call gk20a_vm_free_va. Bug 200255799 JIRA VFND-3033 Change-Id: Ic23ea68905ea423173d1859fd100e7b2c82a1bcc Signed-off-by: Richard Zhao Reviewed-on: http://git-master/r/1262590 (cherry picked from commit 918aea147b395f7337db348d2616fb4b195dc53a) Reviewed-on: http://git-master/r/1263400 Reviewed-by: Aingara Paramakuru GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov --- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/vgpu') diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c index 4746f04b..85dc8c22 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c @@ -35,7 +35,8 @@ static void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); WARN_ON(err || msg.ret); - gk20a_vm_free_va(vm, gr_ctx->mem.gpu_va, gr_ctx->mem.size, 0); + gk20a_vm_free_va(vm, gr_ctx->mem.gpu_va, gr_ctx->mem.size, + gmmu_page_size_kernel); gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.pagepool_ctxsw_buffer); gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer); -- cgit v1.2.2 From f41740bf08c77f54561f1b957fe552d8234524b7 Mon Sep 17 00:00:00 2001 From: Aparna Das Date: Mon, 12 Dec 2016 12:28:59 -0800 Subject: gpu: nvgpu: vgpu: no support for sparse mapping Currently sparse mapping is not supported for gp10b in virtualized environment. Modify gpu characteristics to reflect non-implementation of this functionality. Also fix return value in vgpu_gp10b_locked_gmmu_map() on error condition. Bug 200243373 Change-Id: Ia367b923b87738a5cad0617cdb074f5a24fb1c81 Signed-off-by: Aparna Das Reviewed-on: http://git-master/r/1269710 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Aingara Paramakuru Reviewed-by: Sachit Kadle Reviewed-by: Konsta Holtta Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov --- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/nvgpu/vgpu') diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c index 8be6b19c..66fda2d9 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c @@ -74,10 +74,10 @@ static u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, /* FIXME: add support for sparse mappings */ if (WARN_ON(!sgt) || WARN_ON(!g->mm.bypass_smmu)) - return -EINVAL; + return 0; if (space_to_skip & (page_size - 1)) - return -EINVAL; + return 0; /* Allocate (or validate when map_offset != 0) the virtual address. */ if (!map_offset) { @@ -182,4 +182,7 @@ void vgpu_gp10b_init_mm_ops(struct gpu_ops *gops) gops->mm.gmmu_map = vgpu_gp10b_locked_gmmu_map; gops->mm.init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw; + + /* FIXME: add support for sparse mappings */ + gops->mm.support_sparse = NULL; } -- cgit v1.2.2