From 6a25181882cdda68dfa4680b35f12c11b47ea036 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Mon, 10 Apr 2017 15:32:59 -0700 Subject: gpu: nvgpu: vgpu: add basic t19x HALs - Added t19x vgpu platform data - Added basic vgpu HAL for gv11b. - Added subctx header HAL. Jira VFND-3796 Change-Id: I2b99364801b41d042b53e057f1a30e1194f354c3 Signed-off-by: Richard Zhao Reviewed-on: https://git-master/r/1474729 GVS: Gerrit_Virtual_Submit Reviewed-by: Aingara Paramakuru Reviewed-by: Terje Bergstrom --- .../nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c | 80 ++++++++++++++++++++++ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c | 26 +++++++ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h | 21 ++++++ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c | 40 +++++++++++ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h | 19 +++++ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 40 +++++++++++ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c | 70 +++++++++++++++++++ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.h | 22 ++++++ 8 files changed, 318 insertions(+) create mode 100644 drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c create mode 100644 drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c create mode 100644 drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h create mode 100644 drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c create mode 100644 drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h create mode 100644 drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c create mode 100644 drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c create mode 100644 drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.h (limited to 'drivers/gpu/nvgpu/vgpu/gv11b') diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c new file mode 100644 index 00000000..a6ed67b2 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "gk20a/gk20a.h" +#include "gk20a/hal_gk20a.h" +#include "gk20a/platform_gk20a.h" +#include "vgpu/clk_vgpu.h" + +#include +#include + +static int gv11b_vgpu_probe(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct gk20a_platform *platform = dev_get_drvdata(dev); + struct resource *r; + void __iomem *regs; + struct fifo_gk20a *f = &platform->g->fifo; + int ret; + + r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "usermode"); + if (!r) { + dev_err(dev, "failed to get usermode regs\n"); + return -ENXIO; + } + regs = devm_ioremap_resource(dev, r); + if (IS_ERR(regs)) { + dev_err(dev, "failed to map usermode regs\n"); + return PTR_ERR(regs); + } + f->t19x.usermode_regs = regs; + +#ifdef CONFIG_TEGRA_GK20A_NVHOST + ret = nvgpu_get_nvhost_dev(platform->g); + if (ret) { + f->t19x.usermode_regs = NULL; + return ret; + } +#endif + vgpu_init_clk_support(platform->g); + + return 0; +} + +struct gk20a_platform gv11b_vgpu_tegra_platform = { + .has_syncpoints = false, + .aggressive_sync_destroy_thresh = 64, + + /* power management configuration */ + .can_railgate_init = false, + .can_elpg_init = false, + .enable_slcg = false, + .enable_blcg = false, + .enable_elcg = false, + .enable_elpg = false, + .enable_aelpg = false, + + .ch_wdt_timeout_ms = 5000, + + .probe = gv11b_vgpu_probe, + .default_big_page_size = SZ_64K, + + .clk_round_rate = vgpu_clk_round_rate, + .get_clk_freqs = vgpu_clk_get_freqs, + + /* frequency scaling configuration */ + .devfreq_governor = "userspace", + + .virtual_dev = true, +}; diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c new file mode 100644 index 00000000..b9df58ec --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include + +#include "vgpu_fifo_gv11b.h" +#include "vgpu_subctx_gv11b.h" + +void vgpu_gv11b_init_fifo_ops(struct gpu_ops *gops) +{ + vgpu_gp10b_init_fifo_ops(gops); + + gops->fifo.init_fifo_setup_hw = NULL; + gops->fifo.free_channel_ctx_header = vgpu_gv11b_free_subctx_header; +} diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h new file mode 100644 index 00000000..a9c13b5f --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _VGPU_FIFO_GV11B_H_ +#define _VGPU_FIFO_GV11B_H_ + +struct gpu_ops; + +void vgpu_gv11b_init_fifo_ops(struct gpu_ops *gops); + +#endif diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c new file mode 100644 index 00000000..fcd31d20 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include + +#include "vgpu_gr_gv11b.h" +#include "vgpu_subctx_gv11b.h" + +static int vgpu_gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) +{ + int err; + + err = vgpu_gv11b_alloc_subctx_header(c); + if (err) + return err; + + err = vgpu_gr_commit_inst(c, gpu_va); + if (err) + vgpu_gv11b_free_subctx_header(c); + + return err; +} + +void vgpu_gv11b_init_gr_ops(struct gpu_ops *gops) +{ + vgpu_gp10b_init_gr_ops(gops); + gops->gr.commit_inst = vgpu_gr_gv11b_commit_inst; +} diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h new file mode 100644 index 00000000..cc3171d4 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _VGPU_GR_GV11B_H_ +#define _VGPU_GR_GV11B_H_ + +void vgpu_gv11b_init_gr_ops(struct gpu_ops *gops); + +#endif diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c new file mode 100644 index 00000000..fff1a386 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include +#include +#include + +#include "vgpu_gr_gv11b.h" +#include "vgpu_fifo_gv11b.h" + +int vgpu_gv11b_init_hal(struct gk20a *g) +{ + int err; + + gk20a_dbg_fn(""); + + err = gv11b_init_hal(g); + if (err) + return err; + + vgpu_init_hal_common(g); + vgpu_gp10b_init_mm_ops(&g->ops); + + vgpu_gv11b_init_gr_ops(&g->ops); + vgpu_gv11b_init_fifo_ops(&g->ops); + + return 0; +} diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c new file mode 100644 index 00000000..93341427 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include + +int vgpu_gv11b_alloc_subctx_header(struct channel_gk20a *c) +{ + struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; + struct tegra_vgpu_cmd_msg msg = {}; + struct tegra_vgpu_alloc_ctx_header_params *p = + &msg.params.t19x.alloc_ctx_header; + struct gr_gk20a *gr = &c->g->gr; + int err; + + msg.cmd = TEGRA_VGPU_CMD_ALLOC_CTX_HEADER; + msg.handle = vgpu_get_handle(c->g); + p->ch_handle = c->virt_ctx; + p->ctx_header_va = __nvgpu_vm_alloc_va(c->vm, + gr->ctx_vars.golden_image_size, + gmmu_page_size_kernel); + if (!p->ctx_header_va) { + nvgpu_err(c->g, "alloc va failed for ctx_header"); + return -ENOMEM; + } + err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); + err = err ? err : msg.ret; + if (unlikely(err)) { + nvgpu_err(c->g, "alloc ctx_header failed err %d", err); + __nvgpu_vm_free_va(c->vm, p->ctx_header_va, + gmmu_page_size_kernel); + return err; + } + ctx->mem.gpu_va = p->ctx_header_va; + + return err; +} + +void vgpu_gv11b_free_subctx_header(struct channel_gk20a *c) +{ + struct ctx_header_desc *ctx = &c->ch_ctx.ctx_header; + struct tegra_vgpu_cmd_msg msg = {}; + struct tegra_vgpu_free_ctx_header_params *p = + &msg.params.t19x.free_ctx_header; + int err; + + if (ctx->mem.gpu_va) { + msg.cmd = TEGRA_VGPU_CMD_FREE_CTX_HEADER; + msg.handle = vgpu_get_handle(c->g); + p->ch_handle = c->virt_ctx; + err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); + err = err ? err : msg.ret; + if (unlikely(err)) + nvgpu_err(c->g, "free ctx_header failed err %d", err); + __nvgpu_vm_free_va(c->vm, ctx->mem.gpu_va, + gmmu_page_size_kernel); + ctx->mem.gpu_va = 0; + } +} diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.h b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.h new file mode 100644 index 00000000..bfcfe65c --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _VGPU_SUBCTX_GV11B_H_ +#define _VGPU_SUBCTX_GV11B_H_ + +struct channel_gk20a; + +int vgpu_gv11b_alloc_subctx_header(struct channel_gk20a *c); +void vgpu_gv11b_free_subctx_header(struct channel_gk20a *c); + +#endif -- cgit v1.2.2 From c865b16337bf37959f6b7e8ff1970d8c3d3a927e Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 23 Jun 2017 13:26:52 -0700 Subject: gpu: nvgpu: gv11b: Per chip default big page size Stop defining per-platform default big page size. It's defined via HAL and inherited from gp10b. JIRA NVGPU-38 Change-Id: If5eedd5d351d5504bdf87489d1aa091d430c43ba Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master/r/1508069 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers/gpu/nvgpu/vgpu/gv11b') diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c index a6ed67b2..446eea26 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c @@ -12,7 +12,6 @@ */ #include "gk20a/gk20a.h" -#include "gk20a/hal_gk20a.h" #include "gk20a/platform_gk20a.h" #include "vgpu/clk_vgpu.h" @@ -68,7 +67,6 @@ struct gk20a_platform gv11b_vgpu_tegra_platform = { .ch_wdt_timeout_ms = 5000, .probe = gv11b_vgpu_probe, - .default_big_page_size = SZ_64K, .clk_round_rate = vgpu_clk_round_rate, .get_clk_freqs = vgpu_clk_get_freqs, -- cgit v1.2.2 From 1ac8f6477df7bd1e1b1c5922b1916ae6450c07ad Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Mon, 21 Aug 2017 15:36:11 -0700 Subject: gpu: nvgpu: vgpu: add TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT Get max subctx count from RM server. Jira VFND-3797 Change-Id: I95de2271a77bedfa8703231fa45da05c7d2da3e6 Signed-off-by: Richard Zhao Reviewed-on: https://git-master.nvidia.com/r/1543018 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/vgpu/gv11b') diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c index b9df58ec..f8f021b7 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c @@ -14,13 +14,31 @@ #include #include +#include "vgpu/vgpu.h" + #include "vgpu_fifo_gv11b.h" #include "vgpu_subctx_gv11b.h" +static int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g) +{ + struct fifo_gk20a *f = &g->fifo; + int err; + + err = vgpu_get_attribute(vgpu_get_handle(g), + TEGRA_VGPU_ATTRIB_MAX_SUBCTX_COUNT, + &f->t19x.max_subctx_count); + if (err) { + nvgpu_err(g, "get max_subctx_count failed %d", err); + return err; + } + + return 0; +} + void vgpu_gv11b_init_fifo_ops(struct gpu_ops *gops) { vgpu_gp10b_init_fifo_ops(gops); - gops->fifo.init_fifo_setup_hw = NULL; + gops->fifo.init_fifo_setup_hw = vgpu_gv11b_init_fifo_setup_hw; gops->fifo.free_channel_ctx_header = vgpu_gv11b_free_subctx_header; } -- cgit v1.2.2 From d61643c0200983dc340d37962bb0a3ca900a3e97 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 25 Sep 2017 08:59:28 -0700 Subject: gpu: nvgpu: gv11b: Change license for common files to MIT Change license of OS independent source code files to MIT. JIRA NVGPU-218 Change-Id: I93c0504f0544ee8ced4898c386b3f5fbaa6a99a9 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1567804 Reviewed-by: svc-mobile-coverity Reviewed-by: David Martinez Nieto Reviewed-by: Seshendra Gadagottu Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit --- .../nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c | 23 +++++++++++++++------- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c | 23 +++++++++++++++------- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h | 23 +++++++++++++++------- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c | 23 +++++++++++++++------- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h | 23 +++++++++++++++------- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 23 +++++++++++++++------- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c | 23 +++++++++++++++------- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.h | 23 +++++++++++++++------- 8 files changed, 128 insertions(+), 56 deletions(-) (limited to 'drivers/gpu/nvgpu/vgpu/gv11b') diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c index 446eea26..887b654d 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c @@ -1,14 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include "gk20a/gk20a.h" diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c index f8f021b7..3df082fc 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c @@ -1,14 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h index a9c13b5f..b3c7f729 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h @@ -1,14 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef _VGPU_FIFO_GV11B_H_ diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c index fcd31d20..a3d1cd90 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c @@ -1,14 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h index cc3171d4..933aa06b 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h @@ -1,14 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef _VGPU_GR_GV11B_H_ diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index fff1a386..34f1198f 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -1,14 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c index 93341427..857e58c4 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c @@ -1,14 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #include diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.h b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.h index bfcfe65c..0e09f4f6 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.h +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.h @@ -1,14 +1,23 @@ /* * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. */ #ifndef _VGPU_SUBCTX_GV11B_H_ -- cgit v1.2.2 From 971987f363751076a9bddddf7deb5a5a17e8739a Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Wed, 20 Sep 2017 11:28:07 -0700 Subject: gpu: nvgpu: vgpu: unset gops->fifo.tsg_verify_status_faulted The native code of fault checking accesses channel registers which is impossible for vgpu. vgpu needs to implement its own later. Bug 200349281 Change-Id: Iea78ad5457bcc30d0545bbe2e1cd1dba76ed2680 Signed-off-by: Richard Zhao Reviewed-on: https://git-master.nvidia.com/r/1564715 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/vgpu/gv11b') diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c index 3df082fc..ff13b11f 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c @@ -50,4 +50,6 @@ void vgpu_gv11b_init_fifo_ops(struct gpu_ops *gops) gops->fifo.init_fifo_setup_hw = vgpu_gv11b_init_fifo_setup_hw; gops->fifo.free_channel_ctx_header = vgpu_gv11b_free_subctx_header; + /* TODO: implement it for CE fault */ + gops->fifo.tsg_verify_status_faulted = NULL; } -- cgit v1.2.2 From 192afccf7c9982ea47b46fd4b7ace4114ff7b45e Mon Sep 17 00:00:00 2001 From: Deepak Goyal Date: Fri, 22 Sep 2017 15:36:36 +0530 Subject: gpu: nvgpu: gv11b: skip clk gating prog for pre-si For pre-silicon platforms, clock gating should be skipped as it is not supported. Added new flags "can_"x"lcg" to check platform capability before programming SLCG,BLCG and ELCG. Bug 200314250 Change-Id: Iec7564b00b988cdd50a02f3130662727839c5047 Signed-off-by: Deepak Goyal Reviewed-on: https://git-master.nvidia.com/r/1566251 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/nvgpu/vgpu/gv11b') diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c index 887b654d..396359c3 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c @@ -72,6 +72,9 @@ struct gk20a_platform gv11b_vgpu_tegra_platform = { .enable_elcg = false, .enable_elpg = false, .enable_aelpg = false, + .can_slcg = false, + .can_blcg = false, + .can_elcg = false, .ch_wdt_timeout_ms = 5000, -- cgit v1.2.2 From b0092ea95c6e1f695912cdb0b13767f3881cb22f Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 27 Sep 2017 15:05:50 -0700 Subject: gpu: nvgpu: gv11b: Abstract IO aperture accessors Implement T19x specific usermode aperture initialization functions. Move usermode_regs field to nvgpu_os_linux_t19x, because it is Linux specific. JIRA NVGPU-259 Change-Id: I9d6ce243a692ab48209d468288ed85f89fb26770 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1569699 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/vgpu/gv11b') diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c index 396359c3..6adbd46b 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c @@ -23,6 +23,7 @@ #include "gk20a/gk20a.h" #include "gk20a/platform_gk20a.h" #include "vgpu/clk_vgpu.h" +#include "common/linux/os_linux.h" #include #include @@ -33,7 +34,7 @@ static int gv11b_vgpu_probe(struct device *dev) struct gk20a_platform *platform = dev_get_drvdata(dev); struct resource *r; void __iomem *regs; - struct fifo_gk20a *f = &platform->g->fifo; + struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(platform->g); int ret; r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "usermode"); @@ -46,12 +47,12 @@ static int gv11b_vgpu_probe(struct device *dev) dev_err(dev, "failed to map usermode regs\n"); return PTR_ERR(regs); } - f->t19x.usermode_regs = regs; + l->t19x.usermode_regs = regs; #ifdef CONFIG_TEGRA_GK20A_NVHOST ret = nvgpu_get_nvhost_dev(platform->g); if (ret) { - f->t19x.usermode_regs = NULL; + l->t19x.usermode_regs = NULL; return ret; } #endif -- cgit v1.2.2 From 4b8dc71de5696679f13f8863bc5775a23e786b34 Mon Sep 17 00:00:00 2001 From: Peter Daifuku Date: Fri, 6 Oct 2017 15:38:11 -0700 Subject: gpu: nvgpu: vgpu: flatten out t19x vgpu hal Instead of calling the native HAL init function then adding multiple layers of modification for VGPU, flatten out the sequence so that all entry points are set statically and visible in a single file. JIRA ESRM-30 Change-Id: I8d277aaccb0e63b2d504e7aba32eb31ef82f4ec0 Signed-off-by: Peter Daifuku Reviewed-on: https://git-master.nvidia.com/r/1574619 Reviewed-by: svc-mobile-coverity Reviewed-by: Richard Zhao GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c | 16 +- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h | 5 +- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c | 10 +- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h | 4 +- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 618 ++++++++++++++++++++++++- 5 files changed, 616 insertions(+), 37 deletions(-) (limited to 'drivers/gpu/nvgpu/vgpu/gv11b') diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c index ff13b11f..048a4c64 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c @@ -21,14 +21,10 @@ */ #include -#include #include "vgpu/vgpu.h" -#include "vgpu_fifo_gv11b.h" -#include "vgpu_subctx_gv11b.h" - -static int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g) +int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g) { struct fifo_gk20a *f = &g->fifo; int err; @@ -43,13 +39,3 @@ static int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g) return 0; } - -void vgpu_gv11b_init_fifo_ops(struct gpu_ops *gops) -{ - vgpu_gp10b_init_fifo_ops(gops); - - gops->fifo.init_fifo_setup_hw = vgpu_gv11b_init_fifo_setup_hw; - gops->fifo.free_channel_ctx_header = vgpu_gv11b_free_subctx_header; - /* TODO: implement it for CE fault */ - gops->fifo.tsg_verify_status_faulted = NULL; -} diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h index b3c7f729..03404542 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h @@ -23,8 +23,7 @@ #ifndef _VGPU_FIFO_GV11B_H_ #define _VGPU_FIFO_GV11B_H_ -struct gpu_ops; - -void vgpu_gv11b_init_fifo_ops(struct gpu_ops *gops); +struct gk20a; +int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g); #endif diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c index a3d1cd90..89952221 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.c @@ -22,12 +22,10 @@ #include #include -#include -#include "vgpu_gr_gv11b.h" #include "vgpu_subctx_gv11b.h" -static int vgpu_gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) +int vgpu_gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) { int err; @@ -41,9 +39,3 @@ static int vgpu_gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) return err; } - -void vgpu_gv11b_init_gr_ops(struct gpu_ops *gops) -{ - vgpu_gp10b_init_gr_ops(gops); - gops->gr.commit_inst = vgpu_gr_gv11b_commit_inst; -} diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h index 933aa06b..562198ca 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gr_gv11b.h @@ -23,6 +23,8 @@ #ifndef _VGPU_GR_GV11B_H_ #define _VGPU_GR_GV11B_H_ -void vgpu_gv11b_init_gr_ops(struct gpu_ops *gops); +struct channel_gk20a; + +int vgpu_gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va); #endif diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 34f1198f..aa661d66 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -23,27 +23,627 @@ #include #include #include +#include +#include +#include +#include +#include +#include +#include #include +#include #include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include #include "vgpu_gr_gv11b.h" #include "vgpu_fifo_gv11b.h" +#include "vgpu_subctx_gv11b.h" + +#include +#include +#include +#include +#include + +static const struct gpu_ops vgpu_gv11b_ops = { + .ltc = { + .determine_L2_size_bytes = vgpu_determine_L2_size_bytes, + .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry, + .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry, + .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry, + .init_cbc = NULL, + .init_fs_state = vgpu_ltc_init_fs_state, + .init_comptags = vgpu_ltc_init_comptags, + .cbc_ctrl = NULL, + .isr = gv11b_ltc_isr, + .cbc_fix_config = gv11b_ltc_cbc_fix_config, + .flush = gm20b_flush_ltc, + .set_enabled = gp10b_ltc_set_enabled, + }, + .ce2 = { + .isr_stall = gv11b_ce_isr, + .isr_nonstall = gp10b_ce_nonstall_isr, + .get_num_pce = vgpu_ce_get_num_pce, + }, + .gr = { + .init_gpc_mmu = gr_gv11b_init_gpc_mmu, + .bundle_cb_defaults = gr_gv11b_bundle_cb_defaults, + .cb_size_default = gr_gv11b_cb_size_default, + .calc_global_ctx_buffer_size = + gr_gv11b_calc_global_ctx_buffer_size, + .commit_global_attrib_cb = gr_gv11b_commit_global_attrib_cb, + .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb, + .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager, + .commit_global_pagepool = gr_gp10b_commit_global_pagepool, + .handle_sw_method = gr_gv11b_handle_sw_method, + .set_alpha_circular_buffer_size = + gr_gv11b_set_alpha_circular_buffer_size, + .set_circular_buffer_size = gr_gv11b_set_circular_buffer_size, + .enable_hww_exceptions = gr_gv11b_enable_hww_exceptions, + .is_valid_class = gr_gv11b_is_valid_class, + .is_valid_gfx_class = gr_gv11b_is_valid_gfx_class, + .is_valid_compute_class = gr_gv11b_is_valid_compute_class, + .get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs, + .get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs, + .init_fs_state = vgpu_gm20b_init_fs_state, + .set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask, + .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, + .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode, + .set_gpc_tpc_mask = gr_gv11b_set_gpc_tpc_mask, + .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask, + .free_channel_ctx = vgpu_gr_free_channel_ctx, + .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx, + .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull, + .get_zcull_info = vgpu_gr_get_zcull_info, + .is_tpc_addr = gr_gm20b_is_tpc_addr, + .get_tpc_num = gr_gm20b_get_tpc_num, + .detect_sm_arch = vgpu_gr_detect_sm_arch, + .add_zbc_color = gr_gp10b_add_zbc_color, + .add_zbc_depth = gr_gp10b_add_zbc_depth, + .zbc_set_table = vgpu_gr_add_zbc, + .zbc_query_table = vgpu_gr_query_zbc, + .pmu_save_zbc = gk20a_pmu_save_zbc, + .add_zbc = gr_gk20a_add_zbc, + .pagepool_default_size = gr_gv11b_pagepool_default_size, + .init_ctx_state = vgpu_gr_gp10b_init_ctx_state, + .alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx, + .free_gr_ctx = vgpu_gr_gp10b_free_gr_ctx, + .update_ctxsw_preemption_mode = + gr_gp10b_update_ctxsw_preemption_mode, + .dump_gr_regs = NULL, + .update_pc_sampling = gr_gm20b_update_pc_sampling, + .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask, + .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp, + .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc, + .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask, + .get_max_fbps_count = vgpu_gr_get_max_fbps_count, + .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, + .wait_empty = gr_gv11b_wait_empty, + .init_cyclestats = gr_gv11b_init_cyclestats, + .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode, + .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, + .bpt_reg_info = gv11b_gr_bpt_reg_info, + .get_access_map = gr_gv11b_get_access_map, + .handle_fecs_error = gr_gv11b_handle_fecs_error, + .handle_sm_exception = gr_gk20a_handle_sm_exception, + .handle_tex_exception = gr_gv11b_handle_tex_exception, + .enable_gpc_exceptions = gr_gv11b_enable_gpc_exceptions, + .enable_exceptions = gr_gv11b_enable_exceptions, + .get_lrf_tex_ltc_dram_override = get_ecc_override_val, + .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode, + .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode, + .record_sm_error_state = gv11b_gr_record_sm_error_state, + .update_sm_error_state = gv11b_gr_update_sm_error_state, + .clear_sm_error_state = vgpu_gr_clear_sm_error_state, + .suspend_contexts = vgpu_gr_suspend_contexts, + .resume_contexts = vgpu_gr_resume_contexts, + .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, + .fuse_override = gp10b_gr_fuse_override, + .init_sm_id_table = gr_gv11b_init_sm_id_table, + .load_smid_config = gr_gv11b_load_smid_config, + .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, + .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, + .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr, + .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr, + .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr, + .setup_rop_mapping = gr_gv11b_setup_rop_mapping, + .program_zcull_mapping = gr_gv11b_program_zcull_mapping, + .commit_global_timeslice = gr_gv11b_commit_global_timeslice, + .commit_inst = vgpu_gr_gv11b_commit_inst, + .write_zcull_ptr = gr_gv11b_write_zcull_ptr, + .write_pm_ptr = gr_gv11b_write_pm_ptr, + .init_elcg_mode = gr_gv11b_init_elcg_mode, + .load_tpc_mask = gr_gv11b_load_tpc_mask, + .inval_icache = gr_gk20a_inval_icache, + .trigger_suspend = gv11b_gr_sm_trigger_suspend, + .wait_for_pause = gr_gk20a_wait_for_pause, + .resume_from_pause = gv11b_gr_resume_from_pause, + .clear_sm_errors = gr_gk20a_clear_sm_errors, + .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions, + .get_esr_sm_sel = gv11b_gr_get_esr_sm_sel, + .sm_debugger_attached = gv11b_gr_sm_debugger_attached, + .suspend_single_sm = gv11b_gr_suspend_single_sm, + .suspend_all_sms = gv11b_gr_suspend_all_sms, + .resume_single_sm = gv11b_gr_resume_single_sm, + .resume_all_sms = gv11b_gr_resume_all_sms, + .get_sm_hww_warp_esr = gv11b_gr_get_sm_hww_warp_esr, + .get_sm_hww_global_esr = gv11b_gr_get_sm_hww_global_esr, + .get_sm_no_lock_down_hww_global_esr_mask = + gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask, + .lock_down_sm = gv11b_gr_lock_down_sm, + .wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down, + .clear_sm_hww = gv11b_gr_clear_sm_hww, + .init_ovr_sm_dsm_perf = gv11b_gr_init_ovr_sm_dsm_perf, + .get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs, + .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, + .set_boosted_ctx = NULL, + .set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode, + .set_czf_bypass = NULL, + .pre_process_sm_exception = gr_gv11b_pre_process_sm_exception, + .set_preemption_buffer_va = gr_gv11b_set_preemption_buffer_va, + .init_preemption_state = NULL, + .update_boosted_ctx = NULL, + .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3, + .create_gr_sysfs = gr_gv11b_create_sysfs, + .set_ctxsw_preemption_mode = vgpu_gr_gp10b_set_ctxsw_preemption_mode, + .is_etpc_addr = gv11b_gr_pri_is_etpc_addr, + .egpc_etpc_priv_addr_table = gv11b_gr_egpc_etpc_priv_addr_table, + .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception, + .zbc_s_query_table = gr_gv11b_zbc_s_query_table, + .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl, + .restore_context_header = gv11b_restore_context_header, + .handle_gpc_gpcmmu_exception = + gr_gv11b_handle_gpc_gpcmmu_exception, + .add_zbc_type_s = gr_gv11b_add_zbc_type_s, + .get_egpc_base = gv11b_gr_get_egpc_base, + .get_egpc_etpc_num = gv11b_gr_get_egpc_etpc_num, + .handle_gpc_gpccs_exception = + gr_gv11b_handle_gpc_gpccs_exception, + .load_zbc_s_tbl = gr_gv11b_load_stencil_tbl, + .access_smpc_reg = gv11b_gr_access_smpc_reg, + .is_egpc_addr = gv11b_gr_pri_is_egpc_addr, + .add_zbc_s = gr_gv11b_add_zbc_stencil, + .handle_gcc_exception = gr_gv11b_handle_gcc_exception, + .init_sw_veid_bundle = gr_gv11b_init_sw_veid_bundle, + .handle_tpc_sm_ecc_exception = + gr_gv11b_handle_tpc_sm_ecc_exception, + .decode_egpc_addr = gv11b_gr_decode_egpc_addr, + .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data, + }, + .fb = { + .reset = gv11b_fb_reset, + .init_hw = gk20a_fb_init_hw, + .init_fs_state = gv11b_fb_init_fs_state, + .init_cbc = gv11b_fb_init_cbc, + .set_mmu_page_size = gm20b_fb_set_mmu_page_size, + .set_use_full_comp_tag_line = + gm20b_fb_set_use_full_comp_tag_line, + .compression_page_size = gp10b_fb_compression_page_size, + .compressible_page_size = gp10b_fb_compressible_page_size, + .vpr_info_fetch = gm20b_fb_vpr_info_fetch, + .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, + .read_wpr_info = gm20b_fb_read_wpr_info, + .is_debug_mode_enabled = NULL, + .set_debug_mode = vgpu_mm_mmu_set_debug_mode, + .tlb_invalidate = vgpu_mm_tlb_invalidate, + .hub_isr = gv11b_fb_hub_isr, + }, + .clock_gating = { + .slcg_bus_load_gating_prod = + gv11b_slcg_bus_load_gating_prod, + .slcg_ce2_load_gating_prod = + gv11b_slcg_ce2_load_gating_prod, + .slcg_chiplet_load_gating_prod = + gv11b_slcg_chiplet_load_gating_prod, + .slcg_ctxsw_firmware_load_gating_prod = + gv11b_slcg_ctxsw_firmware_load_gating_prod, + .slcg_fb_load_gating_prod = + gv11b_slcg_fb_load_gating_prod, + .slcg_fifo_load_gating_prod = + gv11b_slcg_fifo_load_gating_prod, + .slcg_gr_load_gating_prod = + gr_gv11b_slcg_gr_load_gating_prod, + .slcg_ltc_load_gating_prod = + ltc_gv11b_slcg_ltc_load_gating_prod, + .slcg_perf_load_gating_prod = + gv11b_slcg_perf_load_gating_prod, + .slcg_priring_load_gating_prod = + gv11b_slcg_priring_load_gating_prod, + .slcg_pmu_load_gating_prod = + gv11b_slcg_pmu_load_gating_prod, + .slcg_therm_load_gating_prod = + gv11b_slcg_therm_load_gating_prod, + .slcg_xbar_load_gating_prod = + gv11b_slcg_xbar_load_gating_prod, + .blcg_bus_load_gating_prod = + gv11b_blcg_bus_load_gating_prod, + .blcg_ce_load_gating_prod = + gv11b_blcg_ce_load_gating_prod, + .blcg_ctxsw_firmware_load_gating_prod = + gv11b_blcg_ctxsw_firmware_load_gating_prod, + .blcg_fb_load_gating_prod = + gv11b_blcg_fb_load_gating_prod, + .blcg_fifo_load_gating_prod = + gv11b_blcg_fifo_load_gating_prod, + .blcg_gr_load_gating_prod = + gv11b_blcg_gr_load_gating_prod, + .blcg_ltc_load_gating_prod = + gv11b_blcg_ltc_load_gating_prod, + .blcg_pwr_csb_load_gating_prod = + gv11b_blcg_pwr_csb_load_gating_prod, + .blcg_pmu_load_gating_prod = + gv11b_blcg_pmu_load_gating_prod, + .blcg_xbar_load_gating_prod = + gv11b_blcg_xbar_load_gating_prod, + .pg_gr_load_gating_prod = + gr_gv11b_pg_gr_load_gating_prod, + }, + .fifo = { + .init_fifo_setup_hw = vgpu_gv11b_init_fifo_setup_hw, + .bind_channel = vgpu_channel_bind, + .unbind_channel = vgpu_channel_unbind, + .disable_channel = vgpu_channel_disable, + .enable_channel = vgpu_channel_enable, + .alloc_inst = vgpu_channel_alloc_inst, + .free_inst = vgpu_channel_free_inst, + .setup_ramfc = vgpu_channel_setup_ramfc, + .channel_set_priority = vgpu_channel_set_priority, + .channel_set_timeslice = vgpu_channel_set_timeslice, + .default_timeslice_us = vgpu_fifo_default_timeslice_us, + .setup_userd = gk20a_fifo_setup_userd, + .userd_gp_get = gv11b_userd_gp_get, + .userd_gp_put = gv11b_userd_gp_put, + .userd_pb_get = gv11b_userd_pb_get, + .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, + .preempt_channel = vgpu_fifo_preempt_channel, + .preempt_tsg = vgpu_fifo_preempt_tsg, + .enable_tsg = gk20a_enable_tsg, + .disable_tsg = gk20a_disable_tsg, + .tsg_verify_channel_status = NULL, + .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload, + /* TODO: implement it for CE fault */ + .tsg_verify_status_faulted = NULL, + .update_runlist = vgpu_fifo_update_runlist, + .trigger_mmu_fault = NULL, + .get_mmu_fault_info = NULL, + .wait_engine_idle = vgpu_fifo_wait_engine_idle, + .get_num_fifos = gv11b_fifo_get_num_fifos, + .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, + .set_runlist_interleave = vgpu_fifo_set_runlist_interleave, + .tsg_set_timeslice = vgpu_tsg_set_timeslice, + .tsg_open = vgpu_tsg_open, + .force_reset_ch = vgpu_fifo_force_reset_ch, + .engine_enum_from_type = gp10b_fifo_engine_enum_from_type, + .device_info_data_parse = gp10b_device_info_data_parse, + .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v, + .init_engine_info = vgpu_fifo_init_engine_info, + .runlist_entry_size = ram_rl_entry_size_v, + .get_tsg_runlist_entry = gv11b_get_tsg_runlist_entry, + .get_ch_runlist_entry = gv11b_get_ch_runlist_entry, + .is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc, + .dump_pbdma_status = gk20a_dump_pbdma_status, + .dump_eng_status = gv11b_dump_eng_status, + .dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc, + .intr_0_error_mask = gv11b_fifo_intr_0_error_mask, + .is_preempt_pending = gv11b_fifo_is_preempt_pending, + .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs, + .reset_enable_hw = gv11b_init_fifo_reset_enable_hw, + .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg, + .handle_sched_error = gv11b_fifo_handle_sched_error, + .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0, + .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1, + .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers, + .deinit_eng_method_buffers = + gv11b_fifo_deinit_eng_method_buffers, + .tsg_bind_channel = vgpu_tsg_bind_channel, + .tsg_unbind_channel = vgpu_tsg_unbind_channel, +#ifdef CONFIG_TEGRA_GK20A_NVHOST + .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf, + .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, + .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd, + .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size, + .add_syncpt_incr_cmd = gv11b_fifo_add_syncpt_incr_cmd, + .get_syncpt_incr_cmd_size = gv11b_fifo_get_syncpt_incr_cmd_size, +#endif + .resetup_ramfc = NULL, + .reschedule_runlist = NULL, + .device_info_fault_id = top_device_info_data_fault_id_enum_v, + .free_channel_ctx_header = vgpu_gv11b_free_subctx_header, + .preempt_ch_tsg = gv11b_fifo_preempt_ch_tsg, + .handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout, + }, + .gr_ctx = { + .get_netlist_name = gr_gv11b_get_netlist_name, + .is_fw_defined = gr_gv11b_is_firmware_defined, + }, +#ifdef CONFIG_GK20A_CTXSW_TRACE + .fecs_trace = { + .alloc_user_buffer = NULL, + .free_user_buffer = NULL, + .mmap_user_buffer = NULL, + .init = NULL, + .deinit = NULL, + .enable = NULL, + .disable = NULL, + .is_enabled = NULL, + .reset = NULL, + .flush = NULL, + .poll = NULL, + .bind_channel = NULL, + .unbind_channel = NULL, + .max_entries = NULL, + }, +#endif /* CONFIG_GK20A_CTXSW_TRACE */ + .mm = { + /* FIXME: add support for sparse mappings */ + .support_sparse = NULL, + .gmmu_map = vgpu_gp10b_locked_gmmu_map, + .gmmu_unmap = vgpu_locked_gmmu_unmap, + .vm_bind_channel = vgpu_vm_bind_channel, + .fb_flush = vgpu_mm_fb_flush, + .l2_invalidate = vgpu_mm_l2_invalidate, + .l2_flush = vgpu_mm_l2_flush, + .cbc_clean = gk20a_mm_cbc_clean, + .set_big_page_size = gm20b_mm_set_big_page_size, + .get_big_page_sizes = gm20b_mm_get_big_page_sizes, + .get_default_big_page_size = gp10b_mm_get_default_big_page_size, + .gpu_phys_addr = gm20b_gpu_phys_addr, + .get_iommu_bit = gk20a_mm_get_iommu_bit, + .get_mmu_levels = gp10b_mm_get_mmu_levels, + .init_pdb = gp10b_mm_init_pdb, + .init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw, + .is_bar1_supported = gv11b_mm_is_bar1_supported, + .init_inst_block = gv11b_init_inst_block, + .mmu_fault_pending = gv11b_mm_mmu_fault_pending, + .init_bar2_vm = gb10b_init_bar2_vm, + .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, + .remove_bar2_vm = gv11b_mm_remove_bar2_vm, + .fault_info_mem_destroy = gv11b_mm_fault_info_mem_destroy, + }, + .therm = { + .init_therm_setup_hw = gp10b_init_therm_setup_hw, + .elcg_init_idle_filters = gv11b_elcg_init_idle_filters, + }, + .pmu = { + .pmu_setup_elpg = gp10b_pmu_setup_elpg, + .pmu_get_queue_head = pwr_pmu_queue_head_r, + .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, + .pmu_get_queue_tail = pwr_pmu_queue_tail_r, + .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, + .pmu_queue_head = gk20a_pmu_queue_head, + .pmu_queue_tail = gk20a_pmu_queue_tail, + .pmu_msgq_tail = gk20a_pmu_msgq_tail, + .pmu_mutex_size = pwr_pmu_mutex__size_1_v, + .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, + .pmu_mutex_release = gk20a_pmu_mutex_release, + .write_dmatrfbase = gp10b_write_dmatrfbase, + .pmu_elpg_statistics = gp106_pmu_elpg_statistics, + .pmu_pg_init_param = gv11b_pg_gr_init, + .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list, + .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list, + .dump_secure_fuses = pmu_dump_security_fuses_gp10b, + .reset_engine = gp106_pmu_engine_reset, + .is_engine_in_reset = gp106_pmu_is_engine_in_reset, + .pmu_nsbootstrap = gv11b_pmu_bootstrap, + .pmu_pg_set_sub_feature_mask = gv11b_pg_set_subfeature_mask, + .is_pmu_supported = gv11b_is_pmu_supported, + }, + .regops = { + .get_global_whitelist_ranges = + gv11b_get_global_whitelist_ranges, + .get_global_whitelist_ranges_count = + gv11b_get_global_whitelist_ranges_count, + .get_context_whitelist_ranges = + gv11b_get_context_whitelist_ranges, + .get_context_whitelist_ranges_count = + gv11b_get_context_whitelist_ranges_count, + .get_runcontrol_whitelist = gv11b_get_runcontrol_whitelist, + .get_runcontrol_whitelist_count = + gv11b_get_runcontrol_whitelist_count, + .get_runcontrol_whitelist_ranges = + gv11b_get_runcontrol_whitelist_ranges, + .get_runcontrol_whitelist_ranges_count = + gv11b_get_runcontrol_whitelist_ranges_count, + .get_qctl_whitelist = gv11b_get_qctl_whitelist, + .get_qctl_whitelist_count = gv11b_get_qctl_whitelist_count, + .get_qctl_whitelist_ranges = gv11b_get_qctl_whitelist_ranges, + .get_qctl_whitelist_ranges_count = + gv11b_get_qctl_whitelist_ranges_count, + .apply_smpc_war = gv11b_apply_smpc_war, + }, + .mc = { + .intr_enable = mc_gv11b_intr_enable, + .intr_unit_config = mc_gp10b_intr_unit_config, + .isr_stall = mc_gp10b_isr_stall, + .intr_stall = mc_gp10b_intr_stall, + .intr_stall_pause = mc_gp10b_intr_stall_pause, + .intr_stall_resume = mc_gp10b_intr_stall_resume, + .intr_nonstall = mc_gp10b_intr_nonstall, + .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause, + .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume, + .enable = gk20a_mc_enable, + .disable = gk20a_mc_disable, + .reset = gk20a_mc_reset, + .boot_0 = gk20a_mc_boot_0, + .is_intr1_pending = mc_gp10b_is_intr1_pending, + .is_intr_hub_pending = gv11b_mc_is_intr_hub_pending, + }, + .debug = { + .show_dump = NULL, + }, + .dbg_session_ops = { + .exec_reg_ops = vgpu_exec_regops, + .dbg_set_powergate = vgpu_dbg_set_powergate, + .check_and_set_global_reservation = + vgpu_check_and_set_global_reservation, + .check_and_set_context_reservation = + vgpu_check_and_set_context_reservation, + .release_profiler_reservation = + vgpu_release_profiler_reservation, + .perfbuffer_enable = vgpu_perfbuffer_enable, + .perfbuffer_disable = vgpu_perfbuffer_disable, + }, + .bus = { + .init_hw = gk20a_bus_init_hw, + .isr = gk20a_bus_isr, + .read_ptimer = vgpu_read_ptimer, + .get_timestamps_zipper = vgpu_get_timestamps_zipper, + .bar1_bind = NULL, + }, +#if defined(CONFIG_GK20A_CYCLE_STATS) + .css = { + .enable_snapshot = vgpu_css_enable_snapshot_buffer, + .disable_snapshot = vgpu_css_release_snapshot_buffer, + .check_data_available = vgpu_css_flush_snapshots, + .set_handled_snapshots = NULL, + .allocate_perfmon_ids = NULL, + .release_perfmon_ids = NULL, + }, +#endif + .falcon = { + .falcon_hal_sw_init = gk20a_falcon_hal_sw_init, + }, + .priv_ring = { + .isr = gp10b_priv_ring_isr, + }, + .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics, + .get_litter_value = gv11b_get_litter_value, +}; int vgpu_gv11b_init_hal(struct gk20a *g) { - int err; + struct gpu_ops *gops = &g->ops; + struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; + u32 val; + bool priv_security; + + gops->ltc = vgpu_gv11b_ops.ltc; + gops->ce2 = vgpu_gv11b_ops.ce2; + gops->gr = vgpu_gv11b_ops.gr; + gops->fb = vgpu_gv11b_ops.fb; + gops->clock_gating = vgpu_gv11b_ops.clock_gating; + gops->fifo = vgpu_gv11b_ops.fifo; + gops->gr_ctx = vgpu_gv11b_ops.gr_ctx; + gops->mm = vgpu_gv11b_ops.mm; + gops->fecs_trace = vgpu_gv11b_ops.fecs_trace; + gops->therm = vgpu_gv11b_ops.therm; + gops->pmu = vgpu_gv11b_ops.pmu; + gops->regops = vgpu_gv11b_ops.regops; + gops->mc = vgpu_gv11b_ops.mc; + gops->debug = vgpu_gv11b_ops.debug; + gops->dbg_session_ops = vgpu_gv11b_ops.dbg_session_ops; + gops->bus = vgpu_gv11b_ops.bus; +#if defined(CONFIG_GK20A_CYCLE_STATS) + gops->css = vgpu_gv11b_ops.css; +#endif + gops->falcon = vgpu_gv11b_ops.falcon; + gops->priv_ring = vgpu_gv11b_ops.priv_ring; + + /* Lone functions */ + gops->chip_init_gpu_characteristics = + vgpu_gv11b_ops.chip_init_gpu_characteristics; + gops->get_litter_value = vgpu_gv11b_ops.get_litter_value; + + val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); + if (val) { + priv_security = true; + pr_err("priv security is enabled\n"); + } else { + priv_security = false; + pr_err("priv security is disabled\n"); + } + __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false); + __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, priv_security); + __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, priv_security); + + /* priv security dependent ops */ + if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { + /* Add in ops from gm20b acr */ + gops->pmu.prepare_ucode = gp106_prepare_ucode_blob, + gops->pmu.pmu_setup_hw_and_bootstrap = gv11b_bootstrap_hs_flcn, + gops->pmu.get_wpr = gm20b_wpr_info, + gops->pmu.alloc_blob_space = gm20b_alloc_blob_space, + gops->pmu.pmu_populate_loader_cfg = + gp106_pmu_populate_loader_cfg, + gops->pmu.flcn_populate_bl_dmem_desc = + gp106_flcn_populate_bl_dmem_desc, + gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt, + gops->pmu.falcon_clear_halt_interrupt_status = + clear_halt_interrupt_status, + gops->pmu.init_falcon_setup_hw = gv11b_init_pmu_setup_hw1, + + gops->pmu.init_wpr_region = gm20b_pmu_init_acr; + gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; + gops->pmu.is_lazy_bootstrap = gv11b_is_lazy_bootstrap, + gops->pmu.is_priv_load = gv11b_is_priv_load, + + gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; + } else { + /* Inherit from gk20a */ + gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob, + gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1, + + gops->pmu.load_lsfalcon_ucode = NULL; + gops->pmu.init_wpr_region = NULL; + gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; - gk20a_dbg_fn(""); + gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; + } - err = gv11b_init_hal(g); - if (err) - return err; + __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); + gv11b_init_uncompressed_kind_map(); + gv11b_init_kind_attr(); + g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; - vgpu_init_hal_common(g); - vgpu_gp10b_init_mm_ops(&g->ops); + g->name = "gv11b"; - vgpu_gv11b_init_gr_ops(&g->ops); - vgpu_gv11b_init_fifo_ops(&g->ops); + c->twod_class = FERMI_TWOD_A; + c->threed_class = VOLTA_A; + c->compute_class = VOLTA_COMPUTE_A; + c->gpfifo_class = VOLTA_CHANNEL_GPFIFO_A; + c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B; + c->dma_copy_class = VOLTA_DMA_COPY_A; return 0; } -- cgit v1.2.2 From 62e133029d5a89e07e3ba5e96475c0960c0bc3dd Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Mon, 16 Oct 2017 12:38:46 -0700 Subject: gpu: nvgpu: Refactoring nvgpu_vm functions Change required for equivalent change on nvgpu. This is required since a few HALs were added that must be populated for all chips. This patch adds those HAL definitions for gv11b, gv100, and the vgpu. JIRA NVGPU-30 JIRA NVGPU-138 Change-Id: I65374764350a5cacce8624b15d98947fada35a4a Signed-off-by: Alex Waterman Reviewed-on: https://git-master.nvidia.com/r/1579865 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/nvgpu/vgpu/gv11b') diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index aa661d66..80ed59a2 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -436,6 +436,8 @@ static const struct gpu_ops vgpu_gv11b_ops = { .is_bar1_supported = gv11b_mm_is_bar1_supported, .init_inst_block = gv11b_init_inst_block, .mmu_fault_pending = gv11b_mm_mmu_fault_pending, + .get_kind_invalid = gm20b_get_kind_invalid, + .get_kind_pitch = gm20b_get_kind_pitch, .init_bar2_vm = gb10b_init_bar2_vm, .init_bar2_mm_hw_setup = gv11b_init_bar2_mm_hw_setup, .remove_bar2_vm = gv11b_mm_remove_bar2_vm, -- cgit v1.2.2 From 387ecf8a6360f463a129ab569aaef921fe0a2b0e Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Wed, 18 Oct 2017 11:40:46 -0700 Subject: gpu: nvgpu: gv1xx: Remove HAL for restore_context_header gr restore_context_header is not required any more after enabling per context va mode for subcontext. Cleaning-up unused function pointers from gv100 and gv11b HAL. Change-Id: I65cc7d12d3c96726d323defd99726c3e259e7e63 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1581432 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/nvgpu/vgpu/gv11b') diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 80ed59a2..9226206a 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -232,7 +232,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { .handle_tpc_mpc_exception = gr_gv11b_handle_tpc_mpc_exception, .zbc_s_query_table = gr_gv11b_zbc_s_query_table, .load_zbc_s_default_tbl = gr_gv11b_load_stencil_default_tbl, - .restore_context_header = gv11b_restore_context_header, .handle_gpc_gpcmmu_exception = gr_gv11b_handle_gpc_gpcmmu_exception, .add_zbc_type_s = gr_gv11b_add_zbc_type_s, -- cgit v1.2.2 From df4e88a21d51d5e098b66c3094fa91ae633777e5 Mon Sep 17 00:00:00 2001 From: Aparna Das Date: Fri, 4 Aug 2017 17:32:02 -0700 Subject: gpu: nvgpu: vgpu: add support for gv11b syncpoints In t19x, gv11b semaphore read and write operations are translated to host1x syncpoint read and write operations using semaphore syncpoint shim aperture. Implement relevant vgpu hal functions for this in fifo hal. Jira EVLR-1571 Change-Id: I6296cc6e592ea991e1c01bc9662d02fb063ff3c7 Signed-off-by: Aparna Das Reviewed-on: https://git-master.nvidia.com/r/1516367 Reviewed-by: mobile promotions Tested-by: mobile promotions --- .../nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c | 18 ++++- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c | 76 ++++++++++++++++++++++ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h | 2 + drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 2 +- 4 files changed, 95 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/nvgpu/vgpu/gv11b') diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c index 6adbd46b..d48d1308 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c @@ -26,6 +26,8 @@ #include "common/linux/os_linux.h" #include +#include + #include static int gv11b_vgpu_probe(struct device *dev) @@ -35,6 +37,7 @@ static int gv11b_vgpu_probe(struct device *dev) struct resource *r; void __iomem *regs; struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(platform->g); + struct gk20a *g = platform->g; int ret; r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "usermode"); @@ -50,11 +53,22 @@ static int gv11b_vgpu_probe(struct device *dev) l->t19x.usermode_regs = regs; #ifdef CONFIG_TEGRA_GK20A_NVHOST - ret = nvgpu_get_nvhost_dev(platform->g); + ret = nvgpu_get_nvhost_dev(g); if (ret) { l->t19x.usermode_regs = NULL; return ret; } + + ret = nvgpu_nvhost_syncpt_unit_interface_get_aperture(g->nvhost_dev, + &g->syncpt_unit_base, + &g->syncpt_unit_size); + if (ret) { + dev_err(dev, "Failed to get syncpt interface"); + return -ENOSYS; + } + g->syncpt_size = nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(1); + nvgpu_info(g, "syncpt_unit_base %llx syncpt_unit_size %zx size %x\n", + g->syncpt_unit_base, g->syncpt_unit_size, g->syncpt_size); #endif vgpu_init_clk_support(platform->g); @@ -62,7 +76,7 @@ static int gv11b_vgpu_probe(struct device *dev) } struct gk20a_platform gv11b_vgpu_tegra_platform = { - .has_syncpoints = false, + .has_syncpoints = true, .aggressive_sync_destroy_thresh = 64, /* power management configuration */ diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c index 048a4c64..ae9d52a7 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.c @@ -23,6 +23,82 @@ #include #include "vgpu/vgpu.h" +#include "gv11b/fifo_gv11b.h" +#include + +#include + +#ifdef CONFIG_TEGRA_GK20A_NVHOST +int vgpu_gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, + u32 syncpt_id, struct nvgpu_mem *syncpt_buf) +{ + int err; + struct gk20a *g = c->g; + struct vm_gk20a *vm = c->vm; + struct tegra_vgpu_cmd_msg msg = {}; + struct tegra_vgpu_map_syncpt_params *p = &msg.params.t19x.map_syncpt; + + /* + * Add ro map for complete sync point shim range in vm. + * All channels sharing same vm will share same ro mapping. + * Create rw map for current channel sync point. + */ + if (!vm->syncpt_ro_map_gpu_va) { + vm->syncpt_ro_map_gpu_va = __nvgpu_vm_alloc_va(vm, + g->syncpt_unit_size, + gmmu_page_size_kernel); + if (!vm->syncpt_ro_map_gpu_va) { + nvgpu_err(g, "allocating read-only va space failed"); + return -ENOMEM; + } + + msg.cmd = TEGRA_VGPU_CMD_MAP_SYNCPT; + msg.handle = vgpu_get_handle(g); + p->as_handle = c->vm->handle; + p->gpu_va = vm->syncpt_ro_map_gpu_va; + p->len = g->syncpt_unit_size; + p->offset = 0; + p->prot = TEGRA_VGPU_MAP_PROT_READ_ONLY; + err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); + err = err ? err : msg.ret; + if (err) { + nvgpu_err(g, + "mapping read-only va space failed err %d", + err); + __nvgpu_vm_free_va(c->vm, vm->syncpt_ro_map_gpu_va, + gmmu_page_size_kernel); + vm->syncpt_ro_map_gpu_va = 0; + return err; + } + } + + syncpt_buf->gpu_va = __nvgpu_vm_alloc_va(c->vm, g->syncpt_size, + gmmu_page_size_kernel); + if (!syncpt_buf->gpu_va) { + nvgpu_err(g, "allocating syncpt va space failed"); + return -ENOMEM; + } + + msg.cmd = TEGRA_VGPU_CMD_MAP_SYNCPT; + msg.handle = vgpu_get_handle(g); + p->as_handle = c->vm->handle; + p->gpu_va = syncpt_buf->gpu_va; + p->len = g->syncpt_size; + p->offset = + nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(syncpt_id); + p->prot = TEGRA_VGPU_MAP_PROT_NONE; + err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); + err = err ? err : msg.ret; + if (err) { + nvgpu_err(g, "mapping syncpt va space failed err %d", err); + __nvgpu_vm_free_va(c->vm, syncpt_buf->gpu_va, + gmmu_page_size_kernel); + return err; + } + + return 0; +} +#endif /* CONFIG_TEGRA_GK20A_NVHOST */ int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g) { diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h index 03404542..bea935d3 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_fifo_gv11b.h @@ -26,4 +26,6 @@ struct gk20a; int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g); +int vgpu_gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, + u32 syncpt_id, struct nvgpu_mem *syncpt_buf); #endif diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 9226206a..2cd8018c 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -378,7 +378,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .tsg_bind_channel = vgpu_tsg_bind_channel, .tsg_unbind_channel = vgpu_tsg_unbind_channel, #ifdef CONFIG_TEGRA_GK20A_NVHOST - .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf, + .alloc_syncpt_buf = vgpu_gv11b_fifo_alloc_syncpt_buf, .free_syncpt_buf = gv11b_fifo_free_syncpt_buf, .add_syncpt_wait_cmd = gv11b_fifo_add_syncpt_wait_cmd, .get_syncpt_wait_cmd_size = gv11b_fifo_get_syncpt_wait_cmd_size, -- cgit v1.2.2 From c6ccb5f2a1e9a8999436f6c28ed5c416c5418ae3 Mon Sep 17 00:00:00 2001 From: seshendra Gadagottu Date: Mon, 23 Oct 2017 10:20:12 -0700 Subject: gpu: nvgpu: gv11b: use scg perf for smid numbering For SCG to work, smid numbering needs to be done based on scg performance of tpcs. For gv11b and gv11b vgpu, reuse gv100 function "gr_gv100_init_sm_id_table" to do this. Used local variable "index" to avoid multiple computations in the function: gr_gv100_init_sm_id_table index = sm_id + sm Add deug info for printing initialized gpc/tpc/sm/global_tpc indexs. Bug 1842197 Change-Id: Ibf10f47f10a8ca58b86c307a22e159b2cc0d0f43 Signed-off-by: seshendra Gadagottu Reviewed-on: https://git-master.nvidia.com/r/1583916 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/vgpu/gv11b') diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 2cd8018c..7f6df820 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -74,6 +74,8 @@ #include #include +#include + #include #include "vgpu_gr_gv11b.h" @@ -180,7 +182,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .resume_contexts = vgpu_gr_resume_contexts, .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, .fuse_override = gp10b_gr_fuse_override, - .init_sm_id_table = gr_gv11b_init_sm_id_table, + .init_sm_id_table = gr_gv100_init_sm_id_table, .load_smid_config = gr_gv11b_load_smid_config, .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr, -- cgit v1.2.2 From 1cbb5ea0235f15180b1d4299499cab85db23c5ce Mon Sep 17 00:00:00 2001 From: Peter Daifuku Date: Fri, 13 Oct 2017 17:15:46 -0700 Subject: gpu: nvgpu: init_cyclestats fixes - in the native case, replace calls for init_cyclestats with the gm20b version, as each chip had identical versions of the code. - in the virtual case, use the vgpu version of the function in order to get the new max_css_buffer_size characteristic set to the mempool size. JIRA ESRM-54 Bug 200296210 Change-Id: I475876cb392978fb1350ede58e37d0962ae095c3 Signed-off-by: Peter Daifuku Reviewed-on: https://git-master.nvidia.com/r/1578934 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/vgpu/gv11b') diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 7f6df820..80d0ae54 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -162,7 +162,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .get_max_fbps_count = vgpu_gr_get_max_fbps_count, .init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info, .wait_empty = gr_gv11b_wait_empty, - .init_cyclestats = gr_gv11b_init_cyclestats, + .init_cyclestats = vgpu_gr_gm20b_init_cyclestats, .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode, .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs, .bpt_reg_info = gv11b_gr_bpt_reg_info, -- cgit v1.2.2 From f7d8d133bf1b58722ede620fb43fab2053f5e714 Mon Sep 17 00:00:00 2001 From: Aparna Das Date: Wed, 25 Oct 2017 18:20:25 -0700 Subject: gpu: nvgpu: vgpu: unset verify status ctx reload Native code for verifying tsg status on ctx reload is not possible on vgpu. Unset gops->fifo.tsg_verify_status_faulted operation for vgpu for now. This needs to be implemented separately for vgpu later. Bug 200348087 Change-Id:Ib427f66e0897e37c34b882ead95ca8b84d595d72 Signed-off-by: Aparna Das Reviewed-on: https://git-master.nvidia.com/r/1585784 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/vgpu/gv11b') diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 80d0ae54..dd4dfdae 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -342,7 +342,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .enable_tsg = gk20a_enable_tsg, .disable_tsg = gk20a_disable_tsg, .tsg_verify_channel_status = NULL, - .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload, + .tsg_verify_status_ctx_reload = NULL, /* TODO: implement it for CE fault */ .tsg_verify_status_faulted = NULL, .update_runlist = vgpu_fifo_update_runlist, -- cgit v1.2.2 From f913b7a4f9e70df8a76e7b934825ef1d9632f3a1 Mon Sep 17 00:00:00 2001 From: Aparna Das Date: Mon, 30 Oct 2017 16:13:05 -0700 Subject: gpu: nvgpu: vgpu: modify tsg enable sequence TSG enable sequence in native has been modified due to a hardware bug requiring enabling all channels with NEXT and CTX_RELOAD set in a TSG, and then enabling rest of channels.However it is not possible to check if NEXT and CTX_RELOAD is set in vgpu. Have a separate implementation for enabling tsg sequence in vgpu till the fix for hardware bug is implemented for virtualized configuration. Bug 200348087 Change-Id: I8e6c2ba8722531563de65e51e3d6af6acb7af213 Signed-off-by: Aparna Das Reviewed-on: https://git-master.nvidia.com/r/1588739 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Richard Zhao Reviewed-by: Alex Waterman Reviewed-by: Konsta Holtta Reviewed-by: Deepak Nibade GVS: Gerrit_Virtual_Submit Reviewed-by: Nirav Patel Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/vgpu/gv11b') diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index dd4dfdae..e7996ce7 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -339,7 +339,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, .preempt_channel = vgpu_fifo_preempt_channel, .preempt_tsg = vgpu_fifo_preempt_tsg, - .enable_tsg = gk20a_enable_tsg, + .enable_tsg = vgpu_enable_tsg, .disable_tsg = gk20a_disable_tsg, .tsg_verify_channel_status = NULL, .tsg_verify_status_ctx_reload = NULL, -- cgit v1.2.2 From d73e89f984f2f6f8da4e49a0ec3bea0bfc34cde2 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Tue, 31 Oct 2017 19:24:34 +0530 Subject: gpu: nvgpu: move platform_gk20a.h to linux Fix #includes in all the files to include platform_gk20a.h file with correct path NVGPU-316 Change-Id: Icb26d3c75076b8fdc8da992f751e1cfea22996be Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1589939 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/vgpu/gv11b') diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c index d48d1308..fea473a7 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/platform_gv11b_vgpu_tegra.c @@ -21,8 +21,8 @@ */ #include "gk20a/gk20a.h" -#include "gk20a/platform_gk20a.h" #include "vgpu/clk_vgpu.h" +#include "common/linux/platform_gk20a.h" #include "common/linux/os_linux.h" #include -- cgit v1.2.2 From 738bee03730a905d98361cd1260f9b79e3c12bf7 Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Mon, 16 Oct 2017 08:58:59 -0700 Subject: gpu: nvgpu: vgpu: add vgpu_gv11b_tsg_bind_channel Add TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX command to pass subctx_id and runqueu_sel to RM server. Use this command in gv11b's implementation of gops->fifo.tsg_bind_channel. Jira EVLR-1751 Change-Id: I8ba69c95ea1c6bb7fa106588b6420ed543b2386b Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/1579840 Reviewed-by: svc-mobile-coverity Reviewed-by: Richard Zhao GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 3 +- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.c | 59 +++++++++++++++++++++++++++ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.h | 29 +++++++++++++ 3 files changed, 90 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.c create mode 100644 drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.h (limited to 'drivers/gpu/nvgpu/vgpu/gv11b') diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index e7996ce7..56360af4 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -81,6 +81,7 @@ #include "vgpu_gr_gv11b.h" #include "vgpu_fifo_gv11b.h" #include "vgpu_subctx_gv11b.h" +#include "vgpu_tsg_gv11b.h" #include #include @@ -377,7 +378,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .init_eng_method_buffers = gv11b_fifo_init_eng_method_buffers, .deinit_eng_method_buffers = gv11b_fifo_deinit_eng_method_buffers, - .tsg_bind_channel = vgpu_tsg_bind_channel, + .tsg_bind_channel = vgpu_gv11b_tsg_bind_channel, .tsg_unbind_channel = vgpu_tsg_unbind_channel, #ifdef CONFIG_TEGRA_GK20A_NVHOST .alloc_syncpt_buf = vgpu_gv11b_fifo_alloc_syncpt_buf, diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.c new file mode 100644 index 00000000..7e70272a --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.c @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include "vgpu_tsg_gv11b.h" + +int vgpu_gv11b_tsg_bind_channel(struct tsg_gk20a *tsg, + struct channel_gk20a *ch) +{ + struct tegra_vgpu_cmd_msg msg = {}; + struct tegra_vgpu_tsg_bind_channel_ex_params *p = + &msg.params.t19x.tsg_bind_channel_ex; + int err; + + gk20a_dbg_fn(""); + + err = gk20a_tsg_bind_channel(tsg, ch); + if (err) + return err; + + msg.cmd = TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX; + msg.handle = vgpu_get_handle(tsg->g); + p->tsg_id = tsg->tsgid; + p->ch_handle = ch->virt_ctx; + p->subctx_id = ch->t19x.subctx_id; + p->runqueue_sel = ch->t19x.runqueue_sel; + err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); + err = err ? err : msg.ret; + if (err) { + nvgpu_err(tsg->g, + "vgpu_gv11b_tsg_bind_channel failed, ch %d tsgid %d", + ch->chid, tsg->tsgid); + gk20a_tsg_unbind_channel(ch); + } + + return err; +} diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.h b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.h new file mode 100644 index 00000000..c7bb2f4e --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_tsg_gv11b.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _VGPU_TSG_GV11B_H_ +#define _VGPU_TSG_GV11B_H_ + +int vgpu_gv11b_tsg_bind_channel(struct tsg_gk20a *tsg, + struct channel_gk20a *ch); + +#endif -- cgit v1.2.2 From f7f325deb926e4b7253ff31389219c71b9f2148e Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Mon, 21 Aug 2017 15:38:23 -0700 Subject: gpu: nvgpu: vgpu: enable subctx for gv11b Add vgpu_gv11b_init_gpu_characteristics() and enable NVGPU_SUPPORT_TSG_SUBCONTEXTS Jira VFND-3797 Jira EVLR-1751 Change-Id: I288ac062e42ec399a302d693471b50b58c9a2653 Signed-off-by: Thomas Fleury Reviewed-on: https://git-master.nvidia.com/r/1543015 Reviewed-by: Richard Zhao Reviewed-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c | 40 +++++++++++++++++++++++++++ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.h | 21 ++++++++++++++ drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 3 +- 3 files changed, 63 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c create mode 100644 drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.h (limited to 'drivers/gpu/nvgpu/vgpu/gv11b') diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c new file mode 100644 index 00000000..db3dfaf4 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "gk20a/gk20a.h" + +#include +#include + +#include "vgpu/vgpu.h" +#include "vgpu_gv11b.h" + +int vgpu_gv11b_init_gpu_characteristics(struct gk20a *g) +{ + int err; + + gk20a_dbg_fn(""); + + + nvgpu_err(g, "g->gpu_characteristics.flags=%llx", + g->gpu_characteristics.flags); + err = vgpu_init_gpu_characteristics(g); + if (err) { + nvgpu_err(g, "vgpu_init_gpu_characteristics failed, err %d\n", err); + return err; + } + + __nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS, true); + + return 0; +} diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.h b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.h new file mode 100644 index 00000000..9413904b --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _VGPU_GV11B_H_ +#define _VGPU_GV11B_H_ + +struct gk20a; + +int vgpu_gv11b_init_gpu_characteristics(struct gk20a *g); + +#endif diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 56360af4..5adb8ecd 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -78,6 +78,7 @@ #include +#include "vgpu_gv11b.h" #include "vgpu_gr_gv11b.h" #include "vgpu_fifo_gv11b.h" #include "vgpu_subctx_gv11b.h" @@ -551,7 +552,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { .priv_ring = { .isr = gp10b_priv_ring_isr, }, - .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics, + .chip_init_gpu_characteristics = vgpu_gv11b_init_gpu_characteristics, .get_litter_value = gv11b_get_litter_value, }; -- cgit v1.2.2 From 5b368d3e46b946ed2a6b1b70ad2ac600740e582a Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 7 Nov 2017 10:47:20 -0800 Subject: gpu: nvgpu: gv1xx: Move fuse override DT handling Move fuse override DT handling to Linux code. All the chip specific fuse override functions did the same thing, so delete the HAL and call the same function to read the DT overrides on all chips. Also remove the fuse override functionality from dGPU. There are no DT entries for PCIe devices, so it would've failed anyway. JIRA NVGPU-259 Change-Id: Ic672e25090cdfc207d9771ab61b6cf53185113a4 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1593693 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/nvgpu/vgpu/gv11b') diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 5adb8ecd..a2c95edd 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -183,7 +183,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { .suspend_contexts = vgpu_gr_suspend_contexts, .resume_contexts = vgpu_gr_resume_contexts, .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags, - .fuse_override = gp10b_gr_fuse_override, .init_sm_id_table = gr_gv100_init_sm_id_table, .load_smid_config = gr_gv11b_load_smid_config, .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering, -- cgit v1.2.2 From 98bd673a7371940f24d37ad3a6d7b426995e737e Mon Sep 17 00:00:00 2001 From: Sami Kiminki Date: Fri, 15 Sep 2017 18:58:58 +0300 Subject: gpu: nvgpu: Remove PTE kind code for GV100/GV11B Remove gv11b_init_uncompressed_kind_map(), gv11b_init_kind_attr(), and the related kind setup code. They are not needed anymore. While we're doing these changes, remove a redundant assignment of g->bootstrap_owner in hal_gv100.c. Bug 1902982 Change-Id: Ib40d8f55cfbfa34143a3765c2b4913926ca021fd Signed-off-by: Sami Kiminki Reviewed-on: https://git-master.nvidia.com/r/1560931 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers/gpu/nvgpu/vgpu/gv11b') diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index a2c95edd..a496d3fc 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -636,8 +636,6 @@ int vgpu_gv11b_init_hal(struct gk20a *g) } __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); - gv11b_init_uncompressed_kind_map(); - gv11b_init_kind_attr(); g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; g->name = "gv11b"; -- cgit v1.2.2 From e590cf6c2c18d5bd7fca20186ded2a599c68c6c7 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 10 Nov 2017 10:59:26 -0800 Subject: gpu: nvgpu: gv11b: Do not assign GPU classes in vgpu HAL GPU class ids were moved to get_litter_value API, but vgpu was not updated to remove assigning them in HAL initialization. Remove the duplicate assignments. JIRA NVGPU-388 Change-Id: If75944517d1ea813496b1f2a12a1faf03406d8d0 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1596244 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 8 -------- 1 file changed, 8 deletions(-) (limited to 'drivers/gpu/nvgpu/vgpu/gv11b') diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index a496d3fc..b7c7cd2f 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -558,7 +558,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { int vgpu_gv11b_init_hal(struct gk20a *g) { struct gpu_ops *gops = &g->ops; - struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; u32 val; bool priv_security; @@ -640,12 +639,5 @@ int vgpu_gv11b_init_hal(struct gk20a *g) g->name = "gv11b"; - c->twod_class = FERMI_TWOD_A; - c->threed_class = VOLTA_A; - c->compute_class = VOLTA_COMPUTE_A; - c->gpfifo_class = VOLTA_CHANNEL_GPFIFO_A; - c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B; - c->dma_copy_class = VOLTA_DMA_COPY_A; - return 0; } -- cgit v1.2.2 From 0b0f80579c01a53768433ed1909d283719427429 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 10 Nov 2017 11:01:18 -0800 Subject: gpu: nvgpu: vgpu: Delete extra error print vgpu printed GPU characteristics flags at probe time. Delete the print in order to be able to remove GPU characteristics field. JIRA NVGPU-388 Change-Id: Ib08325e7a67598a4f6734f7e839d1b96ba10bd55 Signed-off-by: Terje Bergstrom Reviewed-on: https://git-master.nvidia.com/r/1596245 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'drivers/gpu/nvgpu/vgpu/gv11b') diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c index db3dfaf4..feac195e 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c @@ -25,9 +25,6 @@ int vgpu_gv11b_init_gpu_characteristics(struct gk20a *g) gk20a_dbg_fn(""); - - nvgpu_err(g, "g->gpu_characteristics.flags=%llx", - g->gpu_characteristics.flags); err = vgpu_init_gpu_characteristics(g); if (err) { nvgpu_err(g, "vgpu_init_gpu_characteristics failed, err %d\n", err); -- cgit v1.2.2 From af5e4a1bf63037e7618adfa11a950244df5883f2 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Wed, 15 Nov 2017 15:10:51 +0530 Subject: gpu: nvgpu: deprecate TSG/CHANNEL_SET_PRIORITY IOCTLs TSG/CHANNEL_SET_PRIORITY IOCTLs are deprecated and user space should be using combination of timeslice and interleave levels to decide the priority Hence remove the IOCTLs and all corresponding APIs Jira NVGPU-393 Change-Id: Idce925631653784e39864223dc418a99a7e7ca3c Signed-off-by: Deepak Nibade Reviewed-on: https://git-master.nvidia.com/r/1598582 Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/nvgpu/vgpu/gv11b') diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index b7c7cd2f..17d6f049 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c @@ -330,7 +330,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { .alloc_inst = vgpu_channel_alloc_inst, .free_inst = vgpu_channel_free_inst, .setup_ramfc = vgpu_channel_setup_ramfc, - .channel_set_priority = vgpu_channel_set_priority, .channel_set_timeslice = vgpu_channel_set_timeslice, .default_timeslice_us = vgpu_fifo_default_timeslice_us, .setup_userd = gk20a_fifo_setup_userd, -- cgit v1.2.2