From e14fdcd8f1f4125da697433b1744b1e4e4f15b09 Mon Sep 17 00:00:00 2001 From: Vaibhav Kachore Date: Fri, 6 Jul 2018 15:10:03 +0530 Subject: gpu: nvgpu: enable HWPM Mode-E context switch - Write new pm mode to context buffer header. Ucode use this mode to enable mode-e context switch. This is Mode-B context switch of PMs with Mode-E streamout on one context. If this mode is set, Ucode makes sure that Mode-E pipe (perfmons, routers, pma) is idle before it context switches PMs. - This allows us to collect counters in a secure way (i.e. on context basis) with stream out. Bug 2106999 Change-Id: I5a7435f09d1bf053ca428e538b0a57f3a175ac37 Signed-off-by: Vaibhav Kachore Reviewed-on: https://git-master.nvidia.com/r/1760366 Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/gpu/nvgpu/vgpu/gr_vgpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/nvgpu/vgpu/gr_vgpu.h') diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.h b/drivers/gpu/nvgpu/vgpu/gr_vgpu.h index c4b3944e..149bd17a 100644 --- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.h +++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.h @@ -58,7 +58,7 @@ int vgpu_gr_set_sm_debug_mode(struct gk20a *g, int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g, struct channel_gk20a *ch, bool enable); int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, - struct channel_gk20a *ch, u64 gpu_va, bool enable); + struct channel_gk20a *ch, u64 gpu_va, u32 mode); int vgpu_gr_clear_sm_error_state(struct gk20a *g, struct channel_gk20a *ch, u32 sm_id); int vgpu_gr_suspend_contexts(struct gk20a *g, -- cgit v1.2.2